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47 #include <rte_ethdev.h>
48 #include <rte_ether.h>
52 #ifndef FMAN_DEVICE_PATH
53 #define FMAN_DEVICE_PATH "/dev/mem"
56 #define MEMAC_NUM_OF_PADDRS 7 /* Num of additional exact match MAC adr regs */
58 /* Control and Configuration Register (COMMAND_CONFIG) for MEMAC */
59 #define CMD_CFG_LOOPBACK_EN 0x00000400
60 /**< 21 XGMII/GMII loopback enable */
61 #define CMD_CFG_PROMIS_EN 0x00000010
62 /**< 27 Promiscuous operation enable */
63 #define CMD_CFG_PAUSE_IGNORE 0x00000100
64 /**< 23 Ignore Pause frame quanta */
66 /* Statistics Configuration Register (STATN_CONFIG) */
67 #define STATS_CFG_CLR 0x00000004
68 /**< 29 Reset all counters */
69 #define STATS_CFG_CLR_ON_RD 0x00000002
70 /**< 30 Clear on read */
71 #define STATS_CFG_SATURATE 0x00000001
72 /**< 31 Saturate at the maximum val */
74 /**< Max receive frame length mask */
75 #define MAXFRM_SIZE_MEMAC 0x00007fe0
76 #define MAXFRM_RX_MASK 0x0000ffff
78 /**< Interface Mode Register Register for MEMAC */
79 #define IF_MODE_RLP 0x00000820
82 #define FMAN_PORT_MAX_EXT_POOLS_NUM 8
83 #define FMAN_PORT_OBS_EXT_POOLS_NUM 2
85 #define FMAN_PORT_CG_MAP_NUM 8
86 #define FMAN_PORT_PRS_RESULT_WORDS_NUM 8
87 #define FMAN_PORT_BMI_FIFO_UNITS 0x100
88 #define FMAN_PORT_IC_OFFSET_UNITS 0x10
90 #define FMAN_ENABLE_BPOOL_DEPLETION 0xF00000F0
92 #define HASH_CTRL_MCAST_EN 0x00000100
93 #define GROUP_ADDRESS 0x0000010000000000LL
94 #define HASH_CTRL_ADDR_MASK 0x0000003F
96 /* Pre definitions of FMAN interface and Bpool structures */
99 /* Lists of fman interfaces and bpools */
100 TAILQ_HEAD(rte_fman_if_list, __fman_if);
102 /* Represents the different flavour of network interface */
110 uint32_t mac_addr_l; /**< Lower 32 bits of 48-bit MAC address */
111 uint32_t mac_addr_u; /**< Upper 16 bits of 48-bit MAC address */
115 /* General Control and Status */
117 uint32_t command_config; /**< 0x008 Ctrl and cfg */
118 struct mac_addr mac_addr0; /**< 0x00C-0x010 MAC_ADDR_0...1 */
119 uint32_t maxfrm; /**< 0x014 Max frame length */
121 uint32_t hashtable_ctrl; /**< 0x02C Hash table control */
123 uint32_t ievent; /**< 0x040 Interrupt event */
124 uint32_t tx_ipg_length;
125 /**< 0x044 Transmitter inter-packet-gap */
127 uint32_t imask; /**< 0x04C Interrupt mask */
129 uint32_t pause_quanta[4]; /**< 0x054 Pause quanta */
130 uint32_t pause_thresh[4]; /**< 0x064 Pause quanta threshold */
131 uint32_t rx_pause_status; /**< 0x074 Receive pause status */
133 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];
134 /**< 0x80-0x0B4 mac padr */
135 uint32_t lpwake_timer;
136 /**< 0x0B8 Low Power Wakeup Timer */
137 uint32_t sleep_timer;
138 /**< 0x0BC Transmit EEE Low Power Timer */
140 uint32_t statn_config;
141 /**< 0x0E0 Statistics configuration */
143 /* Rx Statistics Counter */
144 uint32_t reoct_l; /**<Rx Eth Octets Counter */
146 uint32_t roct_l; /**<Rx Octet Counters */
148 uint32_t raln_l; /**<Rx Alignment Error Counter */
150 uint32_t rxpf_l; /**<Rx valid Pause Frame */
152 uint32_t rfrm_l; /**<Rx Frame counter */
154 uint32_t rfcs_l; /**<Rx frame check seq error */
156 uint32_t rvlan_l; /**<Rx Vlan Frame Counter */
158 uint32_t rerr_l; /**<Rx Frame error */
160 uint32_t ruca_l; /**<Rx Unicast */
162 uint32_t rmca_l; /**<Rx Multicast */
164 uint32_t rbca_l; /**<Rx Broadcast */
166 uint32_t rdrp_l; /**<Rx Dropper Packet */
168 uint32_t rpkt_l; /**<Rx packet */
170 uint32_t rund_l; /**<Rx undersized packets */
172 uint32_t r64_l; /**<Rx 64 byte */
186 uint32_t rovr_l; /**<Rx oversized but good */
188 uint32_t rjbr_l; /**<Rx oversized with bad csum */
190 uint32_t rfrg_l; /**<Rx fragment Packet */
192 uint32_t rcnp_l; /**<Rx control packets (0x8808 */
194 uint32_t rdrntp_l; /**<Rx dropped due to FIFO overflow */
196 uint32_t res01d0[12];
197 /* Tx Statistics Counter */
198 uint32_t teoct_l; /**<Tx eth octets */
200 uint32_t toct_l; /**<Tx Octets */
203 uint32_t txpf_l; /**<Tx valid pause frame */
205 uint32_t tfrm_l; /**<Tx frame counter */
207 uint32_t tfcs_l; /**<Tx FCS error */
209 uint32_t tvlan_l; /**<Tx Vlan Frame */
211 uint32_t terr_l; /**<Tx frame error */
213 uint32_t tuca_l; /**<Tx Unicast */
215 uint32_t tmca_l; /**<Tx Multicast */
217 uint32_t tbca_l; /**<Tx Broadcast */
220 uint32_t tpkt_l; /**<Tx Packet */
222 uint32_t tund_l; /**<Tx Undersized */
239 uint32_t tcnp_l; /**<Tx Control Packet type - 0x8808 */
241 uint32_t res02c8[14];
242 /* Line Interface Control */
243 uint32_t if_mode; /**< 0x300 Interface Mode Control */
244 uint32_t if_status; /**< 0x304 Interface Status */
245 uint32_t res0308[14];
247 uint32_t hg_config; /**< 0x340 Control and cfg */
249 uint32_t hg_pause_quanta; /**< 0x350 Pause quanta */
251 uint32_t hg_pause_thresh; /**< 0x360 Pause quanta threshold */
253 uint32_t hgrx_pause_status; /**< 0x370 Receive pause status */
254 uint32_t hg_fifos_status; /**< 0x374 fifos status */
255 uint32_t rhm; /**< 0x378 rx messages counter */
256 uint32_t thm; /**< 0x37C tx messages counter */
260 uint32_t fmbm_rcfg; /**< Rx Configuration */
261 uint32_t fmbm_rst; /**< Rx Status */
262 uint32_t fmbm_rda; /**< Rx DMA attributes*/
263 uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
264 uint32_t fmbm_rfed; /**< Rx Frame End Data*/
265 uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
266 uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/
267 uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/
268 uint32_t fmbm_rfne; /**< Rx Frame Next Engine*/
269 uint32_t fmbm_rfca; /**< Rx Frame Command Attributes.*/
270 uint32_t fmbm_rfpne; /**< Rx Frame Parser Next Engine*/
271 uint32_t fmbm_rpso; /**< Rx Parse Start Offset*/
272 uint32_t fmbm_rpp; /**< Rx Policer Profile */
273 uint32_t fmbm_rccb; /**< Rx Coarse Classification Base */
274 uint32_t fmbm_reth; /**< Rx Excessive Threshold */
275 uint32_t reserved003c[1]; /**< (0x03C 0x03F) */
276 uint32_t fmbm_rprai[FMAN_PORT_PRS_RESULT_WORDS_NUM];
277 /**< Rx Parse Results Array Init*/
278 uint32_t fmbm_rfqid; /**< Rx Frame Queue ID*/
279 uint32_t fmbm_refqid; /**< Rx Error Frame Queue ID*/
280 uint32_t fmbm_rfsdm; /**< Rx Frame Status Discard Mask*/
281 uint32_t fmbm_rfsem; /**< Rx Frame Status Error Mask*/
282 uint32_t fmbm_rfene; /**< Rx Frame Enqueue Next Engine */
283 uint32_t reserved0074[0x2]; /**< (0x074-0x07C) */
285 /**< Rx Frame Continuous Mode Next Engine */
286 uint32_t reserved0080[0x20];/**< (0x080 0x0FF) */
287 uint32_t fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM];
288 /**< Buffer Manager pool Information-*/
289 uint32_t fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM];
290 /**< Allocate Counter-*/
291 uint32_t reserved0130[8];
292 /**< 0x130/0x140 - 0x15F reserved -*/
293 uint32_t fmbm_rcgm[FMAN_PORT_CG_MAP_NUM];
294 /**< Congestion Group Map*/
295 uint32_t fmbm_mpd; /**< BM Pool Depletion */
296 uint32_t reserved0184[0x1F]; /**< (0x184 0x1FF) */
297 uint32_t fmbm_rstc; /**< Rx Statistics Counters*/
298 uint32_t fmbm_rfrc; /**< Rx Frame Counter*/
299 uint32_t fmbm_rfbc; /**< Rx Bad Frames Counter*/
300 uint32_t fmbm_rlfc; /**< Rx Large Frames Counter*/
301 uint32_t fmbm_rffc; /**< Rx Filter Frames Counter*/
302 uint32_t fmbm_rfdc; /**< Rx Frame Discard Counter*/
303 uint32_t fmbm_rfldec; /**< Rx Frames List DMA Error Counter*/
304 uint32_t fmbm_rodc; /**< Rx Out of Buffers Discard nntr*/
305 uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter*/
306 uint32_t reserved0224[0x17]; /**< (0x224 0x27F) */
307 uint32_t fmbm_rpc; /**< Rx Performance Counters*/
308 uint32_t fmbm_rpcp; /**< Rx Performance Count Parameters*/
309 uint32_t fmbm_rccn; /**< Rx Cycle Counter*/
310 uint32_t fmbm_rtuc; /**< Rx Tasks Utilization Counter*/
312 /**< Rx Receive Queue Utilization cntr*/
313 uint32_t fmbm_rduc; /**< Rx DMA Utilization Counter*/
314 uint32_t fmbm_rfuc; /**< Rx FIFO Utilization Counter*/
315 uint32_t fmbm_rpac; /**< Rx Pause Activation Counter*/
316 uint32_t reserved02a0[0x18]; /**< (0x2A0 0x2FF) */
317 uint32_t fmbm_rdbg; /**< Rx Debug-*/
320 struct fman_port_qmi_regs {
321 uint32_t fmqm_pnc; /**< PortID n Configuration Register */
322 uint32_t fmqm_pns; /**< PortID n Status Register */
323 uint32_t fmqm_pnts; /**< PortID n Task Status Register */
324 uint32_t reserved00c[4]; /**< 0xn00C - 0xn01B */
325 uint32_t fmqm_pnen; /**< PortID n Enqueue NIA Register */
326 uint32_t fmqm_pnetfc; /**< PortID n Enq Total Frame Counter */
327 uint32_t reserved024[2]; /**< 0xn024 - 0x02B */
328 uint32_t fmqm_pndn; /**< PortID n Dequeue NIA Register */
329 uint32_t fmqm_pndc; /**< PortID n Dequeue Config Register */
330 uint32_t fmqm_pndtfc; /**< PortID n Dequeue tot Frame cntr */
331 uint32_t fmqm_pndfdc; /**< PortID n Dequeue FQID Dflt Cntr */
332 uint32_t fmqm_pndcc; /**< PortID n Dequeue Confirm Counter */
335 /* This struct exports parameters about an Fman network interface, determined
336 * from the device-tree.
339 /* Which Fman this interface belongs to */
341 /* The type/speed of the interface */
342 enum fman_mac_type mac_type;
343 /* Boolean, set when mac type is memac */
345 /* Boolean, set when PHY is RGMII */
347 /* The index of this MAC (within the Fman it belongs to) */
349 /* The MAC address */
350 struct ether_addr mac_addr;
351 /* The Qman channel to schedule Tx FQs to */
353 /* The hard-coded FQIDs for this interface. Note: this doesn't cover
354 * the PCD nor the "Rx default" FQIDs, which are configured via FMC
355 * and its XML-based configuration.
357 uint32_t fqid_rx_def;
358 uint32_t fqid_rx_err;
359 uint32_t fqid_tx_err;
360 uint32_t fqid_tx_confirm;
362 struct list_head bpool_list;
363 /* The node for linking this interface into "fman_if_list" */
364 struct list_head node;
367 /* This struct exposes parameters for buffer pools, extracted from the network
368 * interface settings in the device tree.
370 struct fman_if_bpool {
375 /* The node for linking this bpool into fman_if::bpool_list */
376 struct list_head node;
379 /* Internal Context transfer params - FMBM_RICP*/
380 struct fman_if_ic_params {
381 /*IC offset in the packet buffer */
383 /*IC internal offset */
389 /* The exported "struct fman_if" type contains the subset of fields we want
390 * exposed. This struct is embedded in a larger "struct __fman_if" which
391 * contains the extra bits we *don't* want exposed.
395 char node_path[PATH_MAX];
400 struct list_head node;
403 /* And this is the base list node that the interfaces are added to. (See
404 * fman_if_enable_all_rx() below for an example of its use.)
406 extern const struct list_head *fman_if_list;
408 extern int fman_ccsr_map_fd;
410 /* To iterate the "bpool_list" for an interface. Eg;
411 * struct fman_if *p = get_ptr_to_some_interface();
412 * struct fman_if_bpool *bp;
413 * printf("Interface uses following BPIDs;\n");
414 * fman_if_for_each_bpool(bp, p) {
415 * printf(" %d\n", bp->bpid);
419 #define fman_if_for_each_bpool(bp, __if) \
420 list_for_each_entry(bp, &(__if)->bpool_list, node)
422 #define FMAN_ERR(rc, fmt, args...) \
425 DPAA_BUS_LOG(ERR, fmt "(%d)", ##args, errno); \
428 #define FMAN_IP_REV_1 0xC30C4
429 #define FMAN_IP_REV_1_MAJOR_MASK 0x0000FF00
430 #define FMAN_IP_REV_1_MAJOR_SHIFT 8
432 #define FMAN_V3_CONTEXTA_EN_A2V 0x10000000
433 #define FMAN_V3_CONTEXTA_EN_OVOM 0x02000000
434 #define FMAN_V3_CONTEXTA_EN_EBD 0x80000000
435 #define FMAN_CONTEXTA_DIS_CHECKSUM 0x7ull
436 #define FMAN_CONTEXTA_SET_OPCODE11 0x2000000b00000000
437 extern u16 fman_ip_rev;
438 extern u32 fman_dealloc_bufs_mask_hi;
439 extern u32 fman_dealloc_bufs_mask_lo;
442 * Initialize the FMAN driver
446 * 0 for success; error OTHERWISE
451 * Teardown the FMAN driver
456 void fman_finish(void);
458 #endif /* __FMAN_H */