1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2019 NXP
17 #include <sys/types.h>
18 #include <sys/queue.h>
19 #include <sys/ioctl.h>
22 #include <sys/epoll.h>
23 #include <sys/eventfd.h>
24 #include <sys/syscall.h>
27 #include <ethdev_driver.h>
28 #include <rte_malloc.h>
29 #include <rte_memcpy.h>
30 #include <rte_string_fns.h>
31 #include <rte_cycles.h>
32 #include <rte_kvargs.h>
35 #include <fslmc_logs.h>
36 #include <rte_fslmc.h>
37 #include "dpaa2_hw_pvt.h"
38 #include "dpaa2_hw_dpio.h"
39 #include <mc/fsl_dpmng.h>
41 #define NUM_HOST_CPUS RTE_MAX_LCORE
43 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
44 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
46 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
48 TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev);
49 static struct dpio_dev_list dpio_dev_list
50 = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */
51 static uint32_t io_space_count;
53 /* Variable to store DPAA2 platform type */
54 uint32_t dpaa2_svr_family;
56 /* Variable to store DPAA2 DQRR size */
57 uint8_t dpaa2_dqrr_size;
58 /* Variable to store DPAA2 EQCR size */
59 uint8_t dpaa2_eqcr_size;
61 /* Variable to hold the portal_key, once created.*/
62 static pthread_key_t dpaa2_portal_key;
64 /*Stashing Macros default for LS208x*/
65 static int dpaa2_core_cluster_base = 0x04;
66 static int dpaa2_cluster_sz = 2;
68 /* For LS208X platform There are four clusters with following mapping:
69 * Cluster 1 (ID = x04) : CPU0, CPU1;
70 * Cluster 2 (ID = x05) : CPU2, CPU3;
71 * Cluster 3 (ID = x06) : CPU4, CPU5;
72 * Cluster 4 (ID = x07) : CPU6, CPU7;
74 /* For LS108X platform There are two clusters with following mapping:
75 * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
76 * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
78 /* For LX2160 platform There are four clusters with following mapping:
79 * Cluster 1 (ID = x00) : CPU0, CPU1;
80 * Cluster 2 (ID = x01) : CPU2, CPU3;
81 * Cluster 3 (ID = x02) : CPU4, CPU5;
82 * Cluster 4 (ID = x03) : CPU6, CPU7;
83 * Cluster 1 (ID = x04) : CPU8, CPU9;
84 * Cluster 2 (ID = x05) : CPU10, CP11;
85 * Cluster 3 (ID = x06) : CPU12, CPU13;
86 * Cluster 4 (ID = x07) : CPU14, CPU15;
90 dpaa2_get_core_id(void)
93 int i, ret, cpu_id = -1;
95 ret = pthread_getaffinity_np(pthread_self(), sizeof(cpu_set_t),
98 DPAA2_BUS_ERR("pthread_getaffinity_np() failed");
102 for (i = 0; i < RTE_MAX_LCORE; i++) {
103 if (CPU_ISSET(i, &cpuset)) {
107 /* Multiple cpus are affined */
116 dpaa2_core_cluster_sdest(int cpu_id)
118 int x = cpu_id / dpaa2_cluster_sz;
120 return dpaa2_core_cluster_base + x;
123 #ifdef RTE_EVENT_DPAA2
125 dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id, int cpu_id)
127 #define STRING_LEN 28
128 #define COMMAND_LEN 50
129 uint32_t cpu_mask = 1;
132 char *temp = NULL, *token = NULL;
133 char string[STRING_LEN], command[COMMAND_LEN];
136 snprintf(string, STRING_LEN, "dpio.%d", dpio_id);
137 file = fopen("/proc/interrupts", "r");
139 DPAA2_BUS_WARN("Failed to open /proc/interrupts file");
142 while (getline(&temp, &len, file) != -1) {
143 if ((strstr(temp, string)) != NULL) {
144 token = strtok(temp, ":");
150 DPAA2_BUS_WARN("Failed to get interrupt id for dpio.%d",
158 cpu_mask = cpu_mask << cpu_id;
159 snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity",
161 ret = system(command);
164 "Failed to affine interrupts on respective core");
166 DPAA2_BUS_DEBUG(" %s command is executed", command);
172 static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev)
174 struct epoll_event epoll_ev;
175 int eventfd, dpio_epoll_fd, ret;
176 int threshold = 0x3, timeout = 0xFF;
178 dpio_epoll_fd = epoll_create(1);
179 ret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0);
181 DPAA2_BUS_ERR("Interrupt registeration failed");
185 if (getenv("DPAA2_PORTAL_INTR_THRESHOLD"))
186 threshold = atoi(getenv("DPAA2_PORTAL_INTR_THRESHOLD"));
188 if (getenv("DPAA2_PORTAL_INTR_TIMEOUT"))
189 sscanf(getenv("DPAA2_PORTAL_INTR_TIMEOUT"), "%x", &timeout);
191 qbman_swp_interrupt_set_trigger(dpio_dev->sw_portal,
192 QBMAN_SWP_INTERRUPT_DQRI);
193 qbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff);
194 qbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0);
195 qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);
196 qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);
198 eventfd = dpio_dev->intr_handle.fd;
199 epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;
200 epoll_ev.data.fd = eventfd;
202 ret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev);
204 DPAA2_BUS_ERR("epoll_ctl failed");
207 dpio_dev->epoll_fd = dpio_epoll_fd;
212 static void dpaa2_dpio_intr_deinit(struct dpaa2_dpio_dev *dpio_dev)
216 ret = rte_dpaa2_intr_disable(&dpio_dev->intr_handle, 0);
218 DPAA2_BUS_ERR("DPIO interrupt disable failed");
220 close(dpio_dev->epoll_fd);
225 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
229 /* Set the STASH Destination depending on Current CPU ID.
230 * Valid values of SDEST are 4,5,6,7. Where,
232 sdest = dpaa2_core_cluster_sdest(cpu_id);
233 DPAA2_BUS_DEBUG("Portal= %d CPU= %u SDEST= %d",
234 dpio_dev->index, cpu_id, sdest);
236 ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
237 dpio_dev->token, sdest);
239 DPAA2_BUS_ERR("%d ERROR in SDEST", ret);
243 #ifdef RTE_EVENT_DPAA2
244 if (dpaa2_dpio_intr_init(dpio_dev)) {
245 DPAA2_BUS_ERR("Interrupt registration failed for dpio");
248 dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id, cpu_id);
254 static void dpaa2_put_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
257 #ifdef RTE_EVENT_DPAA2
258 dpaa2_dpio_intr_deinit(dpio_dev);
260 rte_atomic16_clear(&dpio_dev->ref_count);
264 static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
266 struct dpaa2_dpio_dev *dpio_dev = NULL;
270 /* Get DPIO dev handle from list using index */
271 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
272 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
276 DPAA2_BUS_ERR("No software portal resource left");
280 DPAA2_BUS_DEBUG("New Portal %p (%d) affined thread - %u",
281 dpio_dev, dpio_dev->index, rte_gettid());
283 /* Set the Stashing Destination */
284 cpu_id = dpaa2_get_core_id();
286 DPAA2_BUS_WARN("Thread not affined to a single core");
287 if (dpaa2_svr_family != SVR_LX2160A)
288 qbman_swp_update(dpio_dev->sw_portal, 1);
290 ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
292 DPAA2_BUS_ERR("dpaa2_configure_stashing failed");
293 rte_atomic16_clear(&dpio_dev->ref_count);
298 ret = pthread_setspecific(dpaa2_portal_key, (void *)dpio_dev);
300 DPAA2_BUS_ERR("pthread_setspecific failed with ret: %d", ret);
301 dpaa2_put_qbman_swp(dpio_dev);
309 dpaa2_affine_qbman_swp(void)
311 struct dpaa2_dpio_dev *dpio_dev;
312 uint64_t tid = rte_gettid();
314 /* Populate the dpaa2_io_portal structure */
315 if (!RTE_PER_LCORE(_dpaa2_io).dpio_dev) {
316 dpio_dev = dpaa2_get_qbman_swp();
318 DPAA2_BUS_ERR("Error in software portal allocation");
321 RTE_PER_LCORE(_dpaa2_io).dpio_dev = dpio_dev;
324 "DPAA Portal=%p (%d) is affined to thread %" PRIu64,
325 dpio_dev, dpio_dev->index, tid);
331 dpaa2_affine_qbman_ethrx_swp(void)
333 struct dpaa2_dpio_dev *dpio_dev;
334 uint64_t tid = rte_gettid();
336 /* Populate the dpaa2_io_portal structure */
337 if (!RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev) {
338 dpio_dev = dpaa2_get_qbman_swp();
340 DPAA2_BUS_ERR("Error in software portal allocation");
343 RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev = dpio_dev;
346 "DPAA Portal=%p (%d) is affined for eth rx to thread %"
347 PRIu64, dpio_dev, dpio_dev->index, tid);
352 static void dpaa2_portal_finish(void *arg)
356 dpaa2_put_qbman_swp(RTE_PER_LCORE(_dpaa2_io).dpio_dev);
357 dpaa2_put_qbman_swp(RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev);
359 pthread_setspecific(dpaa2_portal_key, NULL);
363 dpaa2_create_dpio_device(int vdev_fd,
364 struct vfio_device_info *obj_info,
367 struct dpaa2_dpio_dev *dpio_dev = NULL;
368 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
369 struct qbman_swp_desc p_des;
370 struct dpio_attr attr;
373 if (obj_info->num_regions < NUM_DPIO_REGIONS) {
374 DPAA2_BUS_ERR("Not sufficient number of DPIO regions");
378 dpio_dev = rte_zmalloc(NULL, sizeof(struct dpaa2_dpio_dev),
379 RTE_CACHE_LINE_SIZE);
381 DPAA2_BUS_ERR("Memory allocation failed for DPIO Device");
385 dpio_dev->dpio = NULL;
386 dpio_dev->hw_id = object_id;
387 rte_atomic16_init(&dpio_dev->ref_count);
388 /* Using single portal for all devices */
389 dpio_dev->mc_portal = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
391 dpio_dev->dpio = rte_zmalloc(NULL, sizeof(struct fsl_mc_io),
392 RTE_CACHE_LINE_SIZE);
393 if (!dpio_dev->dpio) {
394 DPAA2_BUS_ERR("Memory allocation failure");
398 dpio_dev->dpio->regs = dpio_dev->mc_portal;
399 if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
401 DPAA2_BUS_ERR("Failed to allocate IO space");
405 if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
406 DPAA2_BUS_ERR("Failed to reset dpio");
410 if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
411 DPAA2_BUS_ERR("Failed to Enable dpio");
415 if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
416 dpio_dev->token, &attr)) {
417 DPAA2_BUS_ERR("DPIO Get attribute failed");
421 /* find the SoC type for the first time */
422 if (!dpaa2_svr_family) {
423 struct mc_soc_version mc_plat_info = {0};
425 if (mc_get_soc_version(dpio_dev->dpio,
426 CMD_PRI_LOW, &mc_plat_info)) {
427 DPAA2_BUS_ERR("Unable to get SoC version information");
428 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) {
429 dpaa2_core_cluster_base = 0x02;
430 dpaa2_cluster_sz = 4;
431 DPAA2_BUS_DEBUG("LS108x (A53) Platform Detected");
432 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LX2160A) {
433 dpaa2_core_cluster_base = 0x00;
434 dpaa2_cluster_sz = 2;
435 DPAA2_BUS_DEBUG("LX2160 Platform Detected");
437 dpaa2_svr_family = (mc_plat_info.svr & 0xffff0000);
439 if (dpaa2_svr_family == SVR_LX2160A) {
440 dpaa2_dqrr_size = DPAA2_LX2_DQRR_RING_SIZE;
441 dpaa2_eqcr_size = DPAA2_LX2_EQCR_RING_SIZE;
443 dpaa2_dqrr_size = DPAA2_DQRR_RING_SIZE;
444 dpaa2_eqcr_size = DPAA2_EQCR_RING_SIZE;
448 if (dpaa2_svr_family == SVR_LX2160A)
449 reg_info.index = DPAA2_SWP_CENA_MEM_REGION;
451 reg_info.index = DPAA2_SWP_CENA_REGION;
453 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
454 DPAA2_BUS_ERR("vfio: error getting region info");
458 dpio_dev->ce_size = reg_info.size;
459 dpio_dev->qbman_portal_ce_paddr = (size_t)mmap(NULL, reg_info.size,
460 PROT_WRITE | PROT_READ, MAP_SHARED,
461 vdev_fd, reg_info.offset);
463 reg_info.index = DPAA2_SWP_CINH_REGION;
464 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
465 DPAA2_BUS_ERR("vfio: error getting region info");
469 dpio_dev->ci_size = reg_info.size;
470 dpio_dev->qbman_portal_ci_paddr = (size_t)mmap(NULL, reg_info.size,
471 PROT_WRITE | PROT_READ, MAP_SHARED,
472 vdev_fd, reg_info.offset);
474 /* Configure & setup SW portal */
476 p_des.idx = attr.qbman_portal_id;
477 p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
478 p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
480 p_des.qman_version = attr.qbman_version;
481 p_des.eqcr_mode = qman_eqcr_vb_ring;
482 p_des.cena_access_mode = qman_cena_fastest_access;
484 dpio_dev->sw_portal = qbman_swp_init(&p_des);
485 if (dpio_dev->sw_portal == NULL) {
486 DPAA2_BUS_ERR("QBMan SW Portal Init failed");
491 dpio_dev->index = io_space_count;
493 if (rte_dpaa2_vfio_setup_intr(&dpio_dev->intr_handle, vdev_fd, 1)) {
494 DPAA2_BUS_ERR("Fail to setup interrupt for %d",
499 dpio_dev->eqresp = rte_zmalloc(NULL, MAX_EQ_RESP_ENTRIES *
500 (sizeof(struct qbman_result) +
501 sizeof(struct eqresp_metadata)),
502 RTE_CACHE_LINE_SIZE);
503 if (!dpio_dev->eqresp) {
504 DPAA2_BUS_ERR("Memory allocation failed for eqresp");
507 dpio_dev->eqresp_meta = (struct eqresp_metadata *)(dpio_dev->eqresp +
508 MAX_EQ_RESP_ENTRIES);
511 TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);
513 if (!dpaa2_portal_key) {
514 /* create the key, supplying a function that'll be invoked
515 * when a portal affined thread will be deleted.
517 ret = pthread_key_create(&dpaa2_portal_key,
518 dpaa2_portal_finish);
520 DPAA2_BUS_DEBUG("Unable to create pthread key (%d)",
529 if (dpio_dev->dpio) {
530 if (dpio_dev->token) {
531 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW,
533 dpio_close(dpio_dev->dpio, CMD_PRI_LOW,
537 rte_free(dpio_dev->eqresp);
538 rte_free(dpio_dev->dpio);
543 /* For each element in the list, cleanup */
544 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
545 if (dpio_dev->dpio) {
546 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW,
548 dpio_close(dpio_dev->dpio, CMD_PRI_LOW,
550 rte_free(dpio_dev->dpio);
555 /* Preventing re-use of the list with old entries */
556 TAILQ_INIT(&dpio_dev_list);
562 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
566 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
567 if (q_storage->dq_storage[i])
568 rte_free(q_storage->dq_storage[i]);
573 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
577 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
578 q_storage->dq_storage[i] = rte_malloc(NULL,
579 dpaa2_dqrr_size * sizeof(struct qbman_result),
580 RTE_CACHE_LINE_SIZE);
581 if (!q_storage->dq_storage[i])
587 rte_free(q_storage->dq_storage[i]);
593 dpaa2_free_eq_descriptors(void)
595 struct dpaa2_dpio_dev *dpio_dev = DPAA2_PER_LCORE_DPIO;
596 struct qbman_result *eqresp;
597 struct eqresp_metadata *eqresp_meta;
598 struct dpaa2_queue *txq;
600 while (dpio_dev->eqresp_ci != dpio_dev->eqresp_pi) {
601 eqresp = &dpio_dev->eqresp[dpio_dev->eqresp_ci];
602 eqresp_meta = &dpio_dev->eqresp_meta[dpio_dev->eqresp_ci];
604 if (!qbman_result_eqresp_rspid(eqresp))
607 if (qbman_result_eqresp_rc(eqresp)) {
608 txq = eqresp_meta->dpaa2_q;
609 txq->cb_eqresp_free(dpio_dev->eqresp_ci);
611 qbman_result_eqresp_set_rspid(eqresp, 0);
613 dpio_dev->eqresp_ci + 1 < MAX_EQ_RESP_ENTRIES ?
614 dpio_dev->eqresp_ci++ : (dpio_dev->eqresp_ci = 0);
617 /* Return 1 less entry so that PI and CI are never same in a
618 * case there all the EQ responses are in use.
620 if (dpio_dev->eqresp_ci > dpio_dev->eqresp_pi)
621 return dpio_dev->eqresp_ci - dpio_dev->eqresp_pi - 1;
623 return dpio_dev->eqresp_ci - dpio_dev->eqresp_pi +
624 MAX_EQ_RESP_ENTRIES - 1;
627 static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
628 .dev_type = DPAA2_IO,
629 .create = dpaa2_create_dpio_device,
632 RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);