4 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
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43 #include <sys/types.h>
44 #include <sys/queue.h>
45 #include <sys/ioctl.h>
48 #include <sys/syscall.h>
49 #include <sys/epoll.h>
50 #include<sys/eventfd.h>
53 #include <rte_ethdev.h>
54 #include <rte_malloc.h>
55 #include <rte_memcpy.h>
56 #include <rte_string_fns.h>
57 #include <rte_cycles.h>
58 #include <rte_kvargs.h>
60 #include <rte_ethdev.h>
62 #include <fslmc_logs.h>
63 #include <fslmc_vfio.h>
64 #include "dpaa2_hw_pvt.h"
65 #include "dpaa2_hw_dpio.h"
66 #include <mc/fsl_dpmng.h>
68 #define NUM_HOST_CPUS RTE_MAX_LCORE
70 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
71 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
73 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
75 TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev);
76 static struct dpio_dev_list dpio_dev_list
77 = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */
78 static uint32_t io_space_count;
80 /*Stashing Macros default for LS208x*/
81 static int dpaa2_core_cluster_base = 0x04;
82 static int dpaa2_cluster_sz = 2;
84 /* For LS208X platform There are four clusters with following mapping:
85 * Cluster 1 (ID = x04) : CPU0, CPU1;
86 * Cluster 2 (ID = x05) : CPU2, CPU3;
87 * Cluster 3 (ID = x06) : CPU4, CPU5;
88 * Cluster 4 (ID = x07) : CPU6, CPU7;
90 /* For LS108X platform There are two clusters with following mapping:
91 * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
92 * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
95 /* Set the STASH Destination depending on Current CPU ID.
96 * e.g. Valid values of SDEST are 4,5,6,7. Where,
97 * CPU 0-1 will have SDEST 4
98 * CPU 2-3 will have SDEST 5.....and so on.
101 dpaa2_core_cluster_sdest(int cpu_id)
103 int x = cpu_id / dpaa2_cluster_sz;
108 return dpaa2_core_cluster_base + x;
111 static void dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id)
113 #define STRING_LEN 28
114 #define COMMAND_LEN 50
115 uint32_t cpu_mask = 1;
118 char *temp = NULL, *token = NULL;
119 char string[STRING_LEN], command[COMMAND_LEN];
122 snprintf(string, STRING_LEN, "dpio.%d", dpio_id);
123 file = fopen("/proc/interrupts", "r");
125 PMD_DRV_LOG(WARNING, "Failed to open /proc/interrupts file\n");
128 while (getline(&temp, &len, file) != -1) {
129 if ((strstr(temp, string)) != NULL) {
130 token = strtok(temp, ":");
136 PMD_DRV_LOG(WARNING, "Failed to get interrupt id for dpio.%d\n",
144 cpu_mask = cpu_mask << rte_lcore_id();
145 snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity",
147 ret = system(command);
150 "Failed to affine interrupts on respective core\n");
152 PMD_DRV_LOG(WARNING, " %s command is executed\n", command);
158 static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev)
160 struct epoll_event epoll_ev;
161 int eventfd, dpio_epoll_fd, ret;
162 int threshold = 0x3, timeout = 0xFF;
164 dpio_epoll_fd = epoll_create(1);
165 ret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0);
167 PMD_DRV_LOG(ERR, "Interrupt registeration failed\n");
171 if (getenv("DPAA2_PORTAL_INTR_THRESHOLD"))
172 threshold = atoi(getenv("DPAA2_PORTAL_INTR_THRESHOLD"));
174 if (getenv("DPAA2_PORTAL_INTR_TIMEOUT"))
175 sscanf(getenv("DPAA2_PORTAL_INTR_TIMEOUT"), "%x", &timeout);
177 qbman_swp_interrupt_set_trigger(dpio_dev->sw_portal,
178 QBMAN_SWP_INTERRUPT_DQRI);
179 qbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff);
180 qbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0);
181 qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);
182 qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);
184 eventfd = dpio_dev->intr_handle.fd;
185 epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;
186 epoll_ev.data.fd = eventfd;
188 ret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev);
190 PMD_DRV_LOG(ERR, "epoll_ctl failed\n");
193 dpio_dev->epoll_fd = dpio_epoll_fd;
195 dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id);
201 configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
203 struct qbman_swp_desc p_des;
204 struct dpio_attr attr;
206 dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io));
207 if (!dpio_dev->dpio) {
208 PMD_INIT_LOG(ERR, "Memory allocation failure\n");
212 PMD_DRV_LOG(DEBUG, "\t Allocated DPIO Portal[%p]", dpio_dev->dpio);
213 dpio_dev->dpio->regs = dpio_dev->mc_portal;
214 if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
216 PMD_INIT_LOG(ERR, "Failed to allocate IO space\n");
217 free(dpio_dev->dpio);
221 if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
222 PMD_INIT_LOG(ERR, "Failed to reset dpio\n");
223 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
224 free(dpio_dev->dpio);
228 if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
229 PMD_INIT_LOG(ERR, "Failed to Enable dpio\n");
230 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
231 free(dpio_dev->dpio);
235 if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
236 dpio_dev->token, &attr)) {
237 PMD_INIT_LOG(ERR, "DPIO Get attribute failed\n");
238 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
239 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
240 free(dpio_dev->dpio);
244 PMD_INIT_LOG(DEBUG, "Qbman Portal ID %d", attr.qbman_portal_id);
246 /* Configure & setup SW portal */
248 p_des.idx = attr.qbman_portal_id;
249 p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
250 p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
252 p_des.qman_version = attr.qbman_version;
254 dpio_dev->sw_portal = qbman_swp_init(&p_des);
255 if (dpio_dev->sw_portal == NULL) {
256 PMD_DRV_LOG(ERR, " QBMan SW Portal Init failed\n");
257 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
258 free(dpio_dev->dpio);
266 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
269 static int first_time;
271 /* find the SoC type for the first time */
273 struct mc_soc_version mc_plat_info = {0};
275 if (mc_get_soc_version(dpio_dev->dpio,
276 CMD_PRI_LOW, &mc_plat_info)) {
277 PMD_INIT_LOG(ERR, "\tmc_get_soc_version failed\n");
278 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) {
279 dpaa2_core_cluster_base = 0x02;
280 dpaa2_cluster_sz = 4;
281 PMD_INIT_LOG(DEBUG, "\tLS108x (A53) Platform Detected");
286 /* Set the Stashing Destination */
288 cpu_id = rte_get_master_lcore();
290 RTE_LOG(ERR, PMD, "\tGetting CPU Index failed\n");
294 /* Set the STASH Destination depending on Current CPU ID.
295 * Valid values of SDEST are 4,5,6,7. Where,
298 sdest = dpaa2_core_cluster_sdest(cpu_id);
299 PMD_DRV_LOG(DEBUG, "Portal= %d CPU= %u SDEST= %d",
300 dpio_dev->index, cpu_id, sdest);
302 ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
303 dpio_dev->token, sdest);
305 PMD_DRV_LOG(ERR, "%d ERROR in SDEST\n", ret);
309 if (dpaa2_dpio_intr_init(dpio_dev)) {
310 PMD_DRV_LOG(ERR, "Interrupt registration failed for dpio\n");
317 struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
319 struct dpaa2_dpio_dev *dpio_dev = NULL;
322 /* Get DPIO dev handle from list using index */
323 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
324 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
330 PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu",
331 dpio_dev, dpio_dev->index, syscall(SYS_gettid));
333 ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
335 PMD_DRV_LOG(ERR, "dpaa2_configure_stashing failed");
341 dpaa2_affine_qbman_swp(void)
343 unsigned int lcore_id = rte_lcore_id();
344 uint64_t tid = syscall(SYS_gettid);
346 if (lcore_id == LCORE_ID_ANY)
347 lcore_id = rte_get_master_lcore();
348 /* if the core id is not supported */
349 else if (lcore_id >= RTE_MAX_LCORE)
352 if (dpaa2_io_portal[lcore_id].dpio_dev) {
353 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
354 " between thread %lu and current %lu",
355 dpaa2_io_portal[lcore_id].dpio_dev,
356 dpaa2_io_portal[lcore_id].dpio_dev->index,
357 dpaa2_io_portal[lcore_id].net_tid,
359 RTE_PER_LCORE(_dpaa2_io).dpio_dev
360 = dpaa2_io_portal[lcore_id].dpio_dev;
361 rte_atomic16_inc(&dpaa2_io_portal
362 [lcore_id].dpio_dev->ref_count);
363 dpaa2_io_portal[lcore_id].net_tid = tid;
365 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
366 dpaa2_io_portal[lcore_id].dpio_dev,
367 dpaa2_io_portal[lcore_id].dpio_dev->index,
372 /* Populate the dpaa2_io_portal structure */
373 dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id);
375 if (dpaa2_io_portal[lcore_id].dpio_dev) {
376 RTE_PER_LCORE(_dpaa2_io).dpio_dev
377 = dpaa2_io_portal[lcore_id].dpio_dev;
378 dpaa2_io_portal[lcore_id].net_tid = tid;
387 dpaa2_affine_qbman_swp_sec(void)
389 unsigned int lcore_id = rte_lcore_id();
390 uint64_t tid = syscall(SYS_gettid);
392 if (lcore_id == LCORE_ID_ANY)
393 lcore_id = rte_get_master_lcore();
394 /* if the core id is not supported */
395 else if (lcore_id >= RTE_MAX_LCORE)
398 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
399 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
400 " between thread %lu and current %lu",
401 dpaa2_io_portal[lcore_id].sec_dpio_dev,
402 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
403 dpaa2_io_portal[lcore_id].sec_tid,
405 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
406 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
407 rte_atomic16_inc(&dpaa2_io_portal
408 [lcore_id].sec_dpio_dev->ref_count);
409 dpaa2_io_portal[lcore_id].sec_tid = tid;
411 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
412 dpaa2_io_portal[lcore_id].sec_dpio_dev,
413 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
418 /* Populate the dpaa2_io_portal structure */
419 dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp(lcore_id);
421 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
422 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
423 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
424 dpaa2_io_portal[lcore_id].sec_tid = tid;
432 dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev,
433 struct vfio_device_info *obj_info,
436 struct dpaa2_dpio_dev *dpio_dev;
437 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
440 if (obj_info->num_regions < NUM_DPIO_REGIONS) {
441 PMD_INIT_LOG(ERR, "ERROR, Not sufficient number "
442 "of DPIO regions.\n");
446 dpio_dev = rte_malloc(NULL, sizeof(struct dpaa2_dpio_dev),
447 RTE_CACHE_LINE_SIZE);
449 PMD_INIT_LOG(ERR, "Memory allocation failed for DPIO Device\n");
453 dpio_dev->dpio = NULL;
454 dpio_dev->hw_id = object_id;
455 dpio_dev->intr_handle.vfio_dev_fd = vdev->fd;
456 rte_atomic16_init(&dpio_dev->ref_count);
457 /* Using single portal for all devices */
458 dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX];
461 vfio_dev_fd = dpio_dev->intr_handle.vfio_dev_fd;
462 if (ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
463 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
468 dpio_dev->ce_size = reg_info.size;
469 dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,
470 PROT_WRITE | PROT_READ, MAP_SHARED,
471 vfio_dev_fd, reg_info.offset);
473 /* Create Mapping for QBMan Cache Enabled area. This is a fix for
474 * SMMU fault for DQRR statshing transaction.
476 if (vfio_dmamap_mem_region(dpio_dev->qbman_portal_ce_paddr,
477 reg_info.offset, reg_info.size)) {
478 PMD_INIT_LOG(ERR, "DMAMAP for Portal CE area failed.\n");
484 if (ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
485 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
490 dpio_dev->ci_size = reg_info.size;
491 dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,
492 PROT_WRITE | PROT_READ, MAP_SHARED,
493 vfio_dev_fd, reg_info.offset);
495 if (configure_dpio_qbman_swp(dpio_dev)) {
497 "Fail to configure the dpio qbman portal for %d\n",
504 dpio_dev->index = io_space_count;
505 TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);
506 PMD_INIT_LOG(DEBUG, "DPAA2: Added [dpio-%d]", object_id);
512 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
516 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
517 if (q_storage->dq_storage[i])
518 rte_free(q_storage->dq_storage[i]);
523 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
527 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
528 q_storage->dq_storage[i] = rte_malloc(NULL,
529 DPAA2_DQRR_RING_SIZE * sizeof(struct qbman_result),
530 RTE_CACHE_LINE_SIZE);
531 if (!q_storage->dq_storage[i])
537 rte_free(q_storage->dq_storage[i]);
542 static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
543 .object_id = DPAA2_MC_DPIO_DEVID,
544 .create = dpaa2_create_dpio_device,
547 RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);