1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
17 #include <sys/types.h>
18 #include <sys/queue.h>
19 #include <sys/ioctl.h>
22 #include <sys/syscall.h>
23 #include <sys/epoll.h>
24 #include<sys/eventfd.h>
27 #include <rte_ethdev.h>
28 #include <rte_malloc.h>
29 #include <rte_memcpy.h>
30 #include <rte_string_fns.h>
31 #include <rte_cycles.h>
32 #include <rte_kvargs.h>
35 #include <fslmc_logs.h>
36 #include <rte_fslmc.h>
37 #include "dpaa2_hw_pvt.h"
38 #include "dpaa2_hw_dpio.h"
39 #include <mc/fsl_dpmng.h>
41 #define NUM_HOST_CPUS RTE_MAX_LCORE
43 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
44 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
46 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
48 TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev);
49 static struct dpio_dev_list dpio_dev_list
50 = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */
51 static uint32_t io_space_count;
53 /* Variable to store DPAA2 platform type */
54 uint32_t dpaa2_svr_family;
56 /*Stashing Macros default for LS208x*/
57 static int dpaa2_core_cluster_base = 0x04;
58 static int dpaa2_cluster_sz = 2;
60 /* For LS208X platform There are four clusters with following mapping:
61 * Cluster 1 (ID = x04) : CPU0, CPU1;
62 * Cluster 2 (ID = x05) : CPU2, CPU3;
63 * Cluster 3 (ID = x06) : CPU4, CPU5;
64 * Cluster 4 (ID = x07) : CPU6, CPU7;
66 /* For LS108X platform There are two clusters with following mapping:
67 * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
68 * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
70 /* For LX2160 platform There are four clusters with following mapping:
71 * Cluster 1 (ID = x00) : CPU0, CPU1;
72 * Cluster 2 (ID = x01) : CPU2, CPU3;
73 * Cluster 3 (ID = x02) : CPU4, CPU5;
74 * Cluster 4 (ID = x03) : CPU6, CPU7;
75 * Cluster 1 (ID = x04) : CPU8, CPU9;
76 * Cluster 2 (ID = x05) : CPU10, CP11;
77 * Cluster 3 (ID = x06) : CPU12, CPU13;
78 * Cluster 4 (ID = x07) : CPU14, CPU15;
82 dpaa2_core_cluster_sdest(int cpu_id)
84 int x = cpu_id / dpaa2_cluster_sz;
86 return dpaa2_core_cluster_base + x;
89 static void dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id)
92 #define COMMAND_LEN 50
93 uint32_t cpu_mask = 1;
96 char *temp = NULL, *token = NULL;
97 char string[STRING_LEN], command[COMMAND_LEN];
100 snprintf(string, STRING_LEN, "dpio.%d", dpio_id);
101 file = fopen("/proc/interrupts", "r");
103 PMD_DRV_LOG(WARNING, "Failed to open /proc/interrupts file\n");
106 while (getline(&temp, &len, file) != -1) {
107 if ((strstr(temp, string)) != NULL) {
108 token = strtok(temp, ":");
114 PMD_DRV_LOG(WARNING, "Failed to get interrupt id for dpio.%d\n",
122 cpu_mask = cpu_mask << rte_lcore_id();
123 snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity",
125 ret = system(command);
128 "Failed to affine interrupts on respective core\n");
130 PMD_DRV_LOG(WARNING, " %s command is executed\n", command);
136 static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev)
138 struct epoll_event epoll_ev;
139 int eventfd, dpio_epoll_fd, ret;
140 int threshold = 0x3, timeout = 0xFF;
142 dpio_epoll_fd = epoll_create(1);
143 ret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0);
145 PMD_DRV_LOG(ERR, "Interrupt registeration failed\n");
149 if (getenv("DPAA2_PORTAL_INTR_THRESHOLD"))
150 threshold = atoi(getenv("DPAA2_PORTAL_INTR_THRESHOLD"));
152 if (getenv("DPAA2_PORTAL_INTR_TIMEOUT"))
153 sscanf(getenv("DPAA2_PORTAL_INTR_TIMEOUT"), "%x", &timeout);
155 qbman_swp_interrupt_set_trigger(dpio_dev->sw_portal,
156 QBMAN_SWP_INTERRUPT_DQRI);
157 qbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff);
158 qbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0);
159 qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);
160 qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);
162 eventfd = dpio_dev->intr_handle.fd;
163 epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;
164 epoll_ev.data.fd = eventfd;
166 ret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev);
168 PMD_DRV_LOG(ERR, "epoll_ctl failed\n");
171 dpio_dev->epoll_fd = dpio_epoll_fd;
173 dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id);
179 configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
181 struct qbman_swp_desc p_des;
182 struct dpio_attr attr;
184 dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io));
185 if (!dpio_dev->dpio) {
186 PMD_INIT_LOG(ERR, "Memory allocation failure\n");
190 PMD_DRV_LOG(DEBUG, "Allocated DPIO Portal[%p]", dpio_dev->dpio);
191 dpio_dev->dpio->regs = dpio_dev->mc_portal;
192 if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
194 PMD_INIT_LOG(ERR, "Failed to allocate IO space\n");
195 free(dpio_dev->dpio);
199 if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
200 PMD_INIT_LOG(ERR, "Failed to reset dpio\n");
201 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
202 free(dpio_dev->dpio);
206 if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
207 PMD_INIT_LOG(ERR, "Failed to Enable dpio\n");
208 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
209 free(dpio_dev->dpio);
213 if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
214 dpio_dev->token, &attr)) {
215 PMD_INIT_LOG(ERR, "DPIO Get attribute failed\n");
216 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
217 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
218 free(dpio_dev->dpio);
222 /* Configure & setup SW portal */
224 p_des.idx = attr.qbman_portal_id;
225 p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
226 p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
228 p_des.qman_version = attr.qbman_version;
230 dpio_dev->sw_portal = qbman_swp_init(&p_des);
231 if (dpio_dev->sw_portal == NULL) {
232 PMD_DRV_LOG(ERR, " QBMan SW Portal Init failed\n");
233 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
234 free(dpio_dev->dpio);
242 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
246 /* Set the Stashing Destination */
248 cpu_id = rte_get_master_lcore();
250 RTE_LOG(ERR, PMD, "\tGetting CPU Index failed\n");
254 /* Set the STASH Destination depending on Current CPU ID.
255 * Valid values of SDEST are 4,5,6,7. Where,
258 sdest = dpaa2_core_cluster_sdest(cpu_id);
259 PMD_DRV_LOG(DEBUG, "Portal= %d CPU= %u SDEST= %d",
260 dpio_dev->index, cpu_id, sdest);
262 ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
263 dpio_dev->token, sdest);
265 PMD_DRV_LOG(ERR, "%d ERROR in SDEST\n", ret);
269 if (dpaa2_dpio_intr_init(dpio_dev)) {
270 PMD_DRV_LOG(ERR, "Interrupt registration failed for dpio\n");
277 struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
279 struct dpaa2_dpio_dev *dpio_dev = NULL;
282 /* Get DPIO dev handle from list using index */
283 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
284 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
290 PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu",
291 dpio_dev, dpio_dev->index, syscall(SYS_gettid));
293 ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
295 PMD_DRV_LOG(ERR, "dpaa2_configure_stashing failed");
301 dpaa2_affine_qbman_swp(void)
303 unsigned int lcore_id = rte_lcore_id();
304 uint64_t tid = syscall(SYS_gettid);
306 if (lcore_id == LCORE_ID_ANY)
307 lcore_id = rte_get_master_lcore();
308 /* if the core id is not supported */
309 else if (lcore_id >= RTE_MAX_LCORE)
312 if (dpaa2_io_portal[lcore_id].dpio_dev) {
313 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
314 " between thread %lu and current %lu",
315 dpaa2_io_portal[lcore_id].dpio_dev,
316 dpaa2_io_portal[lcore_id].dpio_dev->index,
317 dpaa2_io_portal[lcore_id].net_tid,
319 RTE_PER_LCORE(_dpaa2_io).dpio_dev
320 = dpaa2_io_portal[lcore_id].dpio_dev;
321 rte_atomic16_inc(&dpaa2_io_portal
322 [lcore_id].dpio_dev->ref_count);
323 dpaa2_io_portal[lcore_id].net_tid = tid;
325 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
326 dpaa2_io_portal[lcore_id].dpio_dev,
327 dpaa2_io_portal[lcore_id].dpio_dev->index,
332 /* Populate the dpaa2_io_portal structure */
333 dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id);
335 if (dpaa2_io_portal[lcore_id].dpio_dev) {
336 RTE_PER_LCORE(_dpaa2_io).dpio_dev
337 = dpaa2_io_portal[lcore_id].dpio_dev;
338 dpaa2_io_portal[lcore_id].net_tid = tid;
347 dpaa2_affine_qbman_swp_sec(void)
349 unsigned int lcore_id = rte_lcore_id();
350 uint64_t tid = syscall(SYS_gettid);
352 if (lcore_id == LCORE_ID_ANY)
353 lcore_id = rte_get_master_lcore();
354 /* if the core id is not supported */
355 else if (lcore_id >= RTE_MAX_LCORE)
358 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
359 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
360 " between thread %lu and current %lu",
361 dpaa2_io_portal[lcore_id].sec_dpio_dev,
362 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
363 dpaa2_io_portal[lcore_id].sec_tid,
365 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
366 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
367 rte_atomic16_inc(&dpaa2_io_portal
368 [lcore_id].sec_dpio_dev->ref_count);
369 dpaa2_io_portal[lcore_id].sec_tid = tid;
371 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
372 dpaa2_io_portal[lcore_id].sec_dpio_dev,
373 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
378 /* Populate the dpaa2_io_portal structure */
379 dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp(lcore_id);
381 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
382 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
383 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
384 dpaa2_io_portal[lcore_id].sec_tid = tid;
392 dpaa2_create_dpio_device(int vdev_fd,
393 struct vfio_device_info *obj_info,
396 struct dpaa2_dpio_dev *dpio_dev;
397 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
399 if (obj_info->num_regions < NUM_DPIO_REGIONS) {
400 PMD_INIT_LOG(ERR, "ERROR, Not sufficient number "
401 "of DPIO regions.\n");
405 dpio_dev = rte_malloc(NULL, sizeof(struct dpaa2_dpio_dev),
406 RTE_CACHE_LINE_SIZE);
408 PMD_INIT_LOG(ERR, "Memory allocation failed for DPIO Device\n");
412 dpio_dev->dpio = NULL;
413 dpio_dev->hw_id = object_id;
414 rte_atomic16_init(&dpio_dev->ref_count);
415 /* Using single portal for all devices */
416 dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX];
419 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
420 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
425 dpio_dev->ce_size = reg_info.size;
426 dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,
427 PROT_WRITE | PROT_READ, MAP_SHARED,
428 vdev_fd, reg_info.offset);
431 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
432 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
437 dpio_dev->ci_size = reg_info.size;
438 dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,
439 PROT_WRITE | PROT_READ, MAP_SHARED,
440 vdev_fd, reg_info.offset);
442 if (configure_dpio_qbman_swp(dpio_dev)) {
444 "Fail to configure the dpio qbman portal for %d\n",
451 dpio_dev->index = io_space_count;
453 if (rte_dpaa2_vfio_setup_intr(&dpio_dev->intr_handle, vdev_fd, 1)) {
454 PMD_INIT_LOG(ERR, "Fail to setup interrupt for %d\n",
459 /* find the SoC type for the first time */
460 if (!dpaa2_svr_family) {
461 struct mc_soc_version mc_plat_info = {0};
463 if (mc_get_soc_version(dpio_dev->dpio,
464 CMD_PRI_LOW, &mc_plat_info)) {
465 PMD_INIT_LOG(ERR, "\tmc_get_soc_version failed\n");
466 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) {
467 dpaa2_core_cluster_base = 0x02;
468 dpaa2_cluster_sz = 4;
469 PMD_INIT_LOG(DEBUG, "\tLS108x (A53) Platform Detected");
470 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LX2160A) {
471 dpaa2_core_cluster_base = 0x00;
472 dpaa2_cluster_sz = 2;
473 PMD_INIT_LOG(DEBUG, "\tLX2160 Platform Detected");
475 dpaa2_svr_family = (mc_plat_info.svr & 0xffff0000);
478 TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);
479 RTE_LOG(DEBUG, PMD, "DPAA2: Added [dpio.%d]\n", object_id);
485 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
489 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
490 if (q_storage->dq_storage[i])
491 rte_free(q_storage->dq_storage[i]);
496 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
500 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
501 q_storage->dq_storage[i] = rte_malloc(NULL,
502 DPAA2_DQRR_RING_SIZE * sizeof(struct qbman_result),
503 RTE_CACHE_LINE_SIZE);
504 if (!q_storage->dq_storage[i])
510 rte_free(q_storage->dq_storage[i]);
515 static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
516 .dev_type = DPAA2_IO,
517 .create = dpaa2_create_dpio_device,
520 RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);