4 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
5 * Copyright (c) 2016 NXP. All rights reserved.
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15 * the documentation and/or other materials provided with the
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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43 #include <sys/types.h>
44 #include <sys/queue.h>
45 #include <sys/ioctl.h>
48 #include <sys/syscall.h>
51 #include <rte_ethdev.h>
52 #include <rte_malloc.h>
53 #include <rte_memcpy.h>
54 #include <rte_string_fns.h>
55 #include <rte_cycles.h>
56 #include <rte_kvargs.h>
58 #include <rte_ethdev.h>
60 #include <fslmc_logs.h>
61 #include <fslmc_vfio.h>
62 #include "dpaa2_hw_pvt.h"
63 #include "dpaa2_hw_dpio.h"
65 #define NUM_HOST_CPUS RTE_MAX_LCORE
67 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
68 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
70 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
72 TAILQ_HEAD(dpio_device_list, dpaa2_dpio_dev);
73 static struct dpio_device_list *dpio_dev_list; /*!< DPIO device list */
74 static uint32_t io_space_count;
76 /*Stashing Macros default for LS208x*/
77 static int dpaa2_core_cluster_base = 0x04;
78 static int dpaa2_cluster_sz = 2;
80 /* For LS208X platform There are four clusters with following mapping:
81 * Cluster 1 (ID = x04) : CPU0, CPU1;
82 * Cluster 2 (ID = x05) : CPU2, CPU3;
83 * Cluster 3 (ID = x06) : CPU4, CPU5;
84 * Cluster 4 (ID = x07) : CPU6, CPU7;
86 /* For LS108X platform There are two clusters with following mapping:
87 * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
88 * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
91 /* Set the STASH Destination depending on Current CPU ID.
92 * e.g. Valid values of SDEST are 4,5,6,7. Where,
93 * CPU 0-1 will have SDEST 4
94 * CPU 2-3 will have SDEST 5.....and so on.
97 dpaa2_core_cluster_sdest(int cpu_id)
99 int x = cpu_id / dpaa2_cluster_sz;
104 return dpaa2_core_cluster_base + x;
108 configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
110 struct qbman_swp_desc p_des;
111 struct dpio_attr attr;
113 dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io));
114 if (!dpio_dev->dpio) {
115 PMD_INIT_LOG(ERR, "Memory allocation failure\n");
119 PMD_DRV_LOG(DEBUG, "\t Allocated DPIO Portal[%p]", dpio_dev->dpio);
120 dpio_dev->dpio->regs = dpio_dev->mc_portal;
121 if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
123 PMD_INIT_LOG(ERR, "Failed to allocate IO space\n");
124 free(dpio_dev->dpio);
128 if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
129 PMD_INIT_LOG(ERR, "Failed to reset dpio\n");
130 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
131 free(dpio_dev->dpio);
135 if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
136 PMD_INIT_LOG(ERR, "Failed to Enable dpio\n");
137 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
138 free(dpio_dev->dpio);
142 if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
143 dpio_dev->token, &attr)) {
144 PMD_INIT_LOG(ERR, "DPIO Get attribute failed\n");
145 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
146 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
147 free(dpio_dev->dpio);
151 PMD_INIT_LOG(DEBUG, "Qbman Portal ID %d", attr.qbman_portal_id);
152 PMD_INIT_LOG(DEBUG, "Portal CE adr 0x%lX", attr.qbman_portal_ce_offset);
153 PMD_INIT_LOG(DEBUG, "Portal CI adr 0x%lX", attr.qbman_portal_ci_offset);
155 /* Configure & setup SW portal */
157 p_des.idx = attr.qbman_portal_id;
158 p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
159 p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
161 p_des.qman_version = attr.qbman_version;
163 dpio_dev->sw_portal = qbman_swp_init(&p_des);
164 if (dpio_dev->sw_portal == NULL) {
165 PMD_DRV_LOG(ERR, " QBMan SW Portal Init failed\n");
166 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
167 free(dpio_dev->dpio);
171 PMD_INIT_LOG(DEBUG, "QBMan SW Portal 0x%p\n", dpio_dev->sw_portal);
177 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev)
182 /* Set the Stashing Destination */
183 cpu_id = rte_lcore_id();
185 cpu_id = rte_get_master_lcore();
187 RTE_LOG(ERR, PMD, "\tGetting CPU Index failed\n");
191 /* Set the STASH Destination depending on Current CPU ID.
192 * Valid values of SDEST are 4,5,6,7. Where,
193 * CPU 0-1 will have SDEST 4
194 * CPU 2-3 will have SDEST 5.....and so on.
197 sdest = dpaa2_core_cluster_sdest(cpu_id);
198 PMD_DRV_LOG(DEBUG, "Portal= %d CPU= %u SDEST= %d",
199 dpio_dev->index, cpu_id, sdest);
201 ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
202 dpio_dev->token, sdest);
204 PMD_DRV_LOG(ERR, "%d ERROR in SDEST\n", ret);
211 static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
213 struct dpaa2_dpio_dev *dpio_dev = NULL;
216 /* Get DPIO dev handle from list using index */
217 TAILQ_FOREACH(dpio_dev, dpio_dev_list, next) {
218 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
224 PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu",
225 dpio_dev, dpio_dev->index, syscall(SYS_gettid));
227 ret = dpaa2_configure_stashing(dpio_dev);
229 PMD_DRV_LOG(ERR, "dpaa2_configure_stashing failed");
235 dpaa2_affine_qbman_swp(void)
237 unsigned int lcore_id = rte_lcore_id();
238 uint64_t tid = syscall(SYS_gettid);
240 if (lcore_id == LCORE_ID_ANY)
241 lcore_id = rte_get_master_lcore();
242 /* if the core id is not supported */
243 else if (lcore_id >= RTE_MAX_LCORE)
246 if (dpaa2_io_portal[lcore_id].dpio_dev) {
247 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
248 " between thread %lu and current %lu",
249 dpaa2_io_portal[lcore_id].dpio_dev,
250 dpaa2_io_portal[lcore_id].dpio_dev->index,
251 dpaa2_io_portal[lcore_id].net_tid,
253 RTE_PER_LCORE(_dpaa2_io).dpio_dev
254 = dpaa2_io_portal[lcore_id].dpio_dev;
255 rte_atomic16_inc(&dpaa2_io_portal
256 [lcore_id].dpio_dev->ref_count);
257 dpaa2_io_portal[lcore_id].net_tid = tid;
259 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
260 dpaa2_io_portal[lcore_id].dpio_dev,
261 dpaa2_io_portal[lcore_id].dpio_dev->index,
266 /* Populate the dpaa2_io_portal structure */
267 dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp();
269 if (dpaa2_io_portal[lcore_id].dpio_dev) {
270 RTE_PER_LCORE(_dpaa2_io).dpio_dev
271 = dpaa2_io_portal[lcore_id].dpio_dev;
272 dpaa2_io_portal[lcore_id].net_tid = tid;
281 dpaa2_affine_qbman_swp_sec(void)
283 unsigned int lcore_id = rte_lcore_id();
284 uint64_t tid = syscall(SYS_gettid);
286 if (lcore_id == LCORE_ID_ANY)
287 lcore_id = rte_get_master_lcore();
288 /* if the core id is not supported */
289 else if (lcore_id >= RTE_MAX_LCORE)
292 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
293 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
294 " between thread %lu and current %lu",
295 dpaa2_io_portal[lcore_id].sec_dpio_dev,
296 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
297 dpaa2_io_portal[lcore_id].sec_tid,
299 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
300 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
301 rte_atomic16_inc(&dpaa2_io_portal
302 [lcore_id].sec_dpio_dev->ref_count);
303 dpaa2_io_portal[lcore_id].sec_tid = tid;
305 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
306 dpaa2_io_portal[lcore_id].sec_dpio_dev,
307 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
312 /* Populate the dpaa2_io_portal structure */
313 dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp();
315 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
316 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
317 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
318 dpaa2_io_portal[lcore_id].sec_tid = tid;
326 dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev,
327 struct vfio_device_info *obj_info,
330 struct dpaa2_dpio_dev *dpio_dev;
331 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
333 if (obj_info->num_regions < NUM_DPIO_REGIONS) {
334 PMD_INIT_LOG(ERR, "ERROR, Not sufficient number "
335 "of DPIO regions.\n");
339 if (!dpio_dev_list) {
340 dpio_dev_list = malloc(sizeof(struct dpio_device_list));
341 if (!dpio_dev_list) {
342 PMD_INIT_LOG(ERR, "Memory alloc failed in DPIO list\n");
346 /* Initialize the DPIO List */
347 TAILQ_INIT(dpio_dev_list);
350 dpio_dev = malloc(sizeof(struct dpaa2_dpio_dev));
352 PMD_INIT_LOG(ERR, "Memory allocation failed for DPIO Device\n");
356 PMD_DRV_LOG(INFO, "\t Aloocated DPIO [%p]", dpio_dev);
357 dpio_dev->dpio = NULL;
358 dpio_dev->hw_id = object_id;
359 dpio_dev->vfio_fd = vdev->fd;
360 rte_atomic16_init(&dpio_dev->ref_count);
361 /* Using single portal for all devices */
362 dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX];
365 if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
366 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
371 PMD_DRV_LOG(DEBUG, "\t Region Offset = %llx", reg_info.offset);
372 PMD_DRV_LOG(DEBUG, "\t Region Size = %llx", reg_info.size);
373 dpio_dev->ce_size = reg_info.size;
374 dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,
375 PROT_WRITE | PROT_READ, MAP_SHARED,
376 dpio_dev->vfio_fd, reg_info.offset);
378 /* Create Mapping for QBMan Cache Enabled area. This is a fix for
379 * SMMU fault for DQRR statshing transaction.
381 if (vfio_dmamap_mem_region(dpio_dev->qbman_portal_ce_paddr,
382 reg_info.offset, reg_info.size)) {
383 PMD_INIT_LOG(ERR, "DMAMAP for Portal CE area failed.\n");
389 if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
390 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
395 PMD_DRV_LOG(DEBUG, "\t Region Offset = %llx", reg_info.offset);
396 PMD_DRV_LOG(DEBUG, "\t Region Size = %llx", reg_info.size);
397 dpio_dev->ci_size = reg_info.size;
398 dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,
399 PROT_WRITE | PROT_READ, MAP_SHARED,
400 dpio_dev->vfio_fd, reg_info.offset);
402 if (configure_dpio_qbman_swp(dpio_dev)) {
404 "Fail to configure the dpio qbman portal for %d\n",
411 dpio_dev->index = io_space_count;
412 TAILQ_INSERT_HEAD(dpio_dev_list, dpio_dev, next);
418 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
422 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
423 if (q_storage->dq_storage[i])
424 rte_free(q_storage->dq_storage[i]);
429 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
433 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
434 q_storage->dq_storage[i] = rte_malloc(NULL,
435 DPAA2_DQRR_RING_SIZE * sizeof(struct qbman_result),
436 RTE_CACHE_LINE_SIZE);
437 if (!q_storage->dq_storage[i])
444 rte_free(q_storage->dq_storage[i]);