1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
17 #include <sys/types.h>
18 #include <sys/queue.h>
19 #include <sys/ioctl.h>
22 #include <sys/syscall.h>
23 #include <sys/epoll.h>
24 #include<sys/eventfd.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_malloc.h>
29 #include <rte_memcpy.h>
30 #include <rte_string_fns.h>
31 #include <rte_cycles.h>
32 #include <rte_kvargs.h>
35 #include <fslmc_logs.h>
36 #include <rte_fslmc.h>
37 #include "dpaa2_hw_pvt.h"
38 #include "dpaa2_hw_dpio.h"
39 #include <mc/fsl_dpmng.h>
41 #define NUM_HOST_CPUS RTE_MAX_LCORE
43 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
44 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
46 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
48 TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev);
49 static struct dpio_dev_list dpio_dev_list
50 = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */
51 static uint32_t io_space_count;
53 /* Variable to store DPAA2 platform type */
54 uint32_t dpaa2_svr_family;
56 /*Stashing Macros default for LS208x*/
57 static int dpaa2_core_cluster_base = 0x04;
58 static int dpaa2_cluster_sz = 2;
60 /* For LS208X platform There are four clusters with following mapping:
61 * Cluster 1 (ID = x04) : CPU0, CPU1;
62 * Cluster 2 (ID = x05) : CPU2, CPU3;
63 * Cluster 3 (ID = x06) : CPU4, CPU5;
64 * Cluster 4 (ID = x07) : CPU6, CPU7;
66 /* For LS108X platform There are two clusters with following mapping:
67 * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
68 * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
70 /* For LX2160 platform There are four clusters with following mapping:
71 * Cluster 1 (ID = x00) : CPU0, CPU1;
72 * Cluster 2 (ID = x01) : CPU2, CPU3;
73 * Cluster 3 (ID = x02) : CPU4, CPU5;
74 * Cluster 4 (ID = x03) : CPU6, CPU7;
75 * Cluster 1 (ID = x04) : CPU8, CPU9;
76 * Cluster 2 (ID = x05) : CPU10, CP11;
77 * Cluster 3 (ID = x06) : CPU12, CPU13;
78 * Cluster 4 (ID = x07) : CPU14, CPU15;
82 dpaa2_core_cluster_sdest(int cpu_id)
84 int x = cpu_id / dpaa2_cluster_sz;
86 return dpaa2_core_cluster_base + x;
89 #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV
90 static void dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id)
93 #define COMMAND_LEN 50
94 uint32_t cpu_mask = 1;
97 char *temp = NULL, *token = NULL;
98 char string[STRING_LEN], command[COMMAND_LEN];
101 snprintf(string, STRING_LEN, "dpio.%d", dpio_id);
102 file = fopen("/proc/interrupts", "r");
104 DPAA2_BUS_WARN("Failed to open /proc/interrupts file");
107 while (getline(&temp, &len, file) != -1) {
108 if ((strstr(temp, string)) != NULL) {
109 token = strtok(temp, ":");
115 DPAA2_BUS_WARN("Failed to get interrupt id for dpio.%d",
123 cpu_mask = cpu_mask << rte_lcore_id();
124 snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity",
126 ret = system(command);
129 "Failed to affine interrupts on respective core");
131 DPAA2_BUS_DEBUG(" %s command is executed", command);
137 static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev)
139 struct epoll_event epoll_ev;
140 int eventfd, dpio_epoll_fd, ret;
141 int threshold = 0x3, timeout = 0xFF;
143 dpio_epoll_fd = epoll_create(1);
144 ret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0);
146 DPAA2_BUS_ERR("Interrupt registeration failed");
150 if (getenv("DPAA2_PORTAL_INTR_THRESHOLD"))
151 threshold = atoi(getenv("DPAA2_PORTAL_INTR_THRESHOLD"));
153 if (getenv("DPAA2_PORTAL_INTR_TIMEOUT"))
154 sscanf(getenv("DPAA2_PORTAL_INTR_TIMEOUT"), "%x", &timeout);
156 qbman_swp_interrupt_set_trigger(dpio_dev->sw_portal,
157 QBMAN_SWP_INTERRUPT_DQRI);
158 qbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff);
159 qbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0);
160 qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);
161 qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);
163 eventfd = dpio_dev->intr_handle.fd;
164 epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;
165 epoll_ev.data.fd = eventfd;
167 ret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev);
169 DPAA2_BUS_ERR("epoll_ctl failed");
172 dpio_dev->epoll_fd = dpio_epoll_fd;
174 dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id);
181 configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
183 struct qbman_swp_desc p_des;
184 struct dpio_attr attr;
186 dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io));
187 if (!dpio_dev->dpio) {
188 DPAA2_BUS_ERR("Memory allocation failure");
192 dpio_dev->dpio->regs = dpio_dev->mc_portal;
193 if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
195 DPAA2_BUS_ERR("Failed to allocate IO space");
196 free(dpio_dev->dpio);
200 if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
201 DPAA2_BUS_ERR("Failed to reset dpio");
202 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
203 free(dpio_dev->dpio);
207 if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
208 DPAA2_BUS_ERR("Failed to Enable dpio");
209 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
210 free(dpio_dev->dpio);
214 if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
215 dpio_dev->token, &attr)) {
216 DPAA2_BUS_ERR("DPIO Get attribute failed");
217 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
218 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
219 free(dpio_dev->dpio);
223 /* Configure & setup SW portal */
225 p_des.idx = attr.qbman_portal_id;
226 p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
227 p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
229 p_des.qman_version = attr.qbman_version;
231 dpio_dev->sw_portal = qbman_swp_init(&p_des);
232 if (dpio_dev->sw_portal == NULL) {
233 DPAA2_BUS_ERR("QBMan SW Portal Init failed");
234 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
235 free(dpio_dev->dpio);
243 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
247 /* Set the Stashing Destination */
249 cpu_id = rte_get_master_lcore();
251 DPAA2_BUS_ERR("Getting CPU Index failed");
255 /* Set the STASH Destination depending on Current CPU ID.
256 * Valid values of SDEST are 4,5,6,7. Where,
259 sdest = dpaa2_core_cluster_sdest(cpu_id);
260 DPAA2_BUS_DEBUG("Portal= %d CPU= %u SDEST= %d",
261 dpio_dev->index, cpu_id, sdest);
263 ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
264 dpio_dev->token, sdest);
266 DPAA2_BUS_ERR("%d ERROR in SDEST", ret);
270 #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV
271 if (dpaa2_dpio_intr_init(dpio_dev)) {
272 DPAA2_BUS_ERR("Interrupt registration failed for dpio");
280 struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
282 struct dpaa2_dpio_dev *dpio_dev = NULL;
285 /* Get DPIO dev handle from list using index */
286 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
287 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
293 DPAA2_BUS_DEBUG("New Portal %p (%d) affined thread - %lu",
294 dpio_dev, dpio_dev->index, syscall(SYS_gettid));
296 ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
298 DPAA2_BUS_ERR("dpaa2_configure_stashing failed");
304 dpaa2_affine_qbman_swp(void)
306 unsigned int lcore_id = rte_lcore_id();
307 uint64_t tid = syscall(SYS_gettid);
309 if (lcore_id == LCORE_ID_ANY)
310 lcore_id = rte_get_master_lcore();
311 /* if the core id is not supported */
312 else if (lcore_id >= RTE_MAX_LCORE)
315 if (dpaa2_io_portal[lcore_id].dpio_dev) {
316 DPAA2_BUS_DP_INFO("DPAA Portal=%p (%d) is being shared"
317 " between thread %" PRIu64 " and current "
319 dpaa2_io_portal[lcore_id].dpio_dev,
320 dpaa2_io_portal[lcore_id].dpio_dev->index,
321 dpaa2_io_portal[lcore_id].net_tid,
323 RTE_PER_LCORE(_dpaa2_io).dpio_dev
324 = dpaa2_io_portal[lcore_id].dpio_dev;
325 rte_atomic16_inc(&dpaa2_io_portal
326 [lcore_id].dpio_dev->ref_count);
327 dpaa2_io_portal[lcore_id].net_tid = tid;
329 DPAA2_BUS_DP_DEBUG("Old Portal=%p (%d) affined thread - "
331 dpaa2_io_portal[lcore_id].dpio_dev,
332 dpaa2_io_portal[lcore_id].dpio_dev->index,
337 /* Populate the dpaa2_io_portal structure */
338 dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id);
340 if (dpaa2_io_portal[lcore_id].dpio_dev) {
341 RTE_PER_LCORE(_dpaa2_io).dpio_dev
342 = dpaa2_io_portal[lcore_id].dpio_dev;
343 dpaa2_io_portal[lcore_id].net_tid = tid;
352 dpaa2_affine_qbman_ethrx_swp(void)
354 unsigned int lcore_id = rte_lcore_id();
355 uint64_t tid = syscall(SYS_gettid);
357 if (lcore_id == LCORE_ID_ANY)
358 lcore_id = rte_get_master_lcore();
359 /* if the core id is not supported */
360 else if (lcore_id >= RTE_MAX_LCORE)
363 if (dpaa2_io_portal[lcore_id].ethrx_dpio_dev) {
365 "DPAA Portal=%p (%d) is being shared between thread"
366 " %" PRIu64 " and current %" PRIu64 "\n",
367 dpaa2_io_portal[lcore_id].ethrx_dpio_dev,
368 dpaa2_io_portal[lcore_id].ethrx_dpio_dev->index,
369 dpaa2_io_portal[lcore_id].sec_tid,
371 RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev
372 = dpaa2_io_portal[lcore_id].ethrx_dpio_dev;
373 rte_atomic16_inc(&dpaa2_io_portal
374 [lcore_id].ethrx_dpio_dev->ref_count);
375 dpaa2_io_portal[lcore_id].sec_tid = tid;
378 "Old Portal=%p (%d) affined thread"
380 dpaa2_io_portal[lcore_id].ethrx_dpio_dev,
381 dpaa2_io_portal[lcore_id].ethrx_dpio_dev->index,
386 /* Populate the dpaa2_io_portal structure */
387 dpaa2_io_portal[lcore_id].ethrx_dpio_dev =
388 dpaa2_get_qbman_swp(lcore_id);
390 if (dpaa2_io_portal[lcore_id].ethrx_dpio_dev) {
391 RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev
392 = dpaa2_io_portal[lcore_id].ethrx_dpio_dev;
393 dpaa2_io_portal[lcore_id].sec_tid = tid;
401 dpaa2_create_dpio_device(int vdev_fd,
402 struct vfio_device_info *obj_info,
405 struct dpaa2_dpio_dev *dpio_dev;
406 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
408 if (obj_info->num_regions < NUM_DPIO_REGIONS) {
409 DPAA2_BUS_ERR("Not sufficient number of DPIO regions");
413 dpio_dev = rte_malloc(NULL, sizeof(struct dpaa2_dpio_dev),
414 RTE_CACHE_LINE_SIZE);
416 DPAA2_BUS_ERR("Memory allocation failed for DPIO Device");
420 dpio_dev->dpio = NULL;
421 dpio_dev->hw_id = object_id;
422 rte_atomic16_init(&dpio_dev->ref_count);
423 /* Using single portal for all devices */
424 dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX];
427 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
428 DPAA2_BUS_ERR("vfio: error getting region info");
433 dpio_dev->ce_size = reg_info.size;
434 dpio_dev->qbman_portal_ce_paddr = (size_t)mmap(NULL, reg_info.size,
435 PROT_WRITE | PROT_READ, MAP_SHARED,
436 vdev_fd, reg_info.offset);
439 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
440 DPAA2_BUS_ERR("vfio: error getting region info");
445 dpio_dev->ci_size = reg_info.size;
446 dpio_dev->qbman_portal_ci_paddr = (size_t)mmap(NULL, reg_info.size,
447 PROT_WRITE | PROT_READ, MAP_SHARED,
448 vdev_fd, reg_info.offset);
450 if (configure_dpio_qbman_swp(dpio_dev)) {
452 "Fail to configure the dpio qbman portal for %d",
459 dpio_dev->index = io_space_count;
461 if (rte_dpaa2_vfio_setup_intr(&dpio_dev->intr_handle, vdev_fd, 1)) {
462 DPAA2_BUS_ERR("Fail to setup interrupt for %d",
467 /* find the SoC type for the first time */
468 if (!dpaa2_svr_family) {
469 struct mc_soc_version mc_plat_info = {0};
471 if (mc_get_soc_version(dpio_dev->dpio,
472 CMD_PRI_LOW, &mc_plat_info)) {
473 DPAA2_BUS_ERR("Unable to get SoC version information");
474 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) {
475 dpaa2_core_cluster_base = 0x02;
476 dpaa2_cluster_sz = 4;
477 DPAA2_BUS_DEBUG("LS108x (A53) Platform Detected");
478 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LX2160A) {
479 dpaa2_core_cluster_base = 0x00;
480 dpaa2_cluster_sz = 2;
481 DPAA2_BUS_DEBUG("LX2160 Platform Detected");
483 dpaa2_svr_family = (mc_plat_info.svr & 0xffff0000);
486 TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);
492 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
496 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
497 if (q_storage->dq_storage[i])
498 rte_free(q_storage->dq_storage[i]);
503 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
507 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
508 q_storage->dq_storage[i] = rte_malloc(NULL,
509 DPAA2_DQRR_RING_SIZE * sizeof(struct qbman_result),
510 RTE_CACHE_LINE_SIZE);
511 if (!q_storage->dq_storage[i])
517 rte_free(q_storage->dq_storage[i]);
522 static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
523 .dev_type = DPAA2_IO,
524 .create = dpaa2_create_dpio_device,
527 RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);