4 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
5 * Copyright (c) 2016 NXP. All rights reserved.
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43 #include <sys/types.h>
44 #include <sys/queue.h>
45 #include <sys/ioctl.h>
48 #include <sys/syscall.h>
51 #include <rte_ethdev.h>
52 #include <rte_malloc.h>
53 #include <rte_memcpy.h>
54 #include <rte_string_fns.h>
55 #include <rte_cycles.h>
56 #include <rte_kvargs.h>
58 #include <rte_ethdev.h>
60 #include <fslmc_logs.h>
61 #include <fslmc_vfio.h>
62 #include "dpaa2_hw_pvt.h"
63 #include "dpaa2_hw_dpio.h"
64 #include <mc/fsl_dpmng.h>
66 #define NUM_HOST_CPUS RTE_MAX_LCORE
68 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
69 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
71 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
73 TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev);
74 static struct dpio_dev_list dpio_dev_list
75 = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */
76 static uint32_t io_space_count;
78 /*Stashing Macros default for LS208x*/
79 static int dpaa2_core_cluster_base = 0x04;
80 static int dpaa2_cluster_sz = 2;
82 /* For LS208X platform There are four clusters with following mapping:
83 * Cluster 1 (ID = x04) : CPU0, CPU1;
84 * Cluster 2 (ID = x05) : CPU2, CPU3;
85 * Cluster 3 (ID = x06) : CPU4, CPU5;
86 * Cluster 4 (ID = x07) : CPU6, CPU7;
88 /* For LS108X platform There are two clusters with following mapping:
89 * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
90 * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
93 /* Set the STASH Destination depending on Current CPU ID.
94 * e.g. Valid values of SDEST are 4,5,6,7. Where,
95 * CPU 0-1 will have SDEST 4
96 * CPU 2-3 will have SDEST 5.....and so on.
99 dpaa2_core_cluster_sdest(int cpu_id)
101 int x = cpu_id / dpaa2_cluster_sz;
106 return dpaa2_core_cluster_base + x;
110 configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
112 struct qbman_swp_desc p_des;
113 struct dpio_attr attr;
115 dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io));
116 if (!dpio_dev->dpio) {
117 PMD_INIT_LOG(ERR, "Memory allocation failure\n");
121 PMD_DRV_LOG(DEBUG, "\t Allocated DPIO Portal[%p]", dpio_dev->dpio);
122 dpio_dev->dpio->regs = dpio_dev->mc_portal;
123 if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
125 PMD_INIT_LOG(ERR, "Failed to allocate IO space\n");
126 free(dpio_dev->dpio);
130 if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
131 PMD_INIT_LOG(ERR, "Failed to reset dpio\n");
132 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
133 free(dpio_dev->dpio);
137 if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
138 PMD_INIT_LOG(ERR, "Failed to Enable dpio\n");
139 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
140 free(dpio_dev->dpio);
144 if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
145 dpio_dev->token, &attr)) {
146 PMD_INIT_LOG(ERR, "DPIO Get attribute failed\n");
147 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
148 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
149 free(dpio_dev->dpio);
153 PMD_INIT_LOG(DEBUG, "Qbman Portal ID %d", attr.qbman_portal_id);
155 /* Configure & setup SW portal */
157 p_des.idx = attr.qbman_portal_id;
158 p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
159 p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
161 p_des.qman_version = attr.qbman_version;
163 dpio_dev->sw_portal = qbman_swp_init(&p_des);
164 if (dpio_dev->sw_portal == NULL) {
165 PMD_DRV_LOG(ERR, " QBMan SW Portal Init failed\n");
166 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
167 free(dpio_dev->dpio);
175 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
178 static int first_time;
180 /* find the SoC type for the first time */
182 struct mc_soc_version mc_plat_info = {0};
184 if (mc_get_soc_version(dpio_dev->dpio,
185 CMD_PRI_LOW, &mc_plat_info)) {
186 PMD_INIT_LOG(ERR, "\tmc_get_soc_version failed\n");
187 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) {
188 dpaa2_core_cluster_base = 0x02;
189 dpaa2_cluster_sz = 4;
190 PMD_INIT_LOG(DEBUG, "\tLS108x (A53) Platform Detected");
195 /* Set the Stashing Destination */
197 cpu_id = rte_get_master_lcore();
199 RTE_LOG(ERR, PMD, "\tGetting CPU Index failed\n");
203 /* Set the STASH Destination depending on Current CPU ID.
204 * Valid values of SDEST are 4,5,6,7. Where,
207 sdest = dpaa2_core_cluster_sdest(cpu_id);
208 PMD_DRV_LOG(DEBUG, "Portal= %d CPU= %u SDEST= %d",
209 dpio_dev->index, cpu_id, sdest);
211 ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
212 dpio_dev->token, sdest);
214 PMD_DRV_LOG(ERR, "%d ERROR in SDEST\n", ret);
221 struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
223 struct dpaa2_dpio_dev *dpio_dev = NULL;
226 /* Get DPIO dev handle from list using index */
227 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
228 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
234 PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu",
235 dpio_dev, dpio_dev->index, syscall(SYS_gettid));
237 ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
239 PMD_DRV_LOG(ERR, "dpaa2_configure_stashing failed");
245 dpaa2_affine_qbman_swp(void)
247 unsigned int lcore_id = rte_lcore_id();
248 uint64_t tid = syscall(SYS_gettid);
250 if (lcore_id == LCORE_ID_ANY)
251 lcore_id = rte_get_master_lcore();
252 /* if the core id is not supported */
253 else if (lcore_id >= RTE_MAX_LCORE)
256 if (dpaa2_io_portal[lcore_id].dpio_dev) {
257 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
258 " between thread %lu and current %lu",
259 dpaa2_io_portal[lcore_id].dpio_dev,
260 dpaa2_io_portal[lcore_id].dpio_dev->index,
261 dpaa2_io_portal[lcore_id].net_tid,
263 RTE_PER_LCORE(_dpaa2_io).dpio_dev
264 = dpaa2_io_portal[lcore_id].dpio_dev;
265 rte_atomic16_inc(&dpaa2_io_portal
266 [lcore_id].dpio_dev->ref_count);
267 dpaa2_io_portal[lcore_id].net_tid = tid;
269 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
270 dpaa2_io_portal[lcore_id].dpio_dev,
271 dpaa2_io_portal[lcore_id].dpio_dev->index,
276 /* Populate the dpaa2_io_portal structure */
277 dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id);
279 if (dpaa2_io_portal[lcore_id].dpio_dev) {
280 RTE_PER_LCORE(_dpaa2_io).dpio_dev
281 = dpaa2_io_portal[lcore_id].dpio_dev;
282 dpaa2_io_portal[lcore_id].net_tid = tid;
291 dpaa2_affine_qbman_swp_sec(void)
293 unsigned int lcore_id = rte_lcore_id();
294 uint64_t tid = syscall(SYS_gettid);
296 if (lcore_id == LCORE_ID_ANY)
297 lcore_id = rte_get_master_lcore();
298 /* if the core id is not supported */
299 else if (lcore_id >= RTE_MAX_LCORE)
302 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
303 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
304 " between thread %lu and current %lu",
305 dpaa2_io_portal[lcore_id].sec_dpio_dev,
306 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
307 dpaa2_io_portal[lcore_id].sec_tid,
309 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
310 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
311 rte_atomic16_inc(&dpaa2_io_portal
312 [lcore_id].sec_dpio_dev->ref_count);
313 dpaa2_io_portal[lcore_id].sec_tid = tid;
315 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
316 dpaa2_io_portal[lcore_id].sec_dpio_dev,
317 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
322 /* Populate the dpaa2_io_portal structure */
323 dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp(lcore_id);
325 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
326 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
327 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
328 dpaa2_io_portal[lcore_id].sec_tid = tid;
336 dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev,
337 struct vfio_device_info *obj_info,
340 struct dpaa2_dpio_dev *dpio_dev;
341 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
343 if (obj_info->num_regions < NUM_DPIO_REGIONS) {
344 PMD_INIT_LOG(ERR, "ERROR, Not sufficient number "
345 "of DPIO regions.\n");
349 dpio_dev = rte_malloc(NULL, sizeof(struct dpaa2_dpio_dev),
350 RTE_CACHE_LINE_SIZE);
352 PMD_INIT_LOG(ERR, "Memory allocation failed for DPIO Device\n");
356 dpio_dev->dpio = NULL;
357 dpio_dev->hw_id = object_id;
358 dpio_dev->vfio_fd = vdev->fd;
359 rte_atomic16_init(&dpio_dev->ref_count);
360 /* Using single portal for all devices */
361 dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX];
364 if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
365 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
370 dpio_dev->ce_size = reg_info.size;
371 dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,
372 PROT_WRITE | PROT_READ, MAP_SHARED,
373 dpio_dev->vfio_fd, reg_info.offset);
375 /* Create Mapping for QBMan Cache Enabled area. This is a fix for
376 * SMMU fault for DQRR statshing transaction.
378 if (vfio_dmamap_mem_region(dpio_dev->qbman_portal_ce_paddr,
379 reg_info.offset, reg_info.size)) {
380 PMD_INIT_LOG(ERR, "DMAMAP for Portal CE area failed.\n");
386 if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
387 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
392 dpio_dev->ci_size = reg_info.size;
393 dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,
394 PROT_WRITE | PROT_READ, MAP_SHARED,
395 dpio_dev->vfio_fd, reg_info.offset);
397 if (configure_dpio_qbman_swp(dpio_dev)) {
399 "Fail to configure the dpio qbman portal for %d\n",
406 dpio_dev->index = io_space_count;
407 TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);
408 PMD_INIT_LOG(DEBUG, "DPAA2: Added [dpio-%d]", object_id);
414 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
418 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
419 if (q_storage->dq_storage[i])
420 rte_free(q_storage->dq_storage[i]);
425 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
429 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
430 q_storage->dq_storage[i] = rte_malloc(NULL,
431 DPAA2_DQRR_RING_SIZE * sizeof(struct qbman_result),
432 RTE_CACHE_LINE_SIZE);
433 if (!q_storage->dq_storage[i])
439 rte_free(q_storage->dq_storage[i]);
444 static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
445 .object_id = DPAA2_MC_DPIO_DEVID,
446 .create = dpaa2_create_dpio_device,
449 RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);