4 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
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43 #include <sys/types.h>
44 #include <sys/queue.h>
45 #include <sys/ioctl.h>
48 #include <sys/syscall.h>
49 #include <sys/epoll.h>
50 #include<sys/eventfd.h>
53 #include <rte_ethdev.h>
54 #include <rte_malloc.h>
55 #include <rte_memcpy.h>
56 #include <rte_string_fns.h>
57 #include <rte_cycles.h>
58 #include <rte_kvargs.h>
61 #include <fslmc_logs.h>
62 #include <fslmc_vfio.h>
63 #include "dpaa2_hw_pvt.h"
64 #include "dpaa2_hw_dpio.h"
65 #include <mc/fsl_dpmng.h>
67 #define NUM_HOST_CPUS RTE_MAX_LCORE
69 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
70 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
72 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
74 TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev);
75 static struct dpio_dev_list dpio_dev_list
76 = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */
77 static uint32_t io_space_count;
79 /*Stashing Macros default for LS208x*/
80 static int dpaa2_core_cluster_base = 0x04;
81 static int dpaa2_cluster_sz = 2;
83 /* For LS208X platform There are four clusters with following mapping:
84 * Cluster 1 (ID = x04) : CPU0, CPU1;
85 * Cluster 2 (ID = x05) : CPU2, CPU3;
86 * Cluster 3 (ID = x06) : CPU4, CPU5;
87 * Cluster 4 (ID = x07) : CPU6, CPU7;
89 /* For LS108X platform There are two clusters with following mapping:
90 * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
91 * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
94 /* Set the STASH Destination depending on Current CPU ID.
95 * e.g. Valid values of SDEST are 4,5,6,7. Where,
96 * CPU 0-1 will have SDEST 4
97 * CPU 2-3 will have SDEST 5.....and so on.
100 dpaa2_core_cluster_sdest(int cpu_id)
102 int x = cpu_id / dpaa2_cluster_sz;
107 return dpaa2_core_cluster_base + x;
110 static void dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id)
112 #define STRING_LEN 28
113 #define COMMAND_LEN 50
114 uint32_t cpu_mask = 1;
117 char *temp = NULL, *token = NULL;
118 char string[STRING_LEN], command[COMMAND_LEN];
121 snprintf(string, STRING_LEN, "dpio.%d", dpio_id);
122 file = fopen("/proc/interrupts", "r");
124 PMD_DRV_LOG(WARNING, "Failed to open /proc/interrupts file\n");
127 while (getline(&temp, &len, file) != -1) {
128 if ((strstr(temp, string)) != NULL) {
129 token = strtok(temp, ":");
135 PMD_DRV_LOG(WARNING, "Failed to get interrupt id for dpio.%d\n",
143 cpu_mask = cpu_mask << rte_lcore_id();
144 snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity",
146 ret = system(command);
149 "Failed to affine interrupts on respective core\n");
151 PMD_DRV_LOG(WARNING, " %s command is executed\n", command);
157 static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev)
159 struct epoll_event epoll_ev;
160 int eventfd, dpio_epoll_fd, ret;
161 int threshold = 0x3, timeout = 0xFF;
163 dpio_epoll_fd = epoll_create(1);
164 ret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0);
166 PMD_DRV_LOG(ERR, "Interrupt registeration failed\n");
170 if (getenv("DPAA2_PORTAL_INTR_THRESHOLD"))
171 threshold = atoi(getenv("DPAA2_PORTAL_INTR_THRESHOLD"));
173 if (getenv("DPAA2_PORTAL_INTR_TIMEOUT"))
174 sscanf(getenv("DPAA2_PORTAL_INTR_TIMEOUT"), "%x", &timeout);
176 qbman_swp_interrupt_set_trigger(dpio_dev->sw_portal,
177 QBMAN_SWP_INTERRUPT_DQRI);
178 qbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff);
179 qbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0);
180 qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);
181 qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);
183 eventfd = dpio_dev->intr_handle.fd;
184 epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;
185 epoll_ev.data.fd = eventfd;
187 ret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev);
189 PMD_DRV_LOG(ERR, "epoll_ctl failed\n");
192 dpio_dev->epoll_fd = dpio_epoll_fd;
194 dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id);
200 configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
202 struct qbman_swp_desc p_des;
203 struct dpio_attr attr;
205 dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io));
206 if (!dpio_dev->dpio) {
207 PMD_INIT_LOG(ERR, "Memory allocation failure\n");
211 PMD_DRV_LOG(DEBUG, "\t Allocated DPIO Portal[%p]", dpio_dev->dpio);
212 dpio_dev->dpio->regs = dpio_dev->mc_portal;
213 if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
215 PMD_INIT_LOG(ERR, "Failed to allocate IO space\n");
216 free(dpio_dev->dpio);
220 if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
221 PMD_INIT_LOG(ERR, "Failed to reset dpio\n");
222 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
223 free(dpio_dev->dpio);
227 if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
228 PMD_INIT_LOG(ERR, "Failed to Enable dpio\n");
229 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
230 free(dpio_dev->dpio);
234 if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
235 dpio_dev->token, &attr)) {
236 PMD_INIT_LOG(ERR, "DPIO Get attribute failed\n");
237 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
238 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
239 free(dpio_dev->dpio);
243 PMD_INIT_LOG(DEBUG, "Qbman Portal ID %d", attr.qbman_portal_id);
245 /* Configure & setup SW portal */
247 p_des.idx = attr.qbman_portal_id;
248 p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
249 p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
251 p_des.qman_version = attr.qbman_version;
253 dpio_dev->sw_portal = qbman_swp_init(&p_des);
254 if (dpio_dev->sw_portal == NULL) {
255 PMD_DRV_LOG(ERR, " QBMan SW Portal Init failed\n");
256 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
257 free(dpio_dev->dpio);
265 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
268 static int first_time;
270 /* find the SoC type for the first time */
272 struct mc_soc_version mc_plat_info = {0};
274 if (mc_get_soc_version(dpio_dev->dpio,
275 CMD_PRI_LOW, &mc_plat_info)) {
276 PMD_INIT_LOG(ERR, "\tmc_get_soc_version failed\n");
277 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) {
278 dpaa2_core_cluster_base = 0x02;
279 dpaa2_cluster_sz = 4;
280 PMD_INIT_LOG(DEBUG, "\tLS108x (A53) Platform Detected");
285 /* Set the Stashing Destination */
287 cpu_id = rte_get_master_lcore();
289 RTE_LOG(ERR, PMD, "\tGetting CPU Index failed\n");
293 /* Set the STASH Destination depending on Current CPU ID.
294 * Valid values of SDEST are 4,5,6,7. Where,
297 sdest = dpaa2_core_cluster_sdest(cpu_id);
298 PMD_DRV_LOG(DEBUG, "Portal= %d CPU= %u SDEST= %d",
299 dpio_dev->index, cpu_id, sdest);
301 ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
302 dpio_dev->token, sdest);
304 PMD_DRV_LOG(ERR, "%d ERROR in SDEST\n", ret);
308 if (dpaa2_dpio_intr_init(dpio_dev)) {
309 PMD_DRV_LOG(ERR, "Interrupt registration failed for dpio\n");
316 struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
318 struct dpaa2_dpio_dev *dpio_dev = NULL;
321 /* Get DPIO dev handle from list using index */
322 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
323 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
329 PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu",
330 dpio_dev, dpio_dev->index, syscall(SYS_gettid));
332 ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
334 PMD_DRV_LOG(ERR, "dpaa2_configure_stashing failed");
340 dpaa2_affine_qbman_swp(void)
342 unsigned int lcore_id = rte_lcore_id();
343 uint64_t tid = syscall(SYS_gettid);
345 if (lcore_id == LCORE_ID_ANY)
346 lcore_id = rte_get_master_lcore();
347 /* if the core id is not supported */
348 else if (lcore_id >= RTE_MAX_LCORE)
351 if (dpaa2_io_portal[lcore_id].dpio_dev) {
352 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
353 " between thread %lu and current %lu",
354 dpaa2_io_portal[lcore_id].dpio_dev,
355 dpaa2_io_portal[lcore_id].dpio_dev->index,
356 dpaa2_io_portal[lcore_id].net_tid,
358 RTE_PER_LCORE(_dpaa2_io).dpio_dev
359 = dpaa2_io_portal[lcore_id].dpio_dev;
360 rte_atomic16_inc(&dpaa2_io_portal
361 [lcore_id].dpio_dev->ref_count);
362 dpaa2_io_portal[lcore_id].net_tid = tid;
364 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
365 dpaa2_io_portal[lcore_id].dpio_dev,
366 dpaa2_io_portal[lcore_id].dpio_dev->index,
371 /* Populate the dpaa2_io_portal structure */
372 dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id);
374 if (dpaa2_io_portal[lcore_id].dpio_dev) {
375 RTE_PER_LCORE(_dpaa2_io).dpio_dev
376 = dpaa2_io_portal[lcore_id].dpio_dev;
377 dpaa2_io_portal[lcore_id].net_tid = tid;
386 dpaa2_affine_qbman_swp_sec(void)
388 unsigned int lcore_id = rte_lcore_id();
389 uint64_t tid = syscall(SYS_gettid);
391 if (lcore_id == LCORE_ID_ANY)
392 lcore_id = rte_get_master_lcore();
393 /* if the core id is not supported */
394 else if (lcore_id >= RTE_MAX_LCORE)
397 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
398 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
399 " between thread %lu and current %lu",
400 dpaa2_io_portal[lcore_id].sec_dpio_dev,
401 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
402 dpaa2_io_portal[lcore_id].sec_tid,
404 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
405 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
406 rte_atomic16_inc(&dpaa2_io_portal
407 [lcore_id].sec_dpio_dev->ref_count);
408 dpaa2_io_portal[lcore_id].sec_tid = tid;
410 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
411 dpaa2_io_portal[lcore_id].sec_dpio_dev,
412 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
417 /* Populate the dpaa2_io_portal structure */
418 dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp(lcore_id);
420 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
421 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
422 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
423 dpaa2_io_portal[lcore_id].sec_tid = tid;
431 dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev,
432 struct vfio_device_info *obj_info,
435 struct dpaa2_dpio_dev *dpio_dev;
436 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
439 if (obj_info->num_regions < NUM_DPIO_REGIONS) {
440 PMD_INIT_LOG(ERR, "ERROR, Not sufficient number "
441 "of DPIO regions.\n");
445 dpio_dev = rte_malloc(NULL, sizeof(struct dpaa2_dpio_dev),
446 RTE_CACHE_LINE_SIZE);
448 PMD_INIT_LOG(ERR, "Memory allocation failed for DPIO Device\n");
452 dpio_dev->dpio = NULL;
453 dpio_dev->hw_id = object_id;
454 dpio_dev->intr_handle.vfio_dev_fd = vdev->fd;
455 rte_atomic16_init(&dpio_dev->ref_count);
456 /* Using single portal for all devices */
457 dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX];
460 vfio_dev_fd = dpio_dev->intr_handle.vfio_dev_fd;
461 if (ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
462 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
467 dpio_dev->ce_size = reg_info.size;
468 dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,
469 PROT_WRITE | PROT_READ, MAP_SHARED,
470 vfio_dev_fd, reg_info.offset);
472 /* Create Mapping for QBMan Cache Enabled area. This is a fix for
473 * SMMU fault for DQRR statshing transaction.
475 if (vfio_dmamap_mem_region(dpio_dev->qbman_portal_ce_paddr,
476 reg_info.offset, reg_info.size)) {
477 PMD_INIT_LOG(ERR, "DMAMAP for Portal CE area failed.\n");
483 if (ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
484 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
489 dpio_dev->ci_size = reg_info.size;
490 dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,
491 PROT_WRITE | PROT_READ, MAP_SHARED,
492 vfio_dev_fd, reg_info.offset);
494 if (configure_dpio_qbman_swp(dpio_dev)) {
496 "Fail to configure the dpio qbman portal for %d\n",
503 dpio_dev->index = io_space_count;
504 TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);
505 PMD_INIT_LOG(DEBUG, "DPAA2: Added [dpio.%d]", object_id);
511 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
515 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
516 if (q_storage->dq_storage[i])
517 rte_free(q_storage->dq_storage[i]);
522 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
526 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
527 q_storage->dq_storage[i] = rte_malloc(NULL,
528 DPAA2_DQRR_RING_SIZE * sizeof(struct qbman_result),
529 RTE_CACHE_LINE_SIZE);
530 if (!q_storage->dq_storage[i])
536 rte_free(q_storage->dq_storage[i]);
541 static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
542 .object_id = DPAA2_MC_DPIO_DEVID,
543 .create = dpaa2_create_dpio_device,
546 RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);