1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2018 NXP
17 #include <sys/types.h>
18 #include <sys/queue.h>
19 #include <sys/ioctl.h>
22 #include <sys/syscall.h>
23 #include <sys/epoll.h>
24 #include<sys/eventfd.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_malloc.h>
29 #include <rte_memcpy.h>
30 #include <rte_string_fns.h>
31 #include <rte_cycles.h>
32 #include <rte_kvargs.h>
35 #include <fslmc_logs.h>
36 #include <rte_fslmc.h>
37 #include "dpaa2_hw_pvt.h"
38 #include "dpaa2_hw_dpio.h"
39 #include <mc/fsl_dpmng.h>
41 #define NUM_HOST_CPUS RTE_MAX_LCORE
43 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
44 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
46 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
48 TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev);
49 static struct dpio_dev_list dpio_dev_list
50 = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */
51 static uint32_t io_space_count;
53 /* Variable to store DPAA2 platform type */
54 uint32_t dpaa2_svr_family;
56 /* Variable to store DPAA2 DQRR size */
57 uint8_t dpaa2_dqrr_size;
58 /* Variable to store DPAA2 EQCR size */
59 uint8_t dpaa2_eqcr_size;
61 /*Stashing Macros default for LS208x*/
62 static int dpaa2_core_cluster_base = 0x04;
63 static int dpaa2_cluster_sz = 2;
65 /* For LS208X platform There are four clusters with following mapping:
66 * Cluster 1 (ID = x04) : CPU0, CPU1;
67 * Cluster 2 (ID = x05) : CPU2, CPU3;
68 * Cluster 3 (ID = x06) : CPU4, CPU5;
69 * Cluster 4 (ID = x07) : CPU6, CPU7;
71 /* For LS108X platform There are two clusters with following mapping:
72 * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
73 * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
75 /* For LX2160 platform There are four clusters with following mapping:
76 * Cluster 1 (ID = x00) : CPU0, CPU1;
77 * Cluster 2 (ID = x01) : CPU2, CPU3;
78 * Cluster 3 (ID = x02) : CPU4, CPU5;
79 * Cluster 4 (ID = x03) : CPU6, CPU7;
80 * Cluster 1 (ID = x04) : CPU8, CPU9;
81 * Cluster 2 (ID = x05) : CPU10, CP11;
82 * Cluster 3 (ID = x06) : CPU12, CPU13;
83 * Cluster 4 (ID = x07) : CPU14, CPU15;
87 dpaa2_core_cluster_sdest(int cpu_id)
89 int x = cpu_id / dpaa2_cluster_sz;
91 return dpaa2_core_cluster_base + x;
94 #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV
95 static void dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id)
98 #define COMMAND_LEN 50
99 uint32_t cpu_mask = 1;
102 char *temp = NULL, *token = NULL;
103 char string[STRING_LEN], command[COMMAND_LEN];
106 snprintf(string, STRING_LEN, "dpio.%d", dpio_id);
107 file = fopen("/proc/interrupts", "r");
109 DPAA2_BUS_WARN("Failed to open /proc/interrupts file");
112 while (getline(&temp, &len, file) != -1) {
113 if ((strstr(temp, string)) != NULL) {
114 token = strtok(temp, ":");
120 DPAA2_BUS_WARN("Failed to get interrupt id for dpio.%d",
128 cpu_mask = cpu_mask << rte_lcore_id();
129 snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity",
131 ret = system(command);
134 "Failed to affine interrupts on respective core");
136 DPAA2_BUS_DEBUG(" %s command is executed", command);
142 static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev)
144 struct epoll_event epoll_ev;
145 int eventfd, dpio_epoll_fd, ret;
146 int threshold = 0x3, timeout = 0xFF;
148 dpio_epoll_fd = epoll_create(1);
149 ret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0);
151 DPAA2_BUS_ERR("Interrupt registeration failed");
155 if (getenv("DPAA2_PORTAL_INTR_THRESHOLD"))
156 threshold = atoi(getenv("DPAA2_PORTAL_INTR_THRESHOLD"));
158 if (getenv("DPAA2_PORTAL_INTR_TIMEOUT"))
159 sscanf(getenv("DPAA2_PORTAL_INTR_TIMEOUT"), "%x", &timeout);
161 qbman_swp_interrupt_set_trigger(dpio_dev->sw_portal,
162 QBMAN_SWP_INTERRUPT_DQRI);
163 qbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff);
164 qbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0);
165 qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);
166 qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);
168 eventfd = dpio_dev->intr_handle.fd;
169 epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;
170 epoll_ev.data.fd = eventfd;
172 ret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev);
174 DPAA2_BUS_ERR("epoll_ctl failed");
177 dpio_dev->epoll_fd = dpio_epoll_fd;
179 dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id);
186 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
190 /* Set the Stashing Destination */
192 cpu_id = rte_get_master_lcore();
194 DPAA2_BUS_ERR("Getting CPU Index failed");
198 /* Set the STASH Destination depending on Current CPU ID.
199 * Valid values of SDEST are 4,5,6,7. Where,
202 sdest = dpaa2_core_cluster_sdest(cpu_id);
203 DPAA2_BUS_DEBUG("Portal= %d CPU= %u SDEST= %d",
204 dpio_dev->index, cpu_id, sdest);
206 ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
207 dpio_dev->token, sdest);
209 DPAA2_BUS_ERR("%d ERROR in SDEST", ret);
213 #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV
214 if (dpaa2_dpio_intr_init(dpio_dev)) {
215 DPAA2_BUS_ERR("Interrupt registration failed for dpio");
223 struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
225 struct dpaa2_dpio_dev *dpio_dev = NULL;
228 /* Get DPIO dev handle from list using index */
229 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
230 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
236 DPAA2_BUS_DEBUG("New Portal %p (%d) affined thread - %lu",
237 dpio_dev, dpio_dev->index, syscall(SYS_gettid));
239 ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
241 DPAA2_BUS_ERR("dpaa2_configure_stashing failed");
247 dpaa2_affine_qbman_swp(void)
249 unsigned int lcore_id = rte_lcore_id();
250 uint64_t tid = syscall(SYS_gettid);
252 if (lcore_id == LCORE_ID_ANY)
253 lcore_id = rte_get_master_lcore();
254 /* if the core id is not supported */
255 else if (lcore_id >= RTE_MAX_LCORE)
258 if (dpaa2_io_portal[lcore_id].dpio_dev) {
259 DPAA2_BUS_DP_INFO("DPAA Portal=%p (%d) is being shared"
260 " between thread %" PRIu64 " and current "
262 dpaa2_io_portal[lcore_id].dpio_dev,
263 dpaa2_io_portal[lcore_id].dpio_dev->index,
264 dpaa2_io_portal[lcore_id].net_tid,
266 RTE_PER_LCORE(_dpaa2_io).dpio_dev
267 = dpaa2_io_portal[lcore_id].dpio_dev;
268 rte_atomic16_inc(&dpaa2_io_portal
269 [lcore_id].dpio_dev->ref_count);
270 dpaa2_io_portal[lcore_id].net_tid = tid;
272 DPAA2_BUS_DP_DEBUG("Old Portal=%p (%d) affined thread - "
274 dpaa2_io_portal[lcore_id].dpio_dev,
275 dpaa2_io_portal[lcore_id].dpio_dev->index,
280 /* Populate the dpaa2_io_portal structure */
281 dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id);
283 if (dpaa2_io_portal[lcore_id].dpio_dev) {
284 RTE_PER_LCORE(_dpaa2_io).dpio_dev
285 = dpaa2_io_portal[lcore_id].dpio_dev;
286 dpaa2_io_portal[lcore_id].net_tid = tid;
295 dpaa2_affine_qbman_ethrx_swp(void)
297 unsigned int lcore_id = rte_lcore_id();
298 uint64_t tid = syscall(SYS_gettid);
300 if (lcore_id == LCORE_ID_ANY)
301 lcore_id = rte_get_master_lcore();
302 /* if the core id is not supported */
303 else if (lcore_id >= RTE_MAX_LCORE)
306 if (dpaa2_io_portal[lcore_id].ethrx_dpio_dev) {
308 "DPAA Portal=%p (%d) is being shared between thread"
309 " %" PRIu64 " and current %" PRIu64 "\n",
310 dpaa2_io_portal[lcore_id].ethrx_dpio_dev,
311 dpaa2_io_portal[lcore_id].ethrx_dpio_dev->index,
312 dpaa2_io_portal[lcore_id].sec_tid,
314 RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev
315 = dpaa2_io_portal[lcore_id].ethrx_dpio_dev;
316 rte_atomic16_inc(&dpaa2_io_portal
317 [lcore_id].ethrx_dpio_dev->ref_count);
318 dpaa2_io_portal[lcore_id].sec_tid = tid;
321 "Old Portal=%p (%d) affined thread"
323 dpaa2_io_portal[lcore_id].ethrx_dpio_dev,
324 dpaa2_io_portal[lcore_id].ethrx_dpio_dev->index,
329 /* Populate the dpaa2_io_portal structure */
330 dpaa2_io_portal[lcore_id].ethrx_dpio_dev =
331 dpaa2_get_qbman_swp(lcore_id);
333 if (dpaa2_io_portal[lcore_id].ethrx_dpio_dev) {
334 RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev
335 = dpaa2_io_portal[lcore_id].ethrx_dpio_dev;
336 dpaa2_io_portal[lcore_id].sec_tid = tid;
344 dpaa2_create_dpio_device(int vdev_fd,
345 struct vfio_device_info *obj_info,
348 struct dpaa2_dpio_dev *dpio_dev = NULL;
349 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
350 struct qbman_swp_desc p_des;
351 struct dpio_attr attr;
353 if (obj_info->num_regions < NUM_DPIO_REGIONS) {
354 DPAA2_BUS_ERR("Not sufficient number of DPIO regions");
358 dpio_dev = rte_zmalloc(NULL, sizeof(struct dpaa2_dpio_dev),
359 RTE_CACHE_LINE_SIZE);
361 DPAA2_BUS_ERR("Memory allocation failed for DPIO Device");
365 dpio_dev->dpio = NULL;
366 dpio_dev->hw_id = object_id;
367 rte_atomic16_init(&dpio_dev->ref_count);
368 /* Using single portal for all devices */
369 dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX];
371 dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io));
372 if (!dpio_dev->dpio) {
373 DPAA2_BUS_ERR("Memory allocation failure");
377 dpio_dev->dpio->regs = dpio_dev->mc_portal;
378 if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
380 DPAA2_BUS_ERR("Failed to allocate IO space");
384 if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
385 DPAA2_BUS_ERR("Failed to reset dpio");
389 if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
390 DPAA2_BUS_ERR("Failed to Enable dpio");
394 if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
395 dpio_dev->token, &attr)) {
396 DPAA2_BUS_ERR("DPIO Get attribute failed");
400 /* find the SoC type for the first time */
401 if (!dpaa2_svr_family) {
402 struct mc_soc_version mc_plat_info = {0};
404 if (mc_get_soc_version(dpio_dev->dpio,
405 CMD_PRI_LOW, &mc_plat_info)) {
406 DPAA2_BUS_ERR("Unable to get SoC version information");
407 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) {
408 dpaa2_core_cluster_base = 0x02;
409 dpaa2_cluster_sz = 4;
410 DPAA2_BUS_DEBUG("LS108x (A53) Platform Detected");
411 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LX2160A) {
412 dpaa2_core_cluster_base = 0x00;
413 dpaa2_cluster_sz = 2;
414 DPAA2_BUS_DEBUG("LX2160 Platform Detected");
416 dpaa2_svr_family = (mc_plat_info.svr & 0xffff0000);
418 if (dpaa2_svr_family == SVR_LX2160A) {
419 dpaa2_dqrr_size = DPAA2_LX2_DQRR_RING_SIZE;
420 dpaa2_eqcr_size = DPAA2_LX2_EQCR_RING_SIZE;
422 dpaa2_dqrr_size = DPAA2_DQRR_RING_SIZE;
423 dpaa2_eqcr_size = DPAA2_EQCR_RING_SIZE;
427 if (dpaa2_svr_family == SVR_LX2160A)
428 reg_info.index = DPAA2_SWP_CENA_MEM_REGION;
430 reg_info.index = DPAA2_SWP_CENA_REGION;
432 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
433 DPAA2_BUS_ERR("vfio: error getting region info");
437 dpio_dev->ce_size = reg_info.size;
438 dpio_dev->qbman_portal_ce_paddr = (size_t)mmap(NULL, reg_info.size,
439 PROT_WRITE | PROT_READ, MAP_SHARED,
440 vdev_fd, reg_info.offset);
442 reg_info.index = DPAA2_SWP_CINH_REGION;
443 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
444 DPAA2_BUS_ERR("vfio: error getting region info");
448 dpio_dev->ci_size = reg_info.size;
449 dpio_dev->qbman_portal_ci_paddr = (size_t)mmap(NULL, reg_info.size,
450 PROT_WRITE | PROT_READ, MAP_SHARED,
451 vdev_fd, reg_info.offset);
453 /* Configure & setup SW portal */
455 p_des.idx = attr.qbman_portal_id;
456 p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
457 p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
459 p_des.qman_version = attr.qbman_version;
461 dpio_dev->sw_portal = qbman_swp_init(&p_des);
462 if (dpio_dev->sw_portal == NULL) {
463 DPAA2_BUS_ERR("QBMan SW Portal Init failed");
468 dpio_dev->index = io_space_count;
470 if (rte_dpaa2_vfio_setup_intr(&dpio_dev->intr_handle, vdev_fd, 1)) {
471 DPAA2_BUS_ERR("Fail to setup interrupt for %d",
476 TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);
481 if (dpio_dev->dpio) {
482 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
483 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
484 free(dpio_dev->dpio);
491 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
495 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
496 if (q_storage->dq_storage[i])
497 rte_free(q_storage->dq_storage[i]);
502 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
506 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
507 q_storage->dq_storage[i] = rte_malloc(NULL,
508 dpaa2_dqrr_size * sizeof(struct qbman_result),
509 RTE_CACHE_LINE_SIZE);
510 if (!q_storage->dq_storage[i])
516 rte_free(q_storage->dq_storage[i]);
521 static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
522 .dev_type = DPAA2_IO,
523 .create = dpaa2_create_dpio_device,
526 RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);