1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
17 #include <sys/types.h>
18 #include <sys/queue.h>
19 #include <sys/ioctl.h>
22 #include <sys/syscall.h>
23 #include <sys/epoll.h>
24 #include<sys/eventfd.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_malloc.h>
29 #include <rte_memcpy.h>
30 #include <rte_string_fns.h>
31 #include <rte_cycles.h>
32 #include <rte_kvargs.h>
35 #include <fslmc_logs.h>
36 #include <rte_fslmc.h>
37 #include "dpaa2_hw_pvt.h"
38 #include "dpaa2_hw_dpio.h"
39 #include <mc/fsl_dpmng.h>
41 #define NUM_HOST_CPUS RTE_MAX_LCORE
43 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
44 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
46 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
48 TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev);
49 static struct dpio_dev_list dpio_dev_list
50 = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */
51 static uint32_t io_space_count;
53 /* Variable to store DPAA2 platform type */
54 uint32_t dpaa2_svr_family;
56 /*Stashing Macros default for LS208x*/
57 static int dpaa2_core_cluster_base = 0x04;
58 static int dpaa2_cluster_sz = 2;
60 /* For LS208X platform There are four clusters with following mapping:
61 * Cluster 1 (ID = x04) : CPU0, CPU1;
62 * Cluster 2 (ID = x05) : CPU2, CPU3;
63 * Cluster 3 (ID = x06) : CPU4, CPU5;
64 * Cluster 4 (ID = x07) : CPU6, CPU7;
66 /* For LS108X platform There are two clusters with following mapping:
67 * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
68 * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
70 /* For LX2160 platform There are four clusters with following mapping:
71 * Cluster 1 (ID = x00) : CPU0, CPU1;
72 * Cluster 2 (ID = x01) : CPU2, CPU3;
73 * Cluster 3 (ID = x02) : CPU4, CPU5;
74 * Cluster 4 (ID = x03) : CPU6, CPU7;
75 * Cluster 1 (ID = x04) : CPU8, CPU9;
76 * Cluster 2 (ID = x05) : CPU10, CP11;
77 * Cluster 3 (ID = x06) : CPU12, CPU13;
78 * Cluster 4 (ID = x07) : CPU14, CPU15;
82 dpaa2_core_cluster_sdest(int cpu_id)
84 int x = cpu_id / dpaa2_cluster_sz;
86 return dpaa2_core_cluster_base + x;
89 #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV
90 static void dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id)
93 #define COMMAND_LEN 50
94 uint32_t cpu_mask = 1;
97 char *temp = NULL, *token = NULL;
98 char string[STRING_LEN], command[COMMAND_LEN];
101 snprintf(string, STRING_LEN, "dpio.%d", dpio_id);
102 file = fopen("/proc/interrupts", "r");
104 PMD_DRV_LOG(WARNING, "Failed to open /proc/interrupts file\n");
107 while (getline(&temp, &len, file) != -1) {
108 if ((strstr(temp, string)) != NULL) {
109 token = strtok(temp, ":");
115 PMD_DRV_LOG(WARNING, "Failed to get interrupt id for dpio.%d\n",
123 cpu_mask = cpu_mask << rte_lcore_id();
124 snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity",
126 ret = system(command);
129 "Failed to affine interrupts on respective core\n");
131 PMD_DRV_LOG(WARNING, " %s command is executed\n", command);
137 static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev)
139 struct epoll_event epoll_ev;
140 int eventfd, dpio_epoll_fd, ret;
141 int threshold = 0x3, timeout = 0xFF;
143 dpio_epoll_fd = epoll_create(1);
144 ret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0);
146 PMD_DRV_LOG(ERR, "Interrupt registeration failed\n");
150 if (getenv("DPAA2_PORTAL_INTR_THRESHOLD"))
151 threshold = atoi(getenv("DPAA2_PORTAL_INTR_THRESHOLD"));
153 if (getenv("DPAA2_PORTAL_INTR_TIMEOUT"))
154 sscanf(getenv("DPAA2_PORTAL_INTR_TIMEOUT"), "%x", &timeout);
156 qbman_swp_interrupt_set_trigger(dpio_dev->sw_portal,
157 QBMAN_SWP_INTERRUPT_DQRI);
158 qbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff);
159 qbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0);
160 qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);
161 qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);
163 eventfd = dpio_dev->intr_handle.fd;
164 epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;
165 epoll_ev.data.fd = eventfd;
167 ret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev);
169 PMD_DRV_LOG(ERR, "epoll_ctl failed\n");
172 dpio_dev->epoll_fd = dpio_epoll_fd;
174 dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id);
181 configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
183 struct qbman_swp_desc p_des;
184 struct dpio_attr attr;
186 dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io));
187 if (!dpio_dev->dpio) {
188 PMD_INIT_LOG(ERR, "Memory allocation failure\n");
192 PMD_DRV_LOG(DEBUG, "Allocated DPIO Portal[%p]", dpio_dev->dpio);
193 dpio_dev->dpio->regs = dpio_dev->mc_portal;
194 if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
196 PMD_INIT_LOG(ERR, "Failed to allocate IO space\n");
197 free(dpio_dev->dpio);
201 if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
202 PMD_INIT_LOG(ERR, "Failed to reset dpio\n");
203 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
204 free(dpio_dev->dpio);
208 if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
209 PMD_INIT_LOG(ERR, "Failed to Enable dpio\n");
210 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
211 free(dpio_dev->dpio);
215 if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
216 dpio_dev->token, &attr)) {
217 PMD_INIT_LOG(ERR, "DPIO Get attribute failed\n");
218 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
219 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
220 free(dpio_dev->dpio);
224 /* Configure & setup SW portal */
226 p_des.idx = attr.qbman_portal_id;
227 p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
228 p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
230 p_des.qman_version = attr.qbman_version;
232 dpio_dev->sw_portal = qbman_swp_init(&p_des);
233 if (dpio_dev->sw_portal == NULL) {
234 PMD_DRV_LOG(ERR, " QBMan SW Portal Init failed\n");
235 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
236 free(dpio_dev->dpio);
244 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
248 /* Set the Stashing Destination */
250 cpu_id = rte_get_master_lcore();
252 RTE_LOG(ERR, PMD, "\tGetting CPU Index failed\n");
256 /* Set the STASH Destination depending on Current CPU ID.
257 * Valid values of SDEST are 4,5,6,7. Where,
260 sdest = dpaa2_core_cluster_sdest(cpu_id);
261 PMD_DRV_LOG(DEBUG, "Portal= %d CPU= %u SDEST= %d",
262 dpio_dev->index, cpu_id, sdest);
264 ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
265 dpio_dev->token, sdest);
267 PMD_DRV_LOG(ERR, "%d ERROR in SDEST\n", ret);
271 #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV
272 if (dpaa2_dpio_intr_init(dpio_dev)) {
273 PMD_DRV_LOG(ERR, "Interrupt registration failed for dpio\n");
281 struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
283 struct dpaa2_dpio_dev *dpio_dev = NULL;
286 /* Get DPIO dev handle from list using index */
287 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
288 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
294 PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu",
295 dpio_dev, dpio_dev->index, syscall(SYS_gettid));
297 ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
299 PMD_DRV_LOG(ERR, "dpaa2_configure_stashing failed");
305 dpaa2_affine_qbman_swp(void)
307 unsigned int lcore_id = rte_lcore_id();
308 uint64_t tid = syscall(SYS_gettid);
310 if (lcore_id == LCORE_ID_ANY)
311 lcore_id = rte_get_master_lcore();
312 /* if the core id is not supported */
313 else if (lcore_id >= RTE_MAX_LCORE)
316 if (dpaa2_io_portal[lcore_id].dpio_dev) {
317 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
318 " between thread %lu and current %lu",
319 dpaa2_io_portal[lcore_id].dpio_dev,
320 dpaa2_io_portal[lcore_id].dpio_dev->index,
321 dpaa2_io_portal[lcore_id].net_tid,
323 RTE_PER_LCORE(_dpaa2_io).dpio_dev
324 = dpaa2_io_portal[lcore_id].dpio_dev;
325 rte_atomic16_inc(&dpaa2_io_portal
326 [lcore_id].dpio_dev->ref_count);
327 dpaa2_io_portal[lcore_id].net_tid = tid;
329 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
330 dpaa2_io_portal[lcore_id].dpio_dev,
331 dpaa2_io_portal[lcore_id].dpio_dev->index,
336 /* Populate the dpaa2_io_portal structure */
337 dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id);
339 if (dpaa2_io_portal[lcore_id].dpio_dev) {
340 RTE_PER_LCORE(_dpaa2_io).dpio_dev
341 = dpaa2_io_portal[lcore_id].dpio_dev;
342 dpaa2_io_portal[lcore_id].net_tid = tid;
351 dpaa2_affine_qbman_swp_sec(void)
353 unsigned int lcore_id = rte_lcore_id();
354 uint64_t tid = syscall(SYS_gettid);
356 if (lcore_id == LCORE_ID_ANY)
357 lcore_id = rte_get_master_lcore();
358 /* if the core id is not supported */
359 else if (lcore_id >= RTE_MAX_LCORE)
362 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
363 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
364 " between thread %lu and current %lu",
365 dpaa2_io_portal[lcore_id].sec_dpio_dev,
366 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
367 dpaa2_io_portal[lcore_id].sec_tid,
369 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
370 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
371 rte_atomic16_inc(&dpaa2_io_portal
372 [lcore_id].sec_dpio_dev->ref_count);
373 dpaa2_io_portal[lcore_id].sec_tid = tid;
375 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
376 dpaa2_io_portal[lcore_id].sec_dpio_dev,
377 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
382 /* Populate the dpaa2_io_portal structure */
383 dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp(lcore_id);
385 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
386 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
387 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
388 dpaa2_io_portal[lcore_id].sec_tid = tid;
396 dpaa2_create_dpio_device(int vdev_fd,
397 struct vfio_device_info *obj_info,
400 struct dpaa2_dpio_dev *dpio_dev;
401 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
403 if (obj_info->num_regions < NUM_DPIO_REGIONS) {
404 PMD_INIT_LOG(ERR, "ERROR, Not sufficient number "
405 "of DPIO regions.\n");
409 dpio_dev = rte_malloc(NULL, sizeof(struct dpaa2_dpio_dev),
410 RTE_CACHE_LINE_SIZE);
412 PMD_INIT_LOG(ERR, "Memory allocation failed for DPIO Device\n");
416 dpio_dev->dpio = NULL;
417 dpio_dev->hw_id = object_id;
418 rte_atomic16_init(&dpio_dev->ref_count);
419 /* Using single portal for all devices */
420 dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX];
423 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
424 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
429 dpio_dev->ce_size = reg_info.size;
430 dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,
431 PROT_WRITE | PROT_READ, MAP_SHARED,
432 vdev_fd, reg_info.offset);
435 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
436 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
441 dpio_dev->ci_size = reg_info.size;
442 dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,
443 PROT_WRITE | PROT_READ, MAP_SHARED,
444 vdev_fd, reg_info.offset);
446 if (configure_dpio_qbman_swp(dpio_dev)) {
448 "Fail to configure the dpio qbman portal for %d\n",
455 dpio_dev->index = io_space_count;
457 if (rte_dpaa2_vfio_setup_intr(&dpio_dev->intr_handle, vdev_fd, 1)) {
458 PMD_INIT_LOG(ERR, "Fail to setup interrupt for %d\n",
463 /* find the SoC type for the first time */
464 if (!dpaa2_svr_family) {
465 struct mc_soc_version mc_plat_info = {0};
467 if (mc_get_soc_version(dpio_dev->dpio,
468 CMD_PRI_LOW, &mc_plat_info)) {
469 PMD_INIT_LOG(ERR, "\tmc_get_soc_version failed\n");
470 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) {
471 dpaa2_core_cluster_base = 0x02;
472 dpaa2_cluster_sz = 4;
473 PMD_INIT_LOG(DEBUG, "\tLS108x (A53) Platform Detected");
474 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LX2160A) {
475 dpaa2_core_cluster_base = 0x00;
476 dpaa2_cluster_sz = 2;
477 PMD_INIT_LOG(DEBUG, "\tLX2160 Platform Detected");
479 dpaa2_svr_family = (mc_plat_info.svr & 0xffff0000);
482 TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);
483 RTE_LOG(DEBUG, PMD, "DPAA2: Added [dpio.%d]\n", object_id);
489 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
493 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
494 if (q_storage->dq_storage[i])
495 rte_free(q_storage->dq_storage[i]);
500 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
504 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
505 q_storage->dq_storage[i] = rte_malloc(NULL,
506 DPAA2_DQRR_RING_SIZE * sizeof(struct qbman_result),
507 RTE_CACHE_LINE_SIZE);
508 if (!q_storage->dq_storage[i])
514 rte_free(q_storage->dq_storage[i]);
519 static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
520 .dev_type = DPAA2_IO,
521 .create = dpaa2_create_dpio_device,
524 RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);