4 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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43 #include <sys/types.h>
44 #include <sys/queue.h>
45 #include <sys/ioctl.h>
48 #include <sys/syscall.h>
49 #include <sys/epoll.h>
50 #include<sys/eventfd.h>
53 #include <rte_ethdev.h>
54 #include <rte_malloc.h>
55 #include <rte_memcpy.h>
56 #include <rte_string_fns.h>
57 #include <rte_cycles.h>
58 #include <rte_kvargs.h>
61 #include <fslmc_logs.h>
62 #include <rte_fslmc.h>
63 #include "dpaa2_hw_pvt.h"
64 #include "dpaa2_hw_dpio.h"
65 #include <mc/fsl_dpmng.h>
67 #define NUM_HOST_CPUS RTE_MAX_LCORE
69 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
70 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
72 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
74 TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev);
75 static struct dpio_dev_list dpio_dev_list
76 = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */
77 static uint32_t io_space_count;
79 /*Stashing Macros default for LS208x*/
80 static int dpaa2_core_cluster_base = 0x04;
81 static int dpaa2_cluster_sz = 2;
83 /* For LS208X platform There are four clusters with following mapping:
84 * Cluster 1 (ID = x04) : CPU0, CPU1;
85 * Cluster 2 (ID = x05) : CPU2, CPU3;
86 * Cluster 3 (ID = x06) : CPU4, CPU5;
87 * Cluster 4 (ID = x07) : CPU6, CPU7;
89 /* For LS108X platform There are two clusters with following mapping:
90 * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
91 * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
93 /* For LX2160 platform There are four clusters with following mapping:
94 * Cluster 1 (ID = x00) : CPU0, CPU1;
95 * Cluster 2 (ID = x01) : CPU2, CPU3;
96 * Cluster 3 (ID = x02) : CPU4, CPU5;
97 * Cluster 4 (ID = x03) : CPU6, CPU7;
98 * Cluster 1 (ID = x04) : CPU8, CPU9;
99 * Cluster 2 (ID = x05) : CPU10, CP11;
100 * Cluster 3 (ID = x06) : CPU12, CPU13;
101 * Cluster 4 (ID = x07) : CPU14, CPU15;
105 dpaa2_core_cluster_sdest(int cpu_id)
107 int x = cpu_id / dpaa2_cluster_sz;
109 return dpaa2_core_cluster_base + x;
112 static void dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id)
114 #define STRING_LEN 28
115 #define COMMAND_LEN 50
116 uint32_t cpu_mask = 1;
119 char *temp = NULL, *token = NULL;
120 char string[STRING_LEN], command[COMMAND_LEN];
123 snprintf(string, STRING_LEN, "dpio.%d", dpio_id);
124 file = fopen("/proc/interrupts", "r");
126 PMD_DRV_LOG(WARNING, "Failed to open /proc/interrupts file\n");
129 while (getline(&temp, &len, file) != -1) {
130 if ((strstr(temp, string)) != NULL) {
131 token = strtok(temp, ":");
137 PMD_DRV_LOG(WARNING, "Failed to get interrupt id for dpio.%d\n",
145 cpu_mask = cpu_mask << rte_lcore_id();
146 snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity",
148 ret = system(command);
151 "Failed to affine interrupts on respective core\n");
153 PMD_DRV_LOG(WARNING, " %s command is executed\n", command);
159 static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev)
161 struct epoll_event epoll_ev;
162 int eventfd, dpio_epoll_fd, ret;
163 int threshold = 0x3, timeout = 0xFF;
165 dpio_epoll_fd = epoll_create(1);
166 ret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0);
168 PMD_DRV_LOG(ERR, "Interrupt registeration failed\n");
172 if (getenv("DPAA2_PORTAL_INTR_THRESHOLD"))
173 threshold = atoi(getenv("DPAA2_PORTAL_INTR_THRESHOLD"));
175 if (getenv("DPAA2_PORTAL_INTR_TIMEOUT"))
176 sscanf(getenv("DPAA2_PORTAL_INTR_TIMEOUT"), "%x", &timeout);
178 qbman_swp_interrupt_set_trigger(dpio_dev->sw_portal,
179 QBMAN_SWP_INTERRUPT_DQRI);
180 qbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff);
181 qbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0);
182 qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);
183 qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);
185 eventfd = dpio_dev->intr_handle.fd;
186 epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;
187 epoll_ev.data.fd = eventfd;
189 ret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev);
191 PMD_DRV_LOG(ERR, "epoll_ctl failed\n");
194 dpio_dev->epoll_fd = dpio_epoll_fd;
196 dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id);
202 configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
204 struct qbman_swp_desc p_des;
205 struct dpio_attr attr;
207 dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io));
208 if (!dpio_dev->dpio) {
209 PMD_INIT_LOG(ERR, "Memory allocation failure\n");
213 PMD_DRV_LOG(DEBUG, "Allocated DPIO Portal[%p]", dpio_dev->dpio);
214 dpio_dev->dpio->regs = dpio_dev->mc_portal;
215 if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
217 PMD_INIT_LOG(ERR, "Failed to allocate IO space\n");
218 free(dpio_dev->dpio);
222 if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
223 PMD_INIT_LOG(ERR, "Failed to reset dpio\n");
224 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
225 free(dpio_dev->dpio);
229 if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
230 PMD_INIT_LOG(ERR, "Failed to Enable dpio\n");
231 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
232 free(dpio_dev->dpio);
236 if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
237 dpio_dev->token, &attr)) {
238 PMD_INIT_LOG(ERR, "DPIO Get attribute failed\n");
239 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
240 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
241 free(dpio_dev->dpio);
245 /* Configure & setup SW portal */
247 p_des.idx = attr.qbman_portal_id;
248 p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
249 p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
251 p_des.qman_version = attr.qbman_version;
253 dpio_dev->sw_portal = qbman_swp_init(&p_des);
254 if (dpio_dev->sw_portal == NULL) {
255 PMD_DRV_LOG(ERR, " QBMan SW Portal Init failed\n");
256 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
257 free(dpio_dev->dpio);
265 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
268 static int first_time;
270 /* find the SoC type for the first time */
272 struct mc_soc_version mc_plat_info = {0};
274 if (mc_get_soc_version(dpio_dev->dpio,
275 CMD_PRI_LOW, &mc_plat_info)) {
276 PMD_INIT_LOG(ERR, "\tmc_get_soc_version failed\n");
277 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) {
278 dpaa2_core_cluster_base = 0x02;
279 dpaa2_cluster_sz = 4;
280 PMD_INIT_LOG(DEBUG, "\tLS108x (A53) Platform Detected");
281 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LX2160A) {
282 dpaa2_core_cluster_base = 0x00;
283 dpaa2_cluster_sz = 2;
284 PMD_INIT_LOG(DEBUG, "\tLX2160 Platform Detected");
289 /* Set the Stashing Destination */
291 cpu_id = rte_get_master_lcore();
293 RTE_LOG(ERR, PMD, "\tGetting CPU Index failed\n");
297 /* Set the STASH Destination depending on Current CPU ID.
298 * Valid values of SDEST are 4,5,6,7. Where,
301 sdest = dpaa2_core_cluster_sdest(cpu_id);
302 PMD_DRV_LOG(DEBUG, "Portal= %d CPU= %u SDEST= %d",
303 dpio_dev->index, cpu_id, sdest);
305 ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
306 dpio_dev->token, sdest);
308 PMD_DRV_LOG(ERR, "%d ERROR in SDEST\n", ret);
312 if (dpaa2_dpio_intr_init(dpio_dev)) {
313 PMD_DRV_LOG(ERR, "Interrupt registration failed for dpio\n");
320 struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
322 struct dpaa2_dpio_dev *dpio_dev = NULL;
325 /* Get DPIO dev handle from list using index */
326 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
327 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
333 PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu",
334 dpio_dev, dpio_dev->index, syscall(SYS_gettid));
336 ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
338 PMD_DRV_LOG(ERR, "dpaa2_configure_stashing failed");
344 dpaa2_affine_qbman_swp(void)
346 unsigned int lcore_id = rte_lcore_id();
347 uint64_t tid = syscall(SYS_gettid);
349 if (lcore_id == LCORE_ID_ANY)
350 lcore_id = rte_get_master_lcore();
351 /* if the core id is not supported */
352 else if (lcore_id >= RTE_MAX_LCORE)
355 if (dpaa2_io_portal[lcore_id].dpio_dev) {
356 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
357 " between thread %lu and current %lu",
358 dpaa2_io_portal[lcore_id].dpio_dev,
359 dpaa2_io_portal[lcore_id].dpio_dev->index,
360 dpaa2_io_portal[lcore_id].net_tid,
362 RTE_PER_LCORE(_dpaa2_io).dpio_dev
363 = dpaa2_io_portal[lcore_id].dpio_dev;
364 rte_atomic16_inc(&dpaa2_io_portal
365 [lcore_id].dpio_dev->ref_count);
366 dpaa2_io_portal[lcore_id].net_tid = tid;
368 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
369 dpaa2_io_portal[lcore_id].dpio_dev,
370 dpaa2_io_portal[lcore_id].dpio_dev->index,
375 /* Populate the dpaa2_io_portal structure */
376 dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id);
378 if (dpaa2_io_portal[lcore_id].dpio_dev) {
379 RTE_PER_LCORE(_dpaa2_io).dpio_dev
380 = dpaa2_io_portal[lcore_id].dpio_dev;
381 dpaa2_io_portal[lcore_id].net_tid = tid;
390 dpaa2_affine_qbman_swp_sec(void)
392 unsigned int lcore_id = rte_lcore_id();
393 uint64_t tid = syscall(SYS_gettid);
395 if (lcore_id == LCORE_ID_ANY)
396 lcore_id = rte_get_master_lcore();
397 /* if the core id is not supported */
398 else if (lcore_id >= RTE_MAX_LCORE)
401 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
402 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
403 " between thread %lu and current %lu",
404 dpaa2_io_portal[lcore_id].sec_dpio_dev,
405 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
406 dpaa2_io_portal[lcore_id].sec_tid,
408 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
409 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
410 rte_atomic16_inc(&dpaa2_io_portal
411 [lcore_id].sec_dpio_dev->ref_count);
412 dpaa2_io_portal[lcore_id].sec_tid = tid;
414 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
415 dpaa2_io_portal[lcore_id].sec_dpio_dev,
416 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
421 /* Populate the dpaa2_io_portal structure */
422 dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp(lcore_id);
424 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
425 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
426 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
427 dpaa2_io_portal[lcore_id].sec_tid = tid;
435 dpaa2_create_dpio_device(int vdev_fd,
436 struct vfio_device_info *obj_info,
439 struct dpaa2_dpio_dev *dpio_dev;
440 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
442 if (obj_info->num_regions < NUM_DPIO_REGIONS) {
443 PMD_INIT_LOG(ERR, "ERROR, Not sufficient number "
444 "of DPIO regions.\n");
448 dpio_dev = rte_malloc(NULL, sizeof(struct dpaa2_dpio_dev),
449 RTE_CACHE_LINE_SIZE);
451 PMD_INIT_LOG(ERR, "Memory allocation failed for DPIO Device\n");
455 dpio_dev->dpio = NULL;
456 dpio_dev->hw_id = object_id;
457 rte_atomic16_init(&dpio_dev->ref_count);
458 /* Using single portal for all devices */
459 dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX];
462 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
463 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
468 dpio_dev->ce_size = reg_info.size;
469 dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,
470 PROT_WRITE | PROT_READ, MAP_SHARED,
471 vdev_fd, reg_info.offset);
474 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
475 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
480 dpio_dev->ci_size = reg_info.size;
481 dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,
482 PROT_WRITE | PROT_READ, MAP_SHARED,
483 vdev_fd, reg_info.offset);
485 if (configure_dpio_qbman_swp(dpio_dev)) {
487 "Fail to configure the dpio qbman portal for %d\n",
494 dpio_dev->index = io_space_count;
496 if (rte_dpaa2_vfio_setup_intr(&dpio_dev->intr_handle, vdev_fd, 1)) {
497 PMD_INIT_LOG(ERR, "Fail to setup interrupt for %d\n",
502 TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);
503 RTE_LOG(DEBUG, PMD, "DPAA2: Added [dpio.%d]\n", object_id);
509 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
513 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
514 if (q_storage->dq_storage[i])
515 rte_free(q_storage->dq_storage[i]);
520 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
524 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
525 q_storage->dq_storage[i] = rte_malloc(NULL,
526 DPAA2_DQRR_RING_SIZE * sizeof(struct qbman_result),
527 RTE_CACHE_LINE_SIZE);
528 if (!q_storage->dq_storage[i])
534 rte_free(q_storage->dq_storage[i]);
539 static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
540 .dev_type = DPAA2_IO,
541 .create = dpaa2_create_dpio_device,
544 RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);