1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2018 NXP
8 #ifndef _DPAA2_HW_PVT_H_
9 #define _DPAA2_HW_PVT_H_
11 #include <rte_eventdev.h>
12 #include <dpaax_iova_table.h>
14 #include <mc/fsl_mc_sys.h>
15 #include <fsl_qbman_portal.h>
23 #define lower_32_bits(x) ((uint32_t)(x))
24 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
26 #define SVR_LS1080A 0x87030000
27 #define SVR_LS2080A 0x87010000
28 #define SVR_LS2088A 0x87090000
29 #define SVR_LX2160A 0x87360000
32 #define VLAN_TAG_SIZE 4 /** < Vlan Header Length */
35 /* Maximum number of slots available in TX ring */
36 #define MAX_TX_RING_SLOTS 32
38 /* Maximum number of slots available in RX ring */
39 #define DPAA2_EQCR_RING_SIZE 8
40 /* Maximum number of slots available in RX ring on LX2 */
41 #define DPAA2_LX2_EQCR_RING_SIZE 32
43 /* Maximum number of slots available in RX ring */
44 #define DPAA2_DQRR_RING_SIZE 16
45 /* Maximum number of slots available in RX ring on LX2 */
46 #define DPAA2_LX2_DQRR_RING_SIZE 32
48 /* EQCR shift to get EQCR size (2 >> 3) = 8 for LS2/LS2 */
49 #define DPAA2_EQCR_SHIFT 3
50 /* EQCR shift to get EQCR size for LX2 (2 >> 5) = 32 for LX2 */
51 #define DPAA2_LX2_EQCR_SHIFT 5
53 #define DPAA2_SWP_CENA_REGION 0
54 #define DPAA2_SWP_CINH_REGION 1
55 #define DPAA2_SWP_CENA_MEM_REGION 2
57 #define MC_PORTAL_INDEX 0
58 #define NUM_DPIO_REGIONS 2
59 #define NUM_DQS_PER_QUEUE 2
61 /* Maximum release/acquire from QBMAN */
62 #define DPAA2_MBUF_MAX_ACQ_REL 7
64 #define DPAA2_MEMPOOL_OPS_NAME "dpaa2"
67 #define DPAA2_MBUF_HW_ANNOTATION 64
68 #define DPAA2_FD_PTA_SIZE 0
70 #if (DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM
71 #error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM"
74 /* we will re-use the HEADROOM for annotation in RX */
75 #define DPAA2_HW_BUF_RESERVE 0
76 #define DPAA2_PACKET_LAYOUT_ALIGN 64 /*changing from 256 */
78 #define DPAA2_DPCI_MAX_QUEUES 2
80 struct dpaa2_dpio_dev {
81 TAILQ_ENTRY(dpaa2_dpio_dev) next;
82 /**< Pointer to Next device instance */
83 uint16_t index; /**< Index of a instance in the list */
84 rte_atomic16_t ref_count;
85 /**< How many thread contexts are sharing this.*/
86 struct fsl_mc_io *dpio; /** handle to DPIO portal object */
88 struct qbman_swp *sw_portal; /** SW portal object */
89 const struct qbman_result *dqrr[4];
90 /**< DQRR Entry for this SW portal */
91 void *mc_portal; /**< MC Portal for configuring this device */
92 uintptr_t qbman_portal_ce_paddr;
93 /**< Physical address of Cache Enabled Area */
94 uintptr_t ce_size; /**< Size of the CE region */
95 uintptr_t qbman_portal_ci_paddr;
96 /**< Physical address of Cache Inhibit Area */
97 uintptr_t ci_size; /**< Size of the CI region */
98 struct rte_intr_handle intr_handle; /* Interrupt related info */
99 int32_t epoll_fd; /**< File descriptor created for interrupt polling */
100 int32_t hw_id; /**< An unique ID of this DPIO device instance */
103 struct dpaa2_dpbp_dev {
104 TAILQ_ENTRY(dpaa2_dpbp_dev) next;
105 /**< Pointer to Next device instance */
106 struct fsl_mc_io dpbp; /** handle to DPBP portal object */
108 rte_atomic16_t in_use;
109 uint32_t dpbp_id; /*HW ID for DPBP object */
112 struct queue_storage_info_t {
113 struct qbman_result *dq_storage[NUM_DQS_PER_QUEUE];
114 struct qbman_result *active_dqs;
115 uint8_t active_dpio_id;
117 uint8_t last_num_pkts;
122 typedef void (dpaa2_queue_cb_dqrr_t)(struct qbman_swp *swp,
123 const struct qbman_fd *fd,
124 const struct qbman_result *dq,
125 struct dpaa2_queue *rxq,
126 struct rte_event *ev);
129 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
131 int32_t eventfd; /*!< Event Fd of this queue */
132 uint32_t fqid; /*!< Unique ID of this queue */
133 uint8_t tc_index; /*!< traffic class identifier */
134 uint16_t flow_id; /*!< To be used by DPAA2 frmework */
139 struct queue_storage_info_t *q_storage;
140 struct qbman_result *cscn;
143 dpaa2_queue_cb_dqrr_t *cb;
144 struct dpaa2_bp_info *bp_array;
147 struct swp_active_dqs {
148 struct qbman_result *global_active_dqs;
149 uint64_t reserved[7];
152 #define NUM_MAX_SWP 64
154 extern struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
156 struct dpaa2_dpci_dev {
157 TAILQ_ENTRY(dpaa2_dpci_dev) next;
158 /**< Pointer to Next device instance */
159 struct fsl_mc_io dpci; /** handle to DPCI portal object */
161 rte_atomic16_t in_use;
162 uint32_t dpci_id; /*HW ID for DPCI object */
163 struct dpaa2_queue rx_queue[DPAA2_DPCI_MAX_QUEUES];
164 struct dpaa2_queue tx_queue[DPAA2_DPCI_MAX_QUEUES];
167 /*! Global MCP list */
168 extern void *(*rte_mcp_ptr_list);
170 /* Refer to Table 7-3 in SEC BG */
175 /* FMT must be 00, MSB is final bit */
176 uint32_t fin_bpid_offset;
178 uint32_t reserved[3]; /* Not used currently */
185 uint32_t fin_bpid_offset;
188 /* There are three types of frames: Single, Scatter Gather and Frame Lists */
189 enum qbman_fd_format {
194 /*Macros to define operations on FD*/
195 #define DPAA2_SET_FD_ADDR(fd, addr) do { \
196 (fd)->simple.addr_lo = lower_32_bits((size_t)(addr)); \
197 (fd)->simple.addr_hi = upper_32_bits((uint64_t)(addr)); \
199 #define DPAA2_SET_FD_LEN(fd, length) ((fd)->simple.len = length)
200 #define DPAA2_SET_FD_BPID(fd, bpid) ((fd)->simple.bpid_offset |= bpid)
201 #define DPAA2_SET_ONLY_FD_BPID(fd, bpid) \
202 ((fd)->simple.bpid_offset = bpid)
203 #define DPAA2_SET_FD_IVP(fd) (((fd)->simple.bpid_offset |= 0x00004000))
204 #define DPAA2_SET_FD_OFFSET(fd, offset) \
205 (((fd)->simple.bpid_offset |= (uint32_t)(offset) << 16))
206 #define DPAA2_SET_FD_INTERNAL_JD(fd, len) \
207 ((fd)->simple.frc = (0x80000000 | (len)))
208 #define DPAA2_GET_FD_FRC_PARSE_SUM(fd) \
209 ((uint16_t)(((fd)->simple.frc & 0xffff0000) >> 16))
210 #define DPAA2_SET_FD_FRC(fd, _frc) ((fd)->simple.frc = _frc)
211 #define DPAA2_RESET_FD_CTRL(fd) ((fd)->simple.ctrl = 0)
213 #define DPAA2_SET_FD_ASAL(fd, asal) ((fd)->simple.ctrl |= (asal << 16))
215 #define DPAA2_RESET_FD_FLC(fd) do { \
216 (fd)->simple.flc_lo = 0; \
217 (fd)->simple.flc_hi = 0; \
220 #define DPAA2_SET_FD_FLC(fd, addr) do { \
221 (fd)->simple.flc_lo = lower_32_bits((size_t)(addr)); \
222 (fd)->simple.flc_hi = upper_32_bits((uint64_t)(addr)); \
224 #define DPAA2_SET_FLE_INTERNAL_JD(fle, len) ((fle)->frc = (0x80000000 | (len)))
225 #define DPAA2_GET_FLE_ADDR(fle) \
226 (size_t)((((uint64_t)((fle)->addr_hi)) << 32) + (fle)->addr_lo)
227 #define DPAA2_SET_FLE_ADDR(fle, addr) do { \
228 (fle)->addr_lo = lower_32_bits((size_t)addr); \
229 (fle)->addr_hi = upper_32_bits((uint64_t)addr); \
231 #define DPAA2_GET_FLE_CTXT(fle) \
232 ((((uint64_t)((fle)->reserved[1])) << 32) + (fle)->reserved[0])
233 #define DPAA2_FLE_SAVE_CTXT(fle, addr) do { \
234 (fle)->reserved[0] = lower_32_bits((size_t)addr); \
235 (fle)->reserved[1] = upper_32_bits((uint64_t)addr); \
237 #define DPAA2_SET_FLE_OFFSET(fle, offset) \
238 ((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16)
239 #define DPAA2_SET_FLE_LEN(fle, len) ((fle)->length = len)
240 #define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (size_t)bpid)
241 #define DPAA2_GET_FLE_BPID(fle) ((fle)->fin_bpid_offset & 0x000000ff)
242 #define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |= 1 << 31)
243 #define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000))
244 #define DPAA2_SET_FLE_BMT(fle) (((fle)->fin_bpid_offset |= 0x00008000))
245 #define DPAA2_SET_FD_COMPOUND_FMT(fd) \
246 ((fd)->simple.bpid_offset |= (uint32_t)1 << 28)
247 #define DPAA2_GET_FD_ADDR(fd) \
248 (((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
250 #define DPAA2_GET_FD_LEN(fd) ((fd)->simple.len)
251 #define DPAA2_GET_FD_BPID(fd) (((fd)->simple.bpid_offset & 0x00003FFF))
252 #define DPAA2_GET_FD_IVP(fd) (((fd)->simple.bpid_offset & 0x00004000) >> 14)
253 #define DPAA2_GET_FD_OFFSET(fd) (((fd)->simple.bpid_offset & 0x0FFF0000) >> 16)
254 #define DPAA2_GET_FD_FRC(fd) ((fd)->simple.frc)
255 #define DPAA2_GET_FD_FLC(fd) \
256 (((uint64_t)((fd)->simple.flc_hi) << 32) + (fd)->simple.flc_lo)
257 #define DPAA2_GET_FD_ERR(fd) ((fd)->simple.bpid_offset & 0x000000FF)
258 #define DPAA2_GET_FLE_OFFSET(fle) (((fle)->fin_bpid_offset & 0x0FFF0000) >> 16)
259 #define DPAA2_SET_FLE_SG_EXT(fle) ((fle)->fin_bpid_offset |= (uint64_t)1 << 29)
260 #define DPAA2_IS_SET_FLE_SG_EXT(fle) \
261 (((fle)->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0)
263 #define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \
264 ((struct rte_mbuf *)((size_t)(buf) - (meta_data_size)))
266 #define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64)
268 #define DPAA2_FD_SET_FORMAT(fd, format) do { \
269 (fd)->simple.bpid_offset &= 0xCFFFFFFF; \
270 (fd)->simple.bpid_offset |= (uint32_t)format << 28; \
272 #define DPAA2_FD_GET_FORMAT(fd) (((fd)->simple.bpid_offset >> 28) & 0x3)
274 #define DPAA2_SG_SET_FINAL(sg, fin) do { \
275 (sg)->fin_bpid_offset &= 0x7FFFFFFF; \
276 (sg)->fin_bpid_offset |= (uint32_t)fin << 31; \
278 #define DPAA2_SG_IS_FINAL(sg) (!!((sg)->fin_bpid_offset >> 31))
279 /* Only Enqueue Error responses will be
280 * pushed on FQID_ERR of Enqueue FQ
282 #define DPAA2_EQ_RESP_ERR_FQ 0
283 /* All Enqueue responses will be pushed on address
284 * set with qbman_eq_desc_set_response
286 #define DPAA2_EQ_RESP_ALWAYS 1
288 /* Various structures representing contiguous memory maps */
289 struct dpaa2_memseg {
290 TAILQ_ENTRY(dpaa2_memseg) next;
296 TAILQ_HEAD(dpaa2_memseg_list, dpaa2_memseg);
297 extern struct dpaa2_memseg_list rte_dpaa2_memsegs;
299 #ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
300 extern uint8_t dpaa2_virt_mode;
301 static void *dpaa2_mem_ptov(phys_addr_t paddr) __attribute__((unused));
303 static void *dpaa2_mem_ptov(phys_addr_t paddr)
308 return (void *)(size_t)paddr;
310 va = (void *)dpaax_iova_table_get_va(paddr);
311 if (likely(va != NULL))
314 /* If not, Fallback to full memseg list searching */
315 va = rte_mem_iova2virt(paddr);
320 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) __attribute__((unused));
322 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
324 const struct rte_memseg *memseg;
329 memseg = rte_mem_virt2memseg((void *)(uintptr_t)vaddr, NULL);
331 return memseg->phys_addr + RTE_PTR_DIFF(vaddr, memseg->addr);
336 * When we are using Physical addresses as IO Virtual Addresses,
337 * Need to call conversion routines dpaa2_mem_vtop & dpaa2_mem_ptov
339 * These routines are called with help of below MACRO's
342 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_iova)
345 * macro to convert Virtual address to IOVA
347 #define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((size_t)(_vaddr))
350 * macro to convert IOVA to Virtual address
352 #define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((size_t)(_iova))
355 * macro to convert modify the memory containing IOVA to Virtual address
357 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \
358 {_mem = (_type)(dpaa2_mem_ptov((size_t)(_mem))); }
360 #else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
362 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_addr)
363 #define DPAA2_VADDR_TO_IOVA(_vaddr) (_vaddr)
364 #define DPAA2_IOVA_TO_VADDR(_iova) (_iova)
365 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type)
367 #endif /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
370 int check_swp_active_dqs(uint16_t dpio_index)
372 if (rte_global_active_dqs_list[dpio_index].global_active_dqs != NULL)
378 void clear_swp_active_dqs(uint16_t dpio_index)
380 rte_global_active_dqs_list[dpio_index].global_active_dqs = NULL;
384 struct qbman_result *get_swp_active_dqs(uint16_t dpio_index)
386 return rte_global_active_dqs_list[dpio_index].global_active_dqs;
390 void set_swp_active_dqs(uint16_t dpio_index, struct qbman_result *dqs)
392 rte_global_active_dqs_list[dpio_index].global_active_dqs = dqs;
394 struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void);
395 void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp);
396 int dpaa2_dpbp_supported(void);
398 struct dpaa2_dpci_dev *rte_dpaa2_alloc_dpci_dev(void);
399 void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci);