1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
8 #ifndef _DPAA2_HW_PVT_H_
9 #define _DPAA2_HW_PVT_H_
11 #include <rte_eventdev.h>
12 #include <dpaax_iova_table.h>
14 #include <mc/fsl_mc_sys.h>
15 #include <fsl_qbman_portal.h>
23 #define lower_32_bits(x) ((uint32_t)(x))
24 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
26 #define SVR_LS1080A 0x87030000
27 #define SVR_LS2080A 0x87010000
28 #define SVR_LS2088A 0x87090000
29 #define SVR_LX2160A 0x87360000
32 #define VLAN_TAG_SIZE 4 /** < Vlan Header Length */
35 #define MAX_TX_RING_SLOTS 8
36 /** <Maximum number of slots available in TX ring*/
38 #define DPAA2_DQRR_RING_SIZE 16
39 /** <Maximum number of slots available in RX ring*/
41 #define DPAA2_SWP_CENA_REGION 0
42 #define DPAA2_SWP_CINH_REGION 1
43 #define DPAA2_SWP_CENA_MEM_REGION 2
45 #define MC_PORTAL_INDEX 0
46 #define NUM_DPIO_REGIONS 2
47 #define NUM_DQS_PER_QUEUE 2
49 /* Maximum release/acquire from QBMAN */
50 #define DPAA2_MBUF_MAX_ACQ_REL 7
52 #define DPAA2_MEMPOOL_OPS_NAME "dpaa2"
55 #define DPAA2_MBUF_HW_ANNOTATION 64
56 #define DPAA2_FD_PTA_SIZE 0
58 #if (DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM
59 #error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM"
62 /* we will re-use the HEADROOM for annotation in RX */
63 #define DPAA2_HW_BUF_RESERVE 0
64 #define DPAA2_PACKET_LAYOUT_ALIGN 64 /*changing from 256 */
66 #define DPAA2_DPCI_MAX_QUEUES 2
68 struct dpaa2_dpio_dev {
69 TAILQ_ENTRY(dpaa2_dpio_dev) next;
70 /**< Pointer to Next device instance */
71 uint16_t index; /**< Index of a instance in the list */
72 rte_atomic16_t ref_count;
73 /**< How many thread contexts are sharing this.*/
74 struct fsl_mc_io *dpio; /** handle to DPIO portal object */
76 struct qbman_swp *sw_portal; /** SW portal object */
77 const struct qbman_result *dqrr[4];
78 /**< DQRR Entry for this SW portal */
79 void *mc_portal; /**< MC Portal for configuring this device */
80 uintptr_t qbman_portal_ce_paddr;
81 /**< Physical address of Cache Enabled Area */
82 uintptr_t ce_size; /**< Size of the CE region */
83 uintptr_t qbman_portal_ci_paddr;
84 /**< Physical address of Cache Inhibit Area */
85 uintptr_t ci_size; /**< Size of the CI region */
86 struct rte_intr_handle intr_handle; /* Interrupt related info */
87 int32_t epoll_fd; /**< File descriptor created for interrupt polling */
88 int32_t hw_id; /**< An unique ID of this DPIO device instance */
91 struct dpaa2_dpbp_dev {
92 TAILQ_ENTRY(dpaa2_dpbp_dev) next;
93 /**< Pointer to Next device instance */
94 struct fsl_mc_io dpbp; /** handle to DPBP portal object */
96 rte_atomic16_t in_use;
97 uint32_t dpbp_id; /*HW ID for DPBP object */
100 struct queue_storage_info_t {
101 struct qbman_result *dq_storage[NUM_DQS_PER_QUEUE];
102 struct qbman_result *active_dqs;
103 uint8_t active_dpio_id;
105 uint8_t last_num_pkts;
110 typedef void (dpaa2_queue_cb_dqrr_t)(struct qbman_swp *swp,
111 const struct qbman_fd *fd,
112 const struct qbman_result *dq,
113 struct dpaa2_queue *rxq,
114 struct rte_event *ev);
117 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
119 int32_t eventfd; /*!< Event Fd of this queue */
120 uint32_t fqid; /*!< Unique ID of this queue */
121 uint8_t tc_index; /*!< traffic class identifier */
122 uint16_t flow_id; /*!< To be used by DPAA2 frmework */
127 struct queue_storage_info_t *q_storage;
128 struct qbman_result *cscn;
131 dpaa2_queue_cb_dqrr_t *cb;
134 struct swp_active_dqs {
135 struct qbman_result *global_active_dqs;
136 uint64_t reserved[7];
139 #define NUM_MAX_SWP 64
141 extern struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
143 struct dpaa2_dpci_dev {
144 TAILQ_ENTRY(dpaa2_dpci_dev) next;
145 /**< Pointer to Next device instance */
146 struct fsl_mc_io dpci; /** handle to DPCI portal object */
148 rte_atomic16_t in_use;
149 uint32_t dpci_id; /*HW ID for DPCI object */
150 struct dpaa2_queue rx_queue[DPAA2_DPCI_MAX_QUEUES];
151 struct dpaa2_queue tx_queue[DPAA2_DPCI_MAX_QUEUES];
154 /*! Global MCP list */
155 extern void *(*rte_mcp_ptr_list);
157 /* Refer to Table 7-3 in SEC BG */
162 /* FMT must be 00, MSB is final bit */
163 uint32_t fin_bpid_offset;
165 uint32_t reserved[3]; /* Not used currently */
172 uint32_t fin_bpid_offset;
175 /* There are three types of frames: Single, Scatter Gather and Frame Lists */
176 enum qbman_fd_format {
181 /*Macros to define operations on FD*/
182 #define DPAA2_SET_FD_ADDR(fd, addr) do { \
183 (fd)->simple.addr_lo = lower_32_bits((size_t)(addr)); \
184 (fd)->simple.addr_hi = upper_32_bits((uint64_t)(addr)); \
186 #define DPAA2_SET_FD_LEN(fd, length) ((fd)->simple.len = length)
187 #define DPAA2_SET_FD_BPID(fd, bpid) ((fd)->simple.bpid_offset |= bpid)
188 #define DPAA2_SET_ONLY_FD_BPID(fd, bpid) \
189 ((fd)->simple.bpid_offset = bpid)
190 #define DPAA2_SET_FD_IVP(fd) (((fd)->simple.bpid_offset |= 0x00004000))
191 #define DPAA2_SET_FD_OFFSET(fd, offset) \
192 (((fd)->simple.bpid_offset |= (uint32_t)(offset) << 16))
193 #define DPAA2_SET_FD_INTERNAL_JD(fd, len) \
194 ((fd)->simple.frc = (0x80000000 | (len)))
195 #define DPAA2_GET_FD_FRC_PARSE_SUM(fd) \
196 ((uint16_t)(((fd)->simple.frc & 0xffff0000) >> 16))
197 #define DPAA2_SET_FD_FRC(fd, _frc) ((fd)->simple.frc = _frc)
198 #define DPAA2_RESET_FD_CTRL(fd) ((fd)->simple.ctrl = 0)
200 #define DPAA2_SET_FD_ASAL(fd, asal) ((fd)->simple.ctrl |= (asal << 16))
201 #define DPAA2_SET_FD_FLC(fd, addr) do { \
202 (fd)->simple.flc_lo = lower_32_bits((size_t)(addr)); \
203 (fd)->simple.flc_hi = upper_32_bits((uint64_t)(addr)); \
205 #define DPAA2_SET_FLE_INTERNAL_JD(fle, len) ((fle)->frc = (0x80000000 | (len)))
206 #define DPAA2_GET_FLE_ADDR(fle) \
207 (size_t)((((uint64_t)((fle)->addr_hi)) << 32) + (fle)->addr_lo)
208 #define DPAA2_SET_FLE_ADDR(fle, addr) do { \
209 (fle)->addr_lo = lower_32_bits((size_t)addr); \
210 (fle)->addr_hi = upper_32_bits((uint64_t)addr); \
212 #define DPAA2_GET_FLE_CTXT(fle) \
213 ((((uint64_t)((fle)->reserved[1])) << 32) + (fle)->reserved[0])
214 #define DPAA2_FLE_SAVE_CTXT(fle, addr) do { \
215 (fle)->reserved[0] = lower_32_bits((size_t)addr); \
216 (fle)->reserved[1] = upper_32_bits((uint64_t)addr); \
218 #define DPAA2_SET_FLE_OFFSET(fle, offset) \
219 ((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16)
220 #define DPAA2_SET_FLE_LEN(fle, len) ((fle)->length = len)
221 #define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (size_t)bpid)
222 #define DPAA2_GET_FLE_BPID(fle) ((fle)->fin_bpid_offset & 0x000000ff)
223 #define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |= 1 << 31)
224 #define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000))
225 #define DPAA2_SET_FLE_BMT(fle) (((fle)->fin_bpid_offset |= 0x00008000))
226 #define DPAA2_SET_FD_COMPOUND_FMT(fd) \
227 ((fd)->simple.bpid_offset |= (uint32_t)1 << 28)
228 #define DPAA2_GET_FD_ADDR(fd) \
229 (((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
231 #define DPAA2_GET_FD_LEN(fd) ((fd)->simple.len)
232 #define DPAA2_GET_FD_BPID(fd) (((fd)->simple.bpid_offset & 0x00003FFF))
233 #define DPAA2_GET_FD_IVP(fd) (((fd)->simple.bpid_offset & 0x00004000) >> 14)
234 #define DPAA2_GET_FD_OFFSET(fd) (((fd)->simple.bpid_offset & 0x0FFF0000) >> 16)
235 #define DPAA2_GET_FD_FRC(fd) ((fd)->simple.frc)
236 #define DPAA2_GET_FD_FLC(fd) \
237 (((uint64_t)((fd)->simple.flc_hi) << 32) + (fd)->simple.flc_lo)
238 #define DPAA2_GET_FD_ERR(fd) ((fd)->simple.bpid_offset & 0x000000FF)
239 #define DPAA2_GET_FLE_OFFSET(fle) (((fle)->fin_bpid_offset & 0x0FFF0000) >> 16)
240 #define DPAA2_SET_FLE_SG_EXT(fle) ((fle)->fin_bpid_offset |= (uint64_t)1 << 29)
241 #define DPAA2_IS_SET_FLE_SG_EXT(fle) \
242 (((fle)->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0)
244 #define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \
245 ((struct rte_mbuf *)((size_t)(buf) - (meta_data_size)))
247 #define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64)
249 #define DPAA2_FD_SET_FORMAT(fd, format) do { \
250 (fd)->simple.bpid_offset &= 0xCFFFFFFF; \
251 (fd)->simple.bpid_offset |= (uint32_t)format << 28; \
253 #define DPAA2_FD_GET_FORMAT(fd) (((fd)->simple.bpid_offset >> 28) & 0x3)
255 #define DPAA2_SG_SET_FINAL(sg, fin) do { \
256 (sg)->fin_bpid_offset &= 0x7FFFFFFF; \
257 (sg)->fin_bpid_offset |= (uint32_t)fin << 31; \
259 #define DPAA2_SG_IS_FINAL(sg) (!!((sg)->fin_bpid_offset >> 31))
260 /* Only Enqueue Error responses will be
261 * pushed on FQID_ERR of Enqueue FQ
263 #define DPAA2_EQ_RESP_ERR_FQ 0
264 /* All Enqueue responses will be pushed on address
265 * set with qbman_eq_desc_set_response
267 #define DPAA2_EQ_RESP_ALWAYS 1
269 /* Various structures representing contiguous memory maps */
270 struct dpaa2_memseg {
271 TAILQ_ENTRY(dpaa2_memseg) next;
277 TAILQ_HEAD(dpaa2_memseg_list, dpaa2_memseg);
278 extern struct dpaa2_memseg_list rte_dpaa2_memsegs;
280 #ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
281 extern uint8_t dpaa2_virt_mode;
282 static void *dpaa2_mem_ptov(phys_addr_t paddr) __attribute__((unused));
284 static void *dpaa2_mem_ptov(phys_addr_t paddr)
289 return (void *)(size_t)paddr;
291 va = (void *)dpaax_iova_table_get_va(paddr);
292 if (likely(va != NULL))
295 /* If not, Fallback to full memseg list searching */
296 va = rte_mem_iova2virt(paddr);
301 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) __attribute__((unused));
303 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
305 const struct rte_memseg *memseg;
310 memseg = rte_mem_virt2memseg((void *)(uintptr_t)vaddr, NULL);
312 return memseg->phys_addr + RTE_PTR_DIFF(vaddr, memseg->addr);
317 * When we are using Physical addresses as IO Virtual Addresses,
318 * Need to call conversion routines dpaa2_mem_vtop & dpaa2_mem_ptov
320 * These routines are called with help of below MACRO's
323 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_iova)
326 * macro to convert Virtual address to IOVA
328 #define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((size_t)(_vaddr))
331 * macro to convert IOVA to Virtual address
333 #define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((size_t)(_iova))
336 * macro to convert modify the memory containing IOVA to Virtual address
338 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \
339 {_mem = (_type)(dpaa2_mem_ptov((size_t)(_mem))); }
341 #else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
343 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_addr)
344 #define DPAA2_VADDR_TO_IOVA(_vaddr) (_vaddr)
345 #define DPAA2_IOVA_TO_VADDR(_iova) (_iova)
346 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type)
348 #endif /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
351 int check_swp_active_dqs(uint16_t dpio_index)
353 if (rte_global_active_dqs_list[dpio_index].global_active_dqs != NULL)
359 void clear_swp_active_dqs(uint16_t dpio_index)
361 rte_global_active_dqs_list[dpio_index].global_active_dqs = NULL;
365 struct qbman_result *get_swp_active_dqs(uint16_t dpio_index)
367 return rte_global_active_dqs_list[dpio_index].global_active_dqs;
371 void set_swp_active_dqs(uint16_t dpio_index, struct qbman_result *dqs)
373 rte_global_active_dqs_list[dpio_index].global_active_dqs = dqs;
375 struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void);
376 void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp);
377 int dpaa2_dpbp_supported(void);
379 struct dpaa2_dpci_dev *rte_dpaa2_alloc_dpci_dev(void);
380 void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci);