4 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Freescale Semiconductor, Inc nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _DPAA2_HW_PVT_H_
35 #define _DPAA2_HW_PVT_H_
37 #include <rte_eventdev.h>
39 #include <mc/fsl_mc_sys.h>
40 #include <fsl_qbman_portal.h>
48 #define lower_32_bits(x) ((uint32_t)(x))
49 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
51 #define SVR_LS1080A 0x87030000
52 #define SVR_LS2080A 0x87010000
53 #define SVR_LS2088A 0x87090000
56 #define ETH_VLAN_HLEN 4 /** < Vlan Header Length */
59 #define MAX_TX_RING_SLOTS 8
60 /** <Maximum number of slots available in TX ring*/
62 #define DPAA2_DQRR_RING_SIZE 16
63 /** <Maximum number of slots available in RX ring*/
65 #define MC_PORTAL_INDEX 0
66 #define NUM_DPIO_REGIONS 2
67 #define NUM_DQS_PER_QUEUE 2
69 /* Maximum release/acquire from QBMAN */
70 #define DPAA2_MBUF_MAX_ACQ_REL 7
73 #define DPAA2_MBUF_HW_ANNOTATION 64
74 #define DPAA2_FD_PTA_SIZE 0
76 #if (DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM
77 #error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM"
80 /* we will re-use the HEADROOM for annotation in RX */
81 #define DPAA2_HW_BUF_RESERVE 0
82 #define DPAA2_PACKET_LAYOUT_ALIGN 64 /*changing from 256 */
84 #define DPAA2_DPCI_MAX_QUEUES 2
86 struct dpaa2_dpio_dev {
87 TAILQ_ENTRY(dpaa2_dpio_dev) next;
88 /**< Pointer to Next device instance */
89 uint16_t index; /**< Index of a instance in the list */
90 rte_atomic16_t ref_count;
91 /**< How many thread contexts are sharing this.*/
92 struct fsl_mc_io *dpio; /** handle to DPIO portal object */
94 struct qbman_swp *sw_portal; /** SW portal object */
95 const struct qbman_result *dqrr[4];
96 /**< DQRR Entry for this SW portal */
97 void *mc_portal; /**< MC Portal for configuring this device */
98 uintptr_t qbman_portal_ce_paddr;
99 /**< Physical address of Cache Enabled Area */
100 uintptr_t ce_size; /**< Size of the CE region */
101 uintptr_t qbman_portal_ci_paddr;
102 /**< Physical address of Cache Inhibit Area */
103 uintptr_t ci_size; /**< Size of the CI region */
104 struct rte_intr_handle intr_handle; /* Interrupt related info */
105 int32_t epoll_fd; /**< File descriptor created for interrupt polling */
106 int32_t hw_id; /**< An unique ID of this DPIO device instance */
111 struct dpaa2_dpbp_dev {
112 TAILQ_ENTRY(dpaa2_dpbp_dev) next;
113 /**< Pointer to Next device instance */
114 struct fsl_mc_io dpbp; /** handle to DPBP portal object */
116 rte_atomic16_t in_use;
117 uint32_t dpbp_id; /*HW ID for DPBP object */
120 struct queue_storage_info_t {
121 struct qbman_result *dq_storage[NUM_DQS_PER_QUEUE];
122 struct qbman_result *active_dqs;
127 typedef void (dpaa2_queue_cb_dqrr_t)(struct qbman_swp *swp,
128 const struct qbman_fd *fd,
129 const struct qbman_result *dq,
130 struct rte_event *ev);
133 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
135 int32_t eventfd; /*!< Event Fd of this queue */
136 uint32_t fqid; /*!< Unique ID of this queue */
137 uint8_t tc_index; /*!< traffic class identifier */
138 uint16_t flow_id; /*!< To be used by DPAA2 frmework */
143 struct queue_storage_info_t *q_storage;
144 struct qbman_result *cscn;
146 dpaa2_queue_cb_dqrr_t *cb;
149 struct swp_active_dqs {
150 struct qbman_result *global_active_dqs;
151 uint64_t reserved[7];
154 #define NUM_MAX_SWP 64
156 extern struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
158 struct dpaa2_dpci_dev {
159 TAILQ_ENTRY(dpaa2_dpci_dev) next;
160 /**< Pointer to Next device instance */
161 struct fsl_mc_io dpci; /** handle to DPCI portal object */
163 rte_atomic16_t in_use;
164 uint32_t dpci_id; /*HW ID for DPCI object */
165 struct dpaa2_queue queue[DPAA2_DPCI_MAX_QUEUES];
168 /*! Global MCP list */
169 extern void *(*rte_mcp_ptr_list);
171 /* Refer to Table 7-3 in SEC BG */
176 /* FMT must be 00, MSB is final bit */
177 uint32_t fin_bpid_offset;
179 uint32_t reserved[3]; /* Not used currently */
186 uint32_t fin_bpid_offset;
189 /* There are three types of frames: Single, Scatter Gather and Frame Lists */
190 enum qbman_fd_format {
195 /*Macros to define operations on FD*/
196 #define DPAA2_SET_FD_ADDR(fd, addr) do { \
197 fd->simple.addr_lo = lower_32_bits((uint64_t)(addr)); \
198 fd->simple.addr_hi = upper_32_bits((uint64_t)(addr)); \
200 #define DPAA2_SET_FD_LEN(fd, length) (fd)->simple.len = length
201 #define DPAA2_SET_FD_BPID(fd, bpid) ((fd)->simple.bpid_offset |= bpid)
202 #define DPAA2_SET_FD_IVP(fd) ((fd->simple.bpid_offset |= 0x00004000))
203 #define DPAA2_SET_FD_OFFSET(fd, offset) \
204 ((fd->simple.bpid_offset |= (uint32_t)(offset) << 16))
205 #define DPAA2_SET_FD_INTERNAL_JD(fd, len) fd->simple.frc = (0x80000000 | (len))
206 #define DPAA2_SET_FD_FRC(fd, frc) fd->simple.frc = frc
207 #define DPAA2_RESET_FD_CTRL(fd) (fd)->simple.ctrl = 0
209 #define DPAA2_SET_FD_ASAL(fd, asal) ((fd)->simple.ctrl |= (asal << 16))
210 #define DPAA2_SET_FD_FLC(fd, addr) do { \
211 fd->simple.flc_lo = lower_32_bits((uint64_t)(addr)); \
212 fd->simple.flc_hi = upper_32_bits((uint64_t)(addr)); \
214 #define DPAA2_SET_FLE_INTERNAL_JD(fle, len) (fle->frc = (0x80000000 | (len)))
215 #define DPAA2_GET_FLE_ADDR(fle) \
216 (uint64_t)((((uint64_t)(fle->addr_hi)) << 32) + fle->addr_lo)
217 #define DPAA2_SET_FLE_ADDR(fle, addr) do { \
218 fle->addr_lo = lower_32_bits((uint64_t)addr); \
219 fle->addr_hi = upper_32_bits((uint64_t)addr); \
221 #define DPAA2_GET_FLE_CTXT(fle) \
222 (uint64_t)((((uint64_t)((fle)->reserved[1])) << 32) + \
224 #define DPAA2_FLE_SAVE_CTXT(fle, addr) do { \
225 fle->reserved[0] = lower_32_bits((uint64_t)addr); \
226 fle->reserved[1] = upper_32_bits((uint64_t)addr); \
228 #define DPAA2_SET_FLE_OFFSET(fle, offset) \
229 ((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16)
230 #define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (uint64_t)bpid)
231 #define DPAA2_GET_FLE_BPID(fle) ((fle)->fin_bpid_offset & 0x000000ff)
232 #define DPAA2_SET_FLE_FIN(fle) (fle->fin_bpid_offset |= (uint64_t)1 << 31)
233 #define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000))
234 #define DPAA2_SET_FD_COMPOUND_FMT(fd) \
235 (fd->simple.bpid_offset |= (uint32_t)1 << 28)
236 #define DPAA2_GET_FD_ADDR(fd) \
237 ((uint64_t)((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
239 #define DPAA2_GET_FD_LEN(fd) ((fd)->simple.len)
240 #define DPAA2_GET_FD_BPID(fd) (((fd)->simple.bpid_offset & 0x00003FFF))
241 #define DPAA2_GET_FD_IVP(fd) ((fd->simple.bpid_offset & 0x00004000) >> 14)
242 #define DPAA2_GET_FD_OFFSET(fd) (((fd)->simple.bpid_offset & 0x0FFF0000) >> 16)
243 #define DPAA2_GET_FLE_OFFSET(fle) (((fle)->fin_bpid_offset & 0x0FFF0000) >> 16)
244 #define DPAA2_SET_FLE_SG_EXT(fle) (fle->fin_bpid_offset |= (uint64_t)1 << 29)
245 #define DPAA2_IS_SET_FLE_SG_EXT(fle) \
246 ((fle->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0)
248 #define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \
249 ((struct rte_mbuf *)((uint64_t)(buf) - (meta_data_size)))
251 #define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64)
253 #define DPAA2_FD_SET_FORMAT(fd, format) do { \
254 (fd)->simple.bpid_offset &= 0xCFFFFFFF; \
255 (fd)->simple.bpid_offset |= (uint32_t)format << 28; \
257 #define DPAA2_FD_GET_FORMAT(fd) (((fd)->simple.bpid_offset >> 28) & 0x3)
259 #define DPAA2_SG_SET_FINAL(sg, fin) do { \
260 (sg)->fin_bpid_offset &= 0x7FFFFFFF; \
261 (sg)->fin_bpid_offset |= (uint32_t)fin << 31; \
263 #define DPAA2_SG_IS_FINAL(sg) (!!((sg)->fin_bpid_offset >> 31))
264 /* Only Enqueue Error responses will be
265 * pushed on FQID_ERR of Enqueue FQ
267 #define DPAA2_EQ_RESP_ERR_FQ 0
268 /* All Enqueue responses will be pushed on address
269 * set with qbman_eq_desc_set_response
271 #define DPAA2_EQ_RESP_ALWAYS 1
273 #ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
274 static void *dpaa2_mem_ptov(phys_addr_t paddr) __attribute__((unused));
275 /* todo - this is costly, need to write a fast coversion routine */
276 static void *dpaa2_mem_ptov(phys_addr_t paddr)
278 const struct rte_memseg *memseg = rte_eal_get_physmem_layout();
281 for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
282 if (paddr >= memseg[i].phys_addr &&
283 (char *)paddr < (char *)memseg[i].phys_addr + memseg[i].len)
284 return (void *)(memseg[i].addr_64
285 + (paddr - memseg[i].phys_addr));
290 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) __attribute__((unused));
291 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
293 const struct rte_memseg *memseg = rte_eal_get_physmem_layout();
296 for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
297 if (vaddr >= memseg[i].addr_64 &&
298 vaddr < memseg[i].addr_64 + memseg[i].len)
299 return memseg[i].phys_addr
300 + (vaddr - memseg[i].addr_64);
302 return (phys_addr_t)(NULL);
306 * When we are using Physical addresses as IO Virtual Addresses,
307 * Need to call conversion routines dpaa2_mem_vtop & dpaa2_mem_ptov
309 * These routines are called with help of below MACRO's
312 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_physaddr)
313 #define DPAA2_OP_VADDR_TO_IOVA(op) (op->phys_addr)
316 * macro to convert Virtual address to IOVA
318 #define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((uint64_t)(_vaddr))
321 * macro to convert IOVA to Virtual address
323 #define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((phys_addr_t)(_iova))
326 * macro to convert modify the memory containing IOVA to Virtual address
328 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \
329 {_mem = (_type)(dpaa2_mem_ptov((phys_addr_t)(_mem))); }
331 #else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
333 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_addr)
334 #define DPAA2_OP_VADDR_TO_IOVA(op) (op)
335 #define DPAA2_VADDR_TO_IOVA(_vaddr) (_vaddr)
336 #define DPAA2_IOVA_TO_VADDR(_iova) (_iova)
337 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type)
339 #endif /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
342 int check_swp_active_dqs(uint16_t dpio_index)
344 if (rte_global_active_dqs_list[dpio_index].global_active_dqs != NULL)
350 void clear_swp_active_dqs(uint16_t dpio_index)
352 rte_global_active_dqs_list[dpio_index].global_active_dqs = NULL;
356 struct qbman_result *get_swp_active_dqs(uint16_t dpio_index)
358 return rte_global_active_dqs_list[dpio_index].global_active_dqs;
362 void set_swp_active_dqs(uint16_t dpio_index, struct qbman_result *dqs)
364 rte_global_active_dqs_list[dpio_index].global_active_dqs = dqs;
366 struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void);
367 void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp);
369 struct dpaa2_dpci_dev *rte_dpaa2_alloc_dpci_dev(void);
370 void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci);