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34 #ifndef _DPAA2_HW_PVT_H_
35 #define _DPAA2_HW_PVT_H_
37 #include <mc/fsl_mc_sys.h>
38 #include <fsl_qbman_portal.h>
41 #define MC_PORTAL_INDEX 0
42 #define NUM_DPIO_REGIONS 2
44 struct dpaa2_dpio_dev {
45 TAILQ_ENTRY(dpaa2_dpio_dev) next;
46 /**< Pointer to Next device instance */
47 uint16_t index; /**< Index of a instance in the list */
48 rte_atomic16_t ref_count;
49 /**< How many thread contexts are sharing this.*/
50 struct fsl_mc_io *dpio; /** handle to DPIO portal object */
52 struct qbman_swp *sw_portal; /** SW portal object */
53 const struct qbman_result *dqrr[4];
54 /**< DQRR Entry for this SW portal */
55 void *mc_portal; /**< MC Portal for configuring this device */
56 uintptr_t qbman_portal_ce_paddr;
57 /**< Physical address of Cache Enabled Area */
58 uintptr_t ce_size; /**< Size of the CE region */
59 uintptr_t qbman_portal_ci_paddr;
60 /**< Physical address of Cache Inhibit Area */
61 uintptr_t ci_size; /**< Size of the CI region */
62 int32_t vfio_fd; /**< File descriptor received via VFIO */
63 int32_t hw_id; /**< An unique ID of this DPIO device instance */
66 /*! Global MCP list */
67 extern void *(*rte_mcp_ptr_list);