1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2019 NXP
8 #ifndef _DPAA2_HW_PVT_H_
9 #define _DPAA2_HW_PVT_H_
11 #include <rte_eventdev.h>
12 #include <dpaax_iova_table.h>
14 #include <mc/fsl_mc_sys.h>
15 #include <fsl_qbman_portal.h>
23 #define lower_32_bits(x) ((uint32_t)(x))
24 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
27 #define VLAN_TAG_SIZE 4 /** < Vlan Header Length */
30 /* Maximum number of slots available in TX ring */
31 #define MAX_TX_RING_SLOTS 32
32 #define MAX_EQ_RESP_ENTRIES (MAX_TX_RING_SLOTS + 1)
34 /* Maximum number of slots available in RX ring */
35 #define DPAA2_EQCR_RING_SIZE 8
36 /* Maximum number of slots available in RX ring on LX2 */
37 #define DPAA2_LX2_EQCR_RING_SIZE 32
39 /* Maximum number of slots available in RX ring */
40 #define DPAA2_DQRR_RING_SIZE 16
41 /* Maximum number of slots available in RX ring on LX2 */
42 #define DPAA2_LX2_DQRR_RING_SIZE 32
44 /* EQCR shift to get EQCR size (2 >> 3) = 8 for LS2/LS2 */
45 #define DPAA2_EQCR_SHIFT 3
46 /* EQCR shift to get EQCR size for LX2 (2 >> 5) = 32 for LX2 */
47 #define DPAA2_LX2_EQCR_SHIFT 5
49 /* Flag to determine an ordered queue mbuf */
50 #define DPAA2_ENQUEUE_FLAG_ORP (1ULL << 30)
51 /* ORP ID shift and mask */
52 #define DPAA2_EQCR_OPRID_SHIFT 16
53 #define DPAA2_EQCR_OPRID_MASK 0x3FFF0000
54 /* Sequence number shift and mask */
55 #define DPAA2_EQCR_SEQNUM_SHIFT 0
56 #define DPAA2_EQCR_SEQNUM_MASK 0x0000FFFF
58 #define DPAA2_SWP_CENA_REGION 0
59 #define DPAA2_SWP_CINH_REGION 1
60 #define DPAA2_SWP_CENA_MEM_REGION 2
62 #define DPAA2_MAX_TX_RETRY_COUNT 10000
64 #define MC_PORTAL_INDEX 0
65 #define NUM_DPIO_REGIONS 2
66 #define NUM_DQS_PER_QUEUE 2
68 /* Maximum release/acquire from QBMAN */
69 #define DPAA2_MBUF_MAX_ACQ_REL 7
71 #define DPAA2_MEMPOOL_OPS_NAME "dpaa2"
74 #define DPAA2_MBUF_HW_ANNOTATION 64
75 #define DPAA2_FD_PTA_SIZE 0
77 /* we will re-use the HEADROOM for annotation in RX */
78 #define DPAA2_HW_BUF_RESERVE 0
79 #define DPAA2_PACKET_LAYOUT_ALIGN 64 /*changing from 256 */
81 #define DPAA2_DPCI_MAX_QUEUES 2
85 struct eqresp_metadata {
86 struct dpaa2_queue *dpaa2_q;
87 struct rte_mempool *mp;
90 struct dpaa2_dpio_dev {
91 TAILQ_ENTRY(dpaa2_dpio_dev) next;
92 /**< Pointer to Next device instance */
93 uint16_t index; /**< Index of a instance in the list */
94 rte_atomic16_t ref_count;
95 /**< How many thread contexts are sharing this.*/
98 struct qbman_result *eqresp;
99 struct eqresp_metadata *eqresp_meta;
100 struct fsl_mc_io *dpio; /** handle to DPIO portal object */
102 struct qbman_swp *sw_portal; /** SW portal object */
103 const struct qbman_result *dqrr[4];
104 /**< DQRR Entry for this SW portal */
105 void *mc_portal; /**< MC Portal for configuring this device */
106 uintptr_t qbman_portal_ce_paddr;
107 /**< Physical address of Cache Enabled Area */
108 uintptr_t ce_size; /**< Size of the CE region */
109 uintptr_t qbman_portal_ci_paddr;
110 /**< Physical address of Cache Inhibit Area */
111 uintptr_t ci_size; /**< Size of the CI region */
112 struct rte_intr_handle intr_handle; /* Interrupt related info */
113 int32_t epoll_fd; /**< File descriptor created for interrupt polling */
114 int32_t hw_id; /**< An unique ID of this DPIO device instance */
117 struct dpaa2_dpbp_dev {
118 TAILQ_ENTRY(dpaa2_dpbp_dev) next;
119 /**< Pointer to Next device instance */
120 struct fsl_mc_io dpbp; /** handle to DPBP portal object */
122 rte_atomic16_t in_use;
123 uint32_t dpbp_id; /*HW ID for DPBP object */
126 struct queue_storage_info_t {
127 struct qbman_result *dq_storage[NUM_DQS_PER_QUEUE];
128 struct qbman_result *active_dqs;
129 uint8_t active_dpio_id;
131 uint8_t last_num_pkts;
136 typedef void (dpaa2_queue_cb_dqrr_t)(struct qbman_swp *swp,
137 const struct qbman_fd *fd,
138 const struct qbman_result *dq,
139 struct dpaa2_queue *rxq,
140 struct rte_event *ev);
142 typedef void (dpaa2_queue_cb_eqresp_free_t)(uint16_t eqresp_ci);
145 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
147 struct rte_eth_dev_data *eth_data;
148 struct rte_cryptodev_data *crypto_data;
150 uint32_t fqid; /*!< Unique ID of this queue */
151 uint16_t flow_id; /*!< To be used by DPAA2 frmework */
152 uint8_t tc_index; /*!< traffic class identifier */
153 uint8_t cgid; /*! < Congestion Group id for this queue */
158 struct queue_storage_info_t *q_storage;
159 struct qbman_result *cscn;
162 int32_t eventfd; /*!< Event Fd of this queue */
163 dpaa2_queue_cb_dqrr_t *cb;
164 dpaa2_queue_cb_eqresp_free_t *cb_eqresp_free;
165 struct dpaa2_bp_info *bp_array;
166 /*to store tx_conf_queue corresponding to tx_queue*/
167 struct dpaa2_queue *tx_conf_queue;
170 struct swp_active_dqs {
171 struct qbman_result *global_active_dqs;
172 uint64_t reserved[7];
175 #define NUM_MAX_SWP 64
177 extern struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
179 struct dpaa2_dpci_dev {
180 TAILQ_ENTRY(dpaa2_dpci_dev) next;
181 /**< Pointer to Next device instance */
182 struct fsl_mc_io dpci; /** handle to DPCI portal object */
184 rte_atomic16_t in_use;
185 uint32_t dpci_id; /*HW ID for DPCI object */
186 struct dpaa2_queue rx_queue[DPAA2_DPCI_MAX_QUEUES];
187 struct dpaa2_queue tx_queue[DPAA2_DPCI_MAX_QUEUES];
190 struct dpaa2_dpcon_dev {
191 TAILQ_ENTRY(dpaa2_dpcon_dev) next;
192 struct fsl_mc_io dpcon;
194 rte_atomic16_t in_use;
196 uint16_t qbman_ch_id;
197 uint8_t num_priorities;
198 uint8_t channel_index;
201 /*! Global MCP list */
202 extern void *(*rte_mcp_ptr_list);
204 /* Refer to Table 7-3 in SEC BG */
209 /* FMT must be 00, MSB is final bit */
210 uint32_t fin_bpid_offset;
212 uint32_t reserved[3]; /* Not used currently */
219 uint32_t fin_bpid_offset;
222 /* There are three types of frames: Single, Scatter Gather and Frame Lists */
223 enum qbman_fd_format {
228 /*Macros to define operations on FD*/
229 #define DPAA2_SET_FD_ADDR(fd, addr) do { \
230 (fd)->simple.addr_lo = lower_32_bits((size_t)(addr)); \
231 (fd)->simple.addr_hi = upper_32_bits((uint64_t)(addr)); \
233 #define DPAA2_SET_FD_LEN(fd, length) ((fd)->simple.len = length)
234 #define DPAA2_SET_FD_BPID(fd, bpid) ((fd)->simple.bpid_offset |= bpid)
235 #define DPAA2_SET_ONLY_FD_BPID(fd, bpid) \
236 ((fd)->simple.bpid_offset = bpid)
237 #define DPAA2_SET_FD_IVP(fd) (((fd)->simple.bpid_offset |= 0x00004000))
238 #define DPAA2_SET_FD_OFFSET(fd, offset) \
239 (((fd)->simple.bpid_offset |= (uint32_t)(offset) << 16))
240 #define DPAA2_SET_FD_INTERNAL_JD(fd, len) \
241 ((fd)->simple.frc = (0x80000000 | (len)))
242 #define DPAA2_GET_FD_FRC_PARSE_SUM(fd) \
243 ((uint16_t)(((fd)->simple.frc & 0xffff0000) >> 16))
244 #define DPAA2_RESET_FD_FRC(fd) ((fd)->simple.frc = 0)
245 #define DPAA2_SET_FD_FRC(fd, _frc) ((fd)->simple.frc = _frc)
246 #define DPAA2_RESET_FD_CTRL(fd) ((fd)->simple.ctrl = 0)
248 #define DPAA2_SET_FD_ASAL(fd, asal) ((fd)->simple.ctrl |= (asal << 16))
250 #define DPAA2_RESET_FD_FLC(fd) do { \
251 (fd)->simple.flc_lo = 0; \
252 (fd)->simple.flc_hi = 0; \
255 #define DPAA2_SET_FD_FLC(fd, addr) do { \
256 (fd)->simple.flc_lo = lower_32_bits((size_t)(addr)); \
257 (fd)->simple.flc_hi = upper_32_bits((uint64_t)(addr)); \
259 #define DPAA2_SET_FLE_INTERNAL_JD(fle, len) ((fle)->frc = (0x80000000 | (len)))
260 #define DPAA2_GET_FLE_ADDR(fle) \
261 (size_t)((((uint64_t)((fle)->addr_hi)) << 32) + (fle)->addr_lo)
262 #define DPAA2_SET_FLE_ADDR(fle, addr) do { \
263 (fle)->addr_lo = lower_32_bits((size_t)addr); \
264 (fle)->addr_hi = upper_32_bits((uint64_t)addr); \
266 #define DPAA2_GET_FLE_CTXT(fle) \
267 ((((uint64_t)((fle)->reserved[1])) << 32) + (fle)->reserved[0])
268 #define DPAA2_FLE_SAVE_CTXT(fle, addr) do { \
269 (fle)->reserved[0] = lower_32_bits((size_t)addr); \
270 (fle)->reserved[1] = upper_32_bits((uint64_t)addr); \
272 #define DPAA2_SET_FLE_OFFSET(fle, offset) \
273 ((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16)
274 #define DPAA2_SET_FLE_LEN(fle, len) ((fle)->length = len)
275 #define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (size_t)bpid)
276 #define DPAA2_GET_FLE_BPID(fle) ((fle)->fin_bpid_offset & 0x000000ff)
277 #define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |= 1 << 31)
278 #define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000))
279 #define DPAA2_SET_FLE_BMT(fle) (((fle)->fin_bpid_offset |= 0x00008000))
280 #define DPAA2_SET_FD_COMPOUND_FMT(fd) \
281 ((fd)->simple.bpid_offset |= (uint32_t)1 << 28)
282 #define DPAA2_GET_FD_ADDR(fd) \
283 (((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
285 #define DPAA2_GET_FD_LEN(fd) ((fd)->simple.len)
286 #define DPAA2_GET_FD_BPID(fd) (((fd)->simple.bpid_offset & 0x00003FFF))
287 #define DPAA2_GET_FD_IVP(fd) (((fd)->simple.bpid_offset & 0x00004000) >> 14)
288 #define DPAA2_GET_FD_OFFSET(fd) (((fd)->simple.bpid_offset & 0x0FFF0000) >> 16)
289 #define DPAA2_GET_FD_FRC(fd) ((fd)->simple.frc)
290 #define DPAA2_GET_FD_FLC(fd) \
291 (((uint64_t)((fd)->simple.flc_hi) << 32) + (fd)->simple.flc_lo)
292 #define DPAA2_GET_FD_ERR(fd) ((fd)->simple.bpid_offset & 0x000000FF)
293 #define DPAA2_GET_FLE_OFFSET(fle) (((fle)->fin_bpid_offset & 0x0FFF0000) >> 16)
294 #define DPAA2_SET_FLE_SG_EXT(fle) ((fle)->fin_bpid_offset |= (uint64_t)1 << 29)
295 #define DPAA2_IS_SET_FLE_SG_EXT(fle) \
296 (((fle)->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0)
298 #define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \
299 ((struct rte_mbuf *)((size_t)(buf) - (meta_data_size)))
301 #define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64)
303 #define DPAA2_FD_SET_FORMAT(fd, format) do { \
304 (fd)->simple.bpid_offset &= 0xCFFFFFFF; \
305 (fd)->simple.bpid_offset |= (uint32_t)format << 28; \
307 #define DPAA2_FD_GET_FORMAT(fd) (((fd)->simple.bpid_offset >> 28) & 0x3)
309 #define DPAA2_SG_SET_FINAL(sg, fin) do { \
310 (sg)->fin_bpid_offset &= 0x7FFFFFFF; \
311 (sg)->fin_bpid_offset |= (uint32_t)fin << 31; \
313 #define DPAA2_SG_IS_FINAL(sg) (!!((sg)->fin_bpid_offset >> 31))
314 /* Only Enqueue Error responses will be
315 * pushed on FQID_ERR of Enqueue FQ
317 #define DPAA2_EQ_RESP_ERR_FQ 0
318 /* All Enqueue responses will be pushed on address
319 * set with qbman_eq_desc_set_response
321 #define DPAA2_EQ_RESP_ALWAYS 1
323 /* Various structures representing contiguous memory maps */
324 struct dpaa2_memseg {
325 TAILQ_ENTRY(dpaa2_memseg) next;
331 TAILQ_HEAD(dpaa2_memseg_list, dpaa2_memseg);
332 extern struct dpaa2_memseg_list rte_dpaa2_memsegs;
334 #ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
335 extern uint8_t dpaa2_virt_mode;
336 static void *dpaa2_mem_ptov(phys_addr_t paddr) __attribute__((unused));
338 static void *dpaa2_mem_ptov(phys_addr_t paddr)
343 return (void *)(size_t)paddr;
345 va = (void *)dpaax_iova_table_get_va(paddr);
346 if (likely(va != NULL))
349 /* If not, Fallback to full memseg list searching */
350 va = rte_mem_iova2virt(paddr);
355 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) __attribute__((unused));
357 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
359 const struct rte_memseg *memseg;
364 memseg = rte_mem_virt2memseg((void *)(uintptr_t)vaddr, NULL);
366 return memseg->phys_addr + RTE_PTR_DIFF(vaddr, memseg->addr);
371 * When we are using Physical addresses as IO Virtual Addresses,
372 * Need to call conversion routines dpaa2_mem_vtop & dpaa2_mem_ptov
374 * These routines are called with help of below MACRO's
377 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_iova)
380 * macro to convert Virtual address to IOVA
382 #define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((size_t)(_vaddr))
385 * macro to convert IOVA to Virtual address
387 #define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((size_t)(_iova))
390 * macro to convert modify the memory containing IOVA to Virtual address
392 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \
393 {_mem = (_type)(dpaa2_mem_ptov((size_t)(_mem))); }
395 #else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
397 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_addr)
398 #define DPAA2_VADDR_TO_IOVA(_vaddr) (_vaddr)
399 #define DPAA2_IOVA_TO_VADDR(_iova) (_iova)
400 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type)
402 #endif /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
405 int check_swp_active_dqs(uint16_t dpio_index)
407 if (rte_global_active_dqs_list[dpio_index].global_active_dqs != NULL)
413 void clear_swp_active_dqs(uint16_t dpio_index)
415 rte_global_active_dqs_list[dpio_index].global_active_dqs = NULL;
419 struct qbman_result *get_swp_active_dqs(uint16_t dpio_index)
421 return rte_global_active_dqs_list[dpio_index].global_active_dqs;
425 void set_swp_active_dqs(uint16_t dpio_index, struct qbman_result *dqs)
427 rte_global_active_dqs_list[dpio_index].global_active_dqs = dqs;
429 struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void);
430 void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp);
431 int dpaa2_dpbp_supported(void);
433 struct dpaa2_dpci_dev *rte_dpaa2_alloc_dpci_dev(void);
434 void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci);