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34 #ifndef _DPAA2_HW_PVT_H_
35 #define _DPAA2_HW_PVT_H_
37 #include <mc/fsl_mc_sys.h>
38 #include <fsl_qbman_portal.h>
46 #define lower_32_bits(x) ((uint32_t)(x))
47 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
50 #define ETH_VLAN_HLEN 4 /** < Vlan Header Length */
53 #define MAX_TX_RING_SLOTS 8
54 /** <Maximum number of slots available in TX ring*/
56 #define DPAA2_DQRR_RING_SIZE 16
57 /** <Maximum number of slots available in RX ring*/
59 #define MC_PORTAL_INDEX 0
60 #define NUM_DPIO_REGIONS 2
61 #define NUM_DQS_PER_QUEUE 2
63 /* Maximum release/acquire from QBMAN */
64 #define DPAA2_MBUF_MAX_ACQ_REL 7
67 #define DPAA2_MBUF_HW_ANNOTATION 64
68 #define DPAA2_FD_PTA_SIZE 64
70 #if (DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM
71 #error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM"
74 /* we will re-use the HEADROOM for annotation in RX */
75 #define DPAA2_HW_BUF_RESERVE 0
76 #define DPAA2_PACKET_LAYOUT_ALIGN 64 /*changing from 256 */
78 struct dpaa2_dpio_dev {
79 TAILQ_ENTRY(dpaa2_dpio_dev) next;
80 /**< Pointer to Next device instance */
81 uint16_t index; /**< Index of a instance in the list */
82 rte_atomic16_t ref_count;
83 /**< How many thread contexts are sharing this.*/
84 struct fsl_mc_io *dpio; /** handle to DPIO portal object */
86 struct qbman_swp *sw_portal; /** SW portal object */
87 const struct qbman_result *dqrr[4];
88 /**< DQRR Entry for this SW portal */
89 void *mc_portal; /**< MC Portal for configuring this device */
90 uintptr_t qbman_portal_ce_paddr;
91 /**< Physical address of Cache Enabled Area */
92 uintptr_t ce_size; /**< Size of the CE region */
93 uintptr_t qbman_portal_ci_paddr;
94 /**< Physical address of Cache Inhibit Area */
95 uintptr_t ci_size; /**< Size of the CI region */
96 int32_t vfio_fd; /**< File descriptor received via VFIO */
97 int32_t hw_id; /**< An unique ID of this DPIO device instance */
100 struct dpaa2_dpbp_dev {
101 TAILQ_ENTRY(dpaa2_dpbp_dev) next;
102 /**< Pointer to Next device instance */
103 struct fsl_mc_io dpbp; /** handle to DPBP portal object */
105 rte_atomic16_t in_use;
106 uint32_t dpbp_id; /*HW ID for DPBP object */
109 struct queue_storage_info_t {
110 struct qbman_result *dq_storage[NUM_DQS_PER_QUEUE];
114 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
116 int32_t eventfd; /*!< Event Fd of this queue */
117 uint32_t fqid; /*!< Unique ID of this queue */
118 uint8_t tc_index; /*!< traffic class identifier */
119 uint16_t flow_id; /*!< To be used by DPAA2 frmework */
123 struct queue_storage_info_t *q_storage;
126 /*! Global MCP list */
127 extern void *(*rte_mcp_ptr_list);
129 /* Refer to Table 7-3 in SEC BG */
134 /* FMT must be 00, MSB is final bit */
135 uint32_t fin_bpid_offset;
137 uint32_t reserved[3]; /* Not used currently */
140 /*Macros to define operations on FD*/
141 #define DPAA2_SET_FD_ADDR(fd, addr) do { \
142 fd->simple.addr_lo = lower_32_bits((uint64_t)(addr)); \
143 fd->simple.addr_hi = upper_32_bits((uint64_t)(addr)); \
145 #define DPAA2_SET_FD_LEN(fd, length) (fd)->simple.len = length
146 #define DPAA2_SET_FD_BPID(fd, bpid) ((fd)->simple.bpid_offset |= bpid)
147 #define DPAA2_SET_FD_OFFSET(fd, offset) \
148 ((fd->simple.bpid_offset |= (uint32_t)(offset) << 16))
149 #define DPAA2_RESET_FD_CTRL(fd) (fd)->simple.ctrl = 0
151 #define DPAA2_SET_FD_ASAL(fd, asal) ((fd)->simple.ctrl |= (asal << 16))
152 #define DPAA2_SET_FD_FLC(fd, addr) do { \
153 fd->simple.flc_lo = lower_32_bits((uint64_t)(addr)); \
154 fd->simple.flc_hi = upper_32_bits((uint64_t)(addr)); \
156 #define DPAA2_GET_FD_ADDR(fd) \
157 ((uint64_t)((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
159 #define DPAA2_GET_FD_LEN(fd) ((fd)->simple.len)
160 #define DPAA2_GET_FD_BPID(fd) (((fd)->simple.bpid_offset & 0x00003FFF))
161 #define DPAA2_GET_FD_OFFSET(fd) (((fd)->simple.bpid_offset & 0x0FFF0000) >> 16)
162 #define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \
163 ((struct rte_mbuf *)((uint64_t)(buf) - (meta_data_size)))
165 #define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64)
167 /* Only Enqueue Error responses will be
168 * pushed on FQID_ERR of Enqueue FQ
170 #define DPAA2_EQ_RESP_ERR_FQ 0
171 /* All Enqueue responses will be pushed on address
172 * set with qbman_eq_desc_set_response
174 #define DPAA2_EQ_RESP_ALWAYS 1
176 struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void);
177 void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp);