4 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
5 * Copyright (c) 2016 NXP. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Freescale Semiconductor, Inc nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _DPAA2_HW_PVT_H_
35 #define _DPAA2_HW_PVT_H_
37 #include <mc/fsl_mc_sys.h>
38 #include <fsl_qbman_portal.h>
41 #define MC_PORTAL_INDEX 0
42 #define NUM_DPIO_REGIONS 2
44 /* Maximum release/acquire from QBMAN */
45 #define DPAA2_MBUF_MAX_ACQ_REL 7
49 struct dpaa2_dpio_dev {
50 TAILQ_ENTRY(dpaa2_dpio_dev) next;
51 /**< Pointer to Next device instance */
52 uint16_t index; /**< Index of a instance in the list */
53 rte_atomic16_t ref_count;
54 /**< How many thread contexts are sharing this.*/
55 struct fsl_mc_io *dpio; /** handle to DPIO portal object */
57 struct qbman_swp *sw_portal; /** SW portal object */
58 const struct qbman_result *dqrr[4];
59 /**< DQRR Entry for this SW portal */
60 void *mc_portal; /**< MC Portal for configuring this device */
61 uintptr_t qbman_portal_ce_paddr;
62 /**< Physical address of Cache Enabled Area */
63 uintptr_t ce_size; /**< Size of the CE region */
64 uintptr_t qbman_portal_ci_paddr;
65 /**< Physical address of Cache Inhibit Area */
66 uintptr_t ci_size; /**< Size of the CI region */
67 int32_t vfio_fd; /**< File descriptor received via VFIO */
68 int32_t hw_id; /**< An unique ID of this DPIO device instance */
71 struct dpaa2_dpbp_dev {
72 TAILQ_ENTRY(dpaa2_dpbp_dev) next;
73 /**< Pointer to Next device instance */
74 struct fsl_mc_io dpbp; /** handle to DPBP portal object */
76 rte_atomic16_t in_use;
77 uint32_t dpbp_id; /*HW ID for DPBP object */
80 /*! Global MCP list */
81 extern void *(*rte_mcp_ptr_list);
83 struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void);
84 void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp);