1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
7 #include "qbman_portal.h"
9 /* QBMan portal management command codes */
10 #define QBMAN_MC_ACQUIRE 0x30
11 #define QBMAN_WQCHAN_CONFIGURE 0x46
13 /* CINH register offsets */
14 #define QBMAN_CINH_SWP_EQCR_PI 0x800
15 #define QBMAN_CINH_SWP_EQCR_CI 0x840
16 #define QBMAN_CINH_SWP_EQAR 0x8c0
17 #define QBMAN_CINH_SWP_DQPI 0xa00
18 #define QBMAN_CINH_SWP_DCAP 0xac0
19 #define QBMAN_CINH_SWP_SDQCR 0xb00
20 #define QBMAN_CINH_SWP_RAR 0xcc0
21 #define QBMAN_CINH_SWP_ISR 0xe00
22 #define QBMAN_CINH_SWP_IER 0xe40
23 #define QBMAN_CINH_SWP_ISDR 0xe80
24 #define QBMAN_CINH_SWP_IIR 0xec0
25 #define QBMAN_CINH_SWP_DQRR_ITR 0xa80
26 #define QBMAN_CINH_SWP_ITPR 0xf40
28 /* CENA register offsets */
29 #define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((uint32_t)(n) << 6))
30 #define QBMAN_CENA_SWP_DQRR(n) (0x200 + ((uint32_t)(n) << 6))
31 #define QBMAN_CENA_SWP_RCR(n) (0x400 + ((uint32_t)(n) << 6))
32 #define QBMAN_CENA_SWP_CR 0x600
33 #define QBMAN_CENA_SWP_RR(vb) (0x700 + ((uint32_t)(vb) >> 1))
34 #define QBMAN_CENA_SWP_VDQCR 0x780
35 #define QBMAN_CENA_SWP_EQCR_CI 0x840
37 /* Reverse mapping of QBMAN_CENA_SWP_DQRR() */
38 #define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)p & 0x1ff) >> 6)
40 /* QBMan FQ management command codes */
41 #define QBMAN_FQ_SCHEDULE 0x48
42 #define QBMAN_FQ_FORCE 0x49
43 #define QBMAN_FQ_XON 0x4d
44 #define QBMAN_FQ_XOFF 0x4e
46 /*******************************/
47 /* Pre-defined attribute codes */
48 /*******************************/
50 #define QBMAN_RESPONSE_VERB_MASK 0x7f
52 /*************************/
53 /* SDQCR attribute codes */
54 /*************************/
55 #define QB_SDQCR_FC_SHIFT 29
56 #define QB_SDQCR_FC_MASK 0x1
57 #define QB_SDQCR_DCT_SHIFT 24
58 #define QB_SDQCR_DCT_MASK 0x3
59 #define QB_SDQCR_TOK_SHIFT 16
60 #define QB_SDQCR_TOK_MASK 0xff
61 #define QB_SDQCR_SRC_SHIFT 0
62 #define QB_SDQCR_SRC_MASK 0xffff
64 /* opaque token for static dequeues */
65 #define QMAN_SDQCR_TOKEN 0xbb
67 enum qbman_sdqcr_dct {
68 qbman_sdqcr_dct_null = 0,
69 qbman_sdqcr_dct_prio_ics,
70 qbman_sdqcr_dct_active_ics,
71 qbman_sdqcr_dct_active
75 qbman_sdqcr_fc_one = 0,
76 qbman_sdqcr_fc_up_to_3 = 1
79 /* We need to keep track of which SWP triggered a pull command
80 * so keep an array of portal IDs and use the token field to
81 * be able to find the proper portal
83 #define MAX_QBMAN_PORTALS 64
84 static struct qbman_swp *portal_idx_map[MAX_QBMAN_PORTALS];
86 /*********************************/
87 /* Portal constructor/destructor */
88 /*********************************/
90 /* Software portals should always be in the power-on state when we initialise,
91 * due to the CCSR-based portal reset functionality that MC has.
93 * Erk! Turns out that QMan versions prior to 4.1 do not correctly reset DQRR
94 * valid-bits, so we need to support a workaround where we don't trust
95 * valid-bits when detecting new entries until any stale ring entries have been
96 * overwritten at least once. The idea is that we read PI for the first few
97 * entries, then switch to valid-bit after that. The trick is to clear the
98 * bug-work-around boolean once the PI wraps around the ring for the first time.
100 * Note: this still carries a slight additional cost once the decrementer hits
103 struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
107 struct qbman_swp *p = malloc(sizeof(*p));
112 #ifdef QBMAN_CHECKING
113 p->mc.check = swp_mc_can_start;
115 p->mc.valid_bit = QB_VALID_BIT;
117 p->sdq |= qbman_sdqcr_dct_prio_ics << QB_SDQCR_DCT_SHIFT;
118 p->sdq |= qbman_sdqcr_fc_up_to_3 << QB_SDQCR_FC_SHIFT;
119 p->sdq |= QMAN_SDQCR_TOKEN << QB_SDQCR_TOK_SHIFT;
121 atomic_set(&p->vdq.busy, 1);
122 p->vdq.valid_bit = QB_VALID_BIT;
123 p->dqrr.next_idx = 0;
124 p->dqrr.valid_bit = QB_VALID_BIT;
125 if ((p->desc.qman_version & 0xFFFF0000) < QMAN_REV_4100) {
126 p->dqrr.dqrr_size = 4;
127 p->dqrr.reset_bug = 1;
129 p->dqrr.dqrr_size = 8;
130 p->dqrr.reset_bug = 0;
133 ret = qbman_swp_sys_init(&p->sys, d, p->dqrr.dqrr_size);
136 pr_err("qbman_swp_sys_init() failed %d\n", ret);
139 /* SDQCR needs to be initialized to 0 when no channels are
140 * being dequeued from or else the QMan HW will indicate an
141 * error. The values that were calculated above will be
142 * applied when dequeues from a specific channel are enabled.
144 qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_SDQCR, 0);
145 eqcr_pi = qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_EQCR_PI);
146 p->eqcr.pi = eqcr_pi & 0xF;
147 p->eqcr.pi_vb = eqcr_pi & QB_VALID_BIT;
148 p->eqcr.ci = qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_EQCR_CI) & 0xF;
149 p->eqcr.available = QBMAN_EQCR_SIZE - qm_cyc_diff(QBMAN_EQCR_SIZE,
150 p->eqcr.ci, p->eqcr.pi);
152 portal_idx_map[p->desc.idx] = p;
156 void qbman_swp_finish(struct qbman_swp *p)
158 #ifdef QBMAN_CHECKING
159 QBMAN_BUG_ON(p->mc.check != swp_mc_can_start);
161 qbman_swp_sys_finish(&p->sys);
162 portal_idx_map[p->desc.idx] = NULL;
166 const struct qbman_swp_desc *qbman_swp_get_desc(struct qbman_swp *p)
175 uint32_t qbman_swp_interrupt_get_vanish(struct qbman_swp *p)
177 return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_ISDR);
180 void qbman_swp_interrupt_set_vanish(struct qbman_swp *p, uint32_t mask)
182 qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ISDR, mask);
185 uint32_t qbman_swp_interrupt_read_status(struct qbman_swp *p)
187 return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_ISR);
190 void qbman_swp_interrupt_clear_status(struct qbman_swp *p, uint32_t mask)
192 qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ISR, mask);
195 uint32_t qbman_swp_dqrr_thrshld_read_status(struct qbman_swp *p)
197 return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_DQRR_ITR);
200 void qbman_swp_dqrr_thrshld_write(struct qbman_swp *p, uint32_t mask)
202 qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_DQRR_ITR, mask);
205 uint32_t qbman_swp_intr_timeout_read_status(struct qbman_swp *p)
207 return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_ITPR);
210 void qbman_swp_intr_timeout_write(struct qbman_swp *p, uint32_t mask)
212 qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ITPR, mask);
215 uint32_t qbman_swp_interrupt_get_trigger(struct qbman_swp *p)
217 return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_IER);
220 void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, uint32_t mask)
222 qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_IER, mask);
225 int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p)
227 return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_IIR);
230 void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit)
232 qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_IIR, inhibit ? 0xffffffff : 0);
235 /***********************/
236 /* Management commands */
237 /***********************/
240 * Internal code common to all types of management commands.
243 void *qbman_swp_mc_start(struct qbman_swp *p)
246 #ifdef QBMAN_CHECKING
247 QBMAN_BUG_ON(p->mc.check != swp_mc_can_start);
249 ret = qbman_cena_write_start(&p->sys, QBMAN_CENA_SWP_CR);
250 #ifdef QBMAN_CHECKING
252 p->mc.check = swp_mc_can_submit;
257 void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint8_t cmd_verb)
260 #ifdef QBMAN_CHECKING
261 QBMAN_BUG_ON(!(p->mc.check != swp_mc_can_submit));
263 /* TBD: "|=" is going to hurt performance. Need to move as many fields
264 * out of word zero, and for those that remain, the "OR" needs to occur
265 * at the caller side. This debug check helps to catch cases where the
266 * caller wants to OR but has forgotten to do so.
268 QBMAN_BUG_ON((*v & cmd_verb) != *v);
269 *v = cmd_verb | p->mc.valid_bit;
270 qbman_cena_write_complete(&p->sys, QBMAN_CENA_SWP_CR, cmd);
271 #ifdef QBMAN_CHECKING
272 p->mc.check = swp_mc_can_poll;
276 void *qbman_swp_mc_result(struct qbman_swp *p)
279 #ifdef QBMAN_CHECKING
280 QBMAN_BUG_ON(p->mc.check != swp_mc_can_poll);
282 qbman_cena_invalidate_prefetch(&p->sys,
283 QBMAN_CENA_SWP_RR(p->mc.valid_bit));
284 ret = qbman_cena_read(&p->sys, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
285 /* Remove the valid-bit - command completed if the rest is non-zero */
286 verb = ret[0] & ~QB_VALID_BIT;
289 #ifdef QBMAN_CHECKING
290 p->mc.check = swp_mc_can_start;
292 p->mc.valid_bit ^= QB_VALID_BIT;
300 #define QB_ENQUEUE_CMD_OPTIONS_SHIFT 0
301 enum qb_enqueue_commands {
303 enqueue_response_always = 1,
304 enqueue_rejects_to_fq = 2
307 #define QB_ENQUEUE_CMD_EC_OPTION_MASK 0x3
308 #define QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT 2
309 #define QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT 3
310 #define QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT 4
311 #define QB_ENQUEUE_CMD_DCA_PK_SHIFT 6
312 #define QB_ENQUEUE_CMD_DCA_EN_SHIFT 7
313 #define QB_ENQUEUE_CMD_NLIS_SHIFT 14
314 #define QB_ENQUEUE_CMD_IS_NESN_SHIFT 15
316 void qbman_eq_desc_clear(struct qbman_eq_desc *d)
318 memset(d, 0, sizeof(*d));
321 void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success)
323 d->eq.verb &= ~(1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT);
325 d->eq.verb |= enqueue_response_always;
327 d->eq.verb |= enqueue_rejects_to_fq;
330 void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success,
331 uint16_t opr_id, uint16_t seqnum, int incomplete)
333 d->eq.verb |= 1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT;
335 d->eq.verb |= enqueue_response_always;
337 d->eq.verb |= enqueue_rejects_to_fq;
339 d->eq.orpid = opr_id;
340 d->eq.seqnum = seqnum;
342 d->eq.seqnum |= 1 << QB_ENQUEUE_CMD_NLIS_SHIFT;
344 d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_NLIS_SHIFT);
347 void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, uint16_t opr_id,
350 d->eq.verb |= 1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT;
351 d->eq.verb &= ~QB_ENQUEUE_CMD_EC_OPTION_MASK;
352 d->eq.orpid = opr_id;
353 d->eq.seqnum = seqnum;
354 d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_NLIS_SHIFT);
355 d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_IS_NESN_SHIFT);
358 void qbman_eq_desc_set_orp_nesn(struct qbman_eq_desc *d, uint16_t opr_id,
361 d->eq.verb |= 1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT;
362 d->eq.verb &= ~QB_ENQUEUE_CMD_EC_OPTION_MASK;
363 d->eq.orpid = opr_id;
364 d->eq.seqnum = seqnum;
365 d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_NLIS_SHIFT);
366 d->eq.seqnum |= 1 << QB_ENQUEUE_CMD_IS_NESN_SHIFT;
369 void qbman_eq_desc_set_response(struct qbman_eq_desc *d,
370 dma_addr_t storage_phys,
373 d->eq.rsp_addr = storage_phys;
377 void qbman_eq_desc_set_token(struct qbman_eq_desc *d, uint8_t token)
382 void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, uint32_t fqid)
384 d->eq.verb &= ~(1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT);
388 void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid,
389 uint16_t qd_bin, uint8_t qd_prio)
391 d->eq.verb |= 1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT;
393 d->eq.qdbin = qd_bin;
394 d->eq.qpri = qd_prio;
397 void qbman_eq_desc_set_eqdi(struct qbman_eq_desc *d, int enable)
400 d->eq.verb |= 1 << QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT;
402 d->eq.verb &= ~(1 << QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT);
405 void qbman_eq_desc_set_dca(struct qbman_eq_desc *d, int enable,
406 uint8_t dqrr_idx, int park)
409 d->eq.dca = dqrr_idx;
411 d->eq.dca |= 1 << QB_ENQUEUE_CMD_DCA_PK_SHIFT;
413 d->eq.dca &= ~(1 << QB_ENQUEUE_CMD_DCA_PK_SHIFT);
414 d->eq.dca |= 1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT;
416 d->eq.dca &= ~(1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT);
420 #define EQAR_IDX(eqar) ((eqar) & 0x7)
421 #define EQAR_VB(eqar) ((eqar) & 0x80)
422 #define EQAR_SUCCESS(eqar) ((eqar) & 0x100)
424 static int qbman_swp_enqueue_array_mode(struct qbman_swp *s,
425 const struct qbman_eq_desc *d,
426 const struct qbman_fd *fd)
429 const uint32_t *cl = qb_cl(d);
430 uint32_t eqar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_EQAR);
432 pr_debug("EQAR=%08x\n", eqar);
433 if (!EQAR_SUCCESS(eqar))
435 p = qbman_cena_write_start_wo_shadow(&s->sys,
436 QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
437 memcpy(&p[1], &cl[1], 28);
438 memcpy(&p[8], fd, sizeof(*fd));
439 /* Set the verb byte, have to substitute in the valid-bit */
441 p[0] = cl[0] | EQAR_VB(eqar);
442 qbman_cena_write_complete_wo_shadow(&s->sys,
443 QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
447 static int qbman_swp_enqueue_ring_mode(struct qbman_swp *s,
448 const struct qbman_eq_desc *d,
449 const struct qbman_fd *fd)
452 const uint32_t *cl = qb_cl(d);
456 if (!s->eqcr.available) {
457 eqcr_ci = s->eqcr.ci;
458 s->eqcr.ci = qbman_cena_read_reg(&s->sys,
459 QBMAN_CENA_SWP_EQCR_CI) & 0xF;
460 diff = qm_cyc_diff(QBMAN_EQCR_SIZE,
461 eqcr_ci, s->eqcr.ci);
462 s->eqcr.available += diff;
467 p = qbman_cena_write_start_wo_shadow(&s->sys,
468 QBMAN_CENA_SWP_EQCR(s->eqcr.pi & 7));
469 memcpy(&p[1], &cl[1], 28);
470 memcpy(&p[8], fd, sizeof(*fd));
473 /* Set the verb byte, have to substitute in the valid-bit */
474 p[0] = cl[0] | s->eqcr.pi_vb;
475 qbman_cena_write_complete_wo_shadow(&s->sys,
476 QBMAN_CENA_SWP_EQCR(s->eqcr.pi & 7));
480 if (!(s->eqcr.pi & 7))
481 s->eqcr.pi_vb ^= QB_VALID_BIT;
486 int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,
487 const struct qbman_fd *fd)
489 if (s->sys.eqcr_mode == qman_eqcr_vb_array)
490 return qbman_swp_enqueue_array_mode(s, d, fd);
491 else /* Use ring mode by default */
492 return qbman_swp_enqueue_ring_mode(s, d, fd);
495 int qbman_swp_enqueue_multiple(struct qbman_swp *s,
496 const struct qbman_eq_desc *d,
497 const struct qbman_fd *fd,
502 const uint32_t *cl = qb_cl(d);
503 uint32_t eqcr_ci, eqcr_pi;
505 int i, num_enqueued = 0;
508 if (!s->eqcr.available) {
509 eqcr_ci = s->eqcr.ci;
510 s->eqcr.ci = qbman_cena_read_reg(&s->sys,
511 QBMAN_CENA_SWP_EQCR_CI) & 0xF;
512 diff = qm_cyc_diff(QBMAN_EQCR_SIZE,
513 eqcr_ci, s->eqcr.ci);
514 s->eqcr.available += diff;
519 eqcr_pi = s->eqcr.pi;
520 num_enqueued = (s->eqcr.available < num_frames) ?
521 s->eqcr.available : num_frames;
522 s->eqcr.available -= num_enqueued;
523 /* Fill in the EQCR ring */
524 for (i = 0; i < num_enqueued; i++) {
525 p = qbman_cena_write_start_wo_shadow(&s->sys,
526 QBMAN_CENA_SWP_EQCR(eqcr_pi & 7));
527 memcpy(&p[1], &cl[1], 28);
528 memcpy(&p[8], &fd[i], sizeof(*fd));
535 /* Set the verb byte, have to substitute in the valid-bit */
536 eqcr_pi = s->eqcr.pi;
537 for (i = 0; i < num_enqueued; i++) {
538 p = qbman_cena_write_start_wo_shadow(&s->sys,
539 QBMAN_CENA_SWP_EQCR(eqcr_pi & 7));
540 p[0] = cl[0] | s->eqcr.pi_vb;
541 if (flags && (flags[i] & QBMAN_ENQUEUE_FLAG_DCA)) {
542 struct qbman_eq_desc *d = (struct qbman_eq_desc *)p;
544 d->eq.dca = (1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT) |
545 ((flags[i]) & QBMAN_EQCR_DCA_IDXMASK);
550 s->eqcr.pi_vb ^= QB_VALID_BIT;
553 /* Flush all the cacheline without load/store in between */
554 eqcr_pi = s->eqcr.pi;
555 addr_cena = (size_t)s->sys.addr_cena;
556 for (i = 0; i < num_enqueued; i++) {
557 dcbf((addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
561 s->eqcr.pi = eqcr_pi;
566 int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s,
567 const struct qbman_eq_desc *d,
568 const struct qbman_fd *fd,
573 uint32_t eqcr_ci, eqcr_pi;
575 int i, num_enqueued = 0;
578 if (!s->eqcr.available) {
579 eqcr_ci = s->eqcr.ci;
580 s->eqcr.ci = qbman_cena_read_reg(&s->sys,
581 QBMAN_CENA_SWP_EQCR_CI) & 0xF;
582 diff = qm_cyc_diff(QBMAN_EQCR_SIZE,
583 eqcr_ci, s->eqcr.ci);
584 s->eqcr.available += diff;
589 eqcr_pi = s->eqcr.pi;
590 num_enqueued = (s->eqcr.available < num_frames) ?
591 s->eqcr.available : num_frames;
592 s->eqcr.available -= num_enqueued;
593 /* Fill in the EQCR ring */
594 for (i = 0; i < num_enqueued; i++) {
595 p = qbman_cena_write_start_wo_shadow(&s->sys,
596 QBMAN_CENA_SWP_EQCR(eqcr_pi & 7));
598 memcpy(&p[1], &cl[1], 28);
599 memcpy(&p[8], &fd[i], sizeof(*fd));
606 /* Set the verb byte, have to substitute in the valid-bit */
607 eqcr_pi = s->eqcr.pi;
608 for (i = 0; i < num_enqueued; i++) {
609 p = qbman_cena_write_start_wo_shadow(&s->sys,
610 QBMAN_CENA_SWP_EQCR(eqcr_pi & 7));
612 p[0] = cl[0] | s->eqcr.pi_vb;
616 s->eqcr.pi_vb ^= QB_VALID_BIT;
619 /* Flush all the cacheline without load/store in between */
620 eqcr_pi = s->eqcr.pi;
621 addr_cena = (size_t)s->sys.addr_cena;
622 for (i = 0; i < num_enqueued; i++) {
623 dcbf((addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
627 s->eqcr.pi = eqcr_pi;
632 /*************************/
633 /* Static (push) dequeue */
634 /*************************/
636 void qbman_swp_push_get(struct qbman_swp *s, uint8_t channel_idx, int *enabled)
638 uint16_t src = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
640 QBMAN_BUG_ON(channel_idx > 15);
641 *enabled = src | (1 << channel_idx);
644 void qbman_swp_push_set(struct qbman_swp *s, uint8_t channel_idx, int enable)
648 QBMAN_BUG_ON(channel_idx > 15);
650 s->sdq |= 1 << channel_idx;
652 s->sdq &= ~(1 << channel_idx);
654 /* Read make the complete src map. If no channels are enabled
655 * the SDQCR must be 0 or else QMan will assert errors
657 dqsrc = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
659 qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_SDQCR, s->sdq);
661 qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_SDQCR, 0);
664 /***************************/
665 /* Volatile (pull) dequeue */
666 /***************************/
668 /* These should be const, eventually */
669 #define QB_VDQCR_VERB_DCT_SHIFT 0
670 #define QB_VDQCR_VERB_DT_SHIFT 2
671 #define QB_VDQCR_VERB_RLS_SHIFT 4
672 #define QB_VDQCR_VERB_WAE_SHIFT 5
676 qb_pull_dt_workqueue,
677 qb_pull_dt_framequeue
680 void qbman_pull_desc_clear(struct qbman_pull_desc *d)
682 memset(d, 0, sizeof(*d));
685 void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
686 struct qbman_result *storage,
687 dma_addr_t storage_phys,
690 d->pull.rsp_addr_virt = (size_t)storage;
693 d->pull.verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT);
696 d->pull.verb |= 1 << QB_VDQCR_VERB_RLS_SHIFT;
698 d->pull.verb |= 1 << QB_VDQCR_VERB_WAE_SHIFT;
700 d->pull.verb &= ~(1 << QB_VDQCR_VERB_WAE_SHIFT);
702 d->pull.rsp_addr = storage_phys;
705 void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, uint8_t numframes)
707 d->pull.numf = numframes - 1;
710 void qbman_pull_desc_set_token(struct qbman_pull_desc *d, uint8_t token)
715 void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, uint32_t fqid)
717 d->pull.verb |= 1 << QB_VDQCR_VERB_DCT_SHIFT;
718 d->pull.verb |= qb_pull_dt_framequeue << QB_VDQCR_VERB_DT_SHIFT;
719 d->pull.dq_src = fqid;
722 void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, uint32_t wqid,
723 enum qbman_pull_type_e dct)
725 d->pull.verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
726 d->pull.verb |= qb_pull_dt_workqueue << QB_VDQCR_VERB_DT_SHIFT;
727 d->pull.dq_src = wqid;
730 void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, uint32_t chid,
731 enum qbman_pull_type_e dct)
733 d->pull.verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
734 d->pull.verb |= qb_pull_dt_channel << QB_VDQCR_VERB_DT_SHIFT;
735 d->pull.dq_src = chid;
738 int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d)
741 uint32_t *cl = qb_cl(d);
743 if (!atomic_dec_and_test(&s->vdq.busy)) {
744 atomic_inc(&s->vdq.busy);
748 d->pull.tok = s->sys.idx + 1;
749 s->vdq.storage = (void *)(size_t)d->pull.rsp_addr_virt;
750 p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR);
751 memcpy(&p[1], &cl[1], 12);
753 /* Set the verb byte, have to substitute in the valid-bit */
755 p[0] = cl[0] | s->vdq.valid_bit;
756 s->vdq.valid_bit ^= QB_VALID_BIT;
757 qbman_cena_write_complete_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR);
766 #define QMAN_DQRR_PI_MASK 0xf
768 #define QBMAN_RESULT_DQ 0x60
769 #define QBMAN_RESULT_FQRN 0x21
770 #define QBMAN_RESULT_FQRNI 0x22
771 #define QBMAN_RESULT_FQPN 0x24
772 #define QBMAN_RESULT_FQDAN 0x25
773 #define QBMAN_RESULT_CDAN 0x26
774 #define QBMAN_RESULT_CSCN_MEM 0x27
775 #define QBMAN_RESULT_CGCU 0x28
776 #define QBMAN_RESULT_BPSCN 0x29
777 #define QBMAN_RESULT_CSCN_WQ 0x2a
779 #include <rte_prefetch.h>
781 void qbman_swp_prefetch_dqrr_next(struct qbman_swp *s)
783 const struct qbman_result *p;
785 p = qbman_cena_read_wo_shadow(&s->sys,
786 QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
790 /* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry
791 * only once, so repeated calls can return a sequence of DQRR entries, without
792 * requiring they be consumed immediately or in any particular order.
794 const struct qbman_result *qbman_swp_dqrr_next(struct qbman_swp *s)
797 uint32_t response_verb;
799 const struct qbman_result *p;
801 /* Before using valid-bit to detect if something is there, we have to
802 * handle the case of the DQRR reset bug...
804 if (unlikely(s->dqrr.reset_bug)) {
805 /* We pick up new entries by cache-inhibited producer index,
806 * which means that a non-coherent mapping would require us to
807 * invalidate and read *only* once that PI has indicated that
808 * there's an entry here. The first trip around the DQRR ring
809 * will be much less efficient than all subsequent trips around
812 uint8_t pi = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_DQPI) &
815 /* there are new entries if pi != next_idx */
816 if (pi == s->dqrr.next_idx)
819 /* if next_idx is/was the last ring index, and 'pi' is
820 * different, we can disable the workaround as all the ring
821 * entries have now been DMA'd to so valid-bit checking is
822 * repaired. Note: this logic needs to be based on next_idx
823 * (which increments one at a time), rather than on pi (which
824 * can burst and wrap-around between our snapshots of it).
826 QBMAN_BUG_ON((s->dqrr.dqrr_size - 1) < 0);
827 if (s->dqrr.next_idx == (s->dqrr.dqrr_size - 1u)) {
828 pr_debug("DEBUG: next_idx=%d, pi=%d, clear reset bug\n",
829 s->dqrr.next_idx, pi);
830 s->dqrr.reset_bug = 0;
832 qbman_cena_invalidate_prefetch(&s->sys,
833 QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
835 p = qbman_cena_read_wo_shadow(&s->sys,
836 QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
839 /* If the valid-bit isn't of the expected polarity, nothing there. Note,
840 * in the DQRR reset bug workaround, we shouldn't need to skip these
841 * check, because we've already determined that a new entry is available
842 * and we've invalidated the cacheline before reading it, so the
843 * valid-bit behaviour is repaired and should tell us what we already
844 * knew from reading PI.
846 if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit)
849 /* There's something there. Move "next_idx" attention to the next ring
850 * entry (and prefetch it) before returning what we found.
853 if (s->dqrr.next_idx == s->dqrr.dqrr_size) {
854 s->dqrr.next_idx = 0;
855 s->dqrr.valid_bit ^= QB_VALID_BIT;
857 /* If this is the final response to a volatile dequeue command
858 * indicate that the vdq is no longer busy
861 response_verb = verb & QBMAN_RESPONSE_VERB_MASK;
862 if ((response_verb == QBMAN_RESULT_DQ) &&
863 (flags & QBMAN_DQ_STAT_VOLATILE) &&
864 (flags & QBMAN_DQ_STAT_EXPIRED))
865 atomic_inc(&s->vdq.busy);
870 /* Consume DQRR entries previously returned from qbman_swp_dqrr_next(). */
871 void qbman_swp_dqrr_consume(struct qbman_swp *s,
872 const struct qbman_result *dq)
874 qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq));
877 /* Consume DQRR entries previously returned from qbman_swp_dqrr_next(). */
878 void qbman_swp_dqrr_idx_consume(struct qbman_swp *s,
881 qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_DCAP, dqrr_index);
884 /*********************************/
885 /* Polling user-provided storage */
886 /*********************************/
887 int qbman_result_has_new_result(struct qbman_swp *s,
888 struct qbman_result *dq)
894 * Set token to be 0 so we will detect change back to 1
895 * next time the looping is traversed. Const is cast away here
896 * as we want users to treat the dequeue responses as read only.
898 ((struct qbman_result *)dq)->dq.tok = 0;
901 * VDQCR "no longer busy" hook - not quite the same as DQRR, because the
902 * fact "VDQCR" shows busy doesn't mean that we hold the result that
903 * makes it available. Eg. we may be looking at our 10th dequeue result,
904 * having released VDQCR after the 1st result and it is now busy due to
905 * some other command!
907 if (s->vdq.storage == dq) {
908 s->vdq.storage = NULL;
909 atomic_inc(&s->vdq.busy);
915 int qbman_check_new_result(struct qbman_result *dq)
921 * Set token to be 0 so we will detect change back to 1
922 * next time the looping is traversed. Const is cast away here
923 * as we want users to treat the dequeue responses as read only.
925 ((struct qbman_result *)dq)->dq.tok = 0;
930 int qbman_check_command_complete(struct qbman_result *dq)
937 s = portal_idx_map[dq->dq.tok - 1];
939 * VDQCR "no longer busy" hook - not quite the same as DQRR, because the
940 * fact "VDQCR" shows busy doesn't mean that we hold the result that
941 * makes it available. Eg. we may be looking at our 10th dequeue result,
942 * having released VDQCR after the 1st result and it is now busy due to
943 * some other command!
945 if (s->vdq.storage == dq) {
946 s->vdq.storage = NULL;
947 atomic_inc(&s->vdq.busy);
953 /********************************/
954 /* Categorising qbman results */
955 /********************************/
957 static inline int __qbman_result_is_x(const struct qbman_result *dq,
960 uint8_t response_verb = dq->dq.verb & QBMAN_RESPONSE_VERB_MASK;
962 return (response_verb == x);
965 int qbman_result_is_DQ(const struct qbman_result *dq)
967 return __qbman_result_is_x(dq, QBMAN_RESULT_DQ);
970 int qbman_result_is_FQDAN(const struct qbman_result *dq)
972 return __qbman_result_is_x(dq, QBMAN_RESULT_FQDAN);
975 int qbman_result_is_CDAN(const struct qbman_result *dq)
977 return __qbman_result_is_x(dq, QBMAN_RESULT_CDAN);
980 int qbman_result_is_CSCN(const struct qbman_result *dq)
982 return __qbman_result_is_x(dq, QBMAN_RESULT_CSCN_MEM) ||
983 __qbman_result_is_x(dq, QBMAN_RESULT_CSCN_WQ);
986 int qbman_result_is_BPSCN(const struct qbman_result *dq)
988 return __qbman_result_is_x(dq, QBMAN_RESULT_BPSCN);
991 int qbman_result_is_CGCU(const struct qbman_result *dq)
993 return __qbman_result_is_x(dq, QBMAN_RESULT_CGCU);
996 int qbman_result_is_FQRN(const struct qbman_result *dq)
998 return __qbman_result_is_x(dq, QBMAN_RESULT_FQRN);
1001 int qbman_result_is_FQRNI(const struct qbman_result *dq)
1003 return __qbman_result_is_x(dq, QBMAN_RESULT_FQRNI);
1006 int qbman_result_is_FQPN(const struct qbman_result *dq)
1008 return __qbman_result_is_x(dq, QBMAN_RESULT_FQPN);
1011 /*********************************/
1012 /* Parsing frame dequeue results */
1013 /*********************************/
1015 /* These APIs assume qbman_result_is_DQ() is TRUE */
1017 uint8_t qbman_result_DQ_flags(const struct qbman_result *dq)
1022 uint16_t qbman_result_DQ_seqnum(const struct qbman_result *dq)
1024 return dq->dq.seqnum;
1027 uint16_t qbman_result_DQ_odpid(const struct qbman_result *dq)
1029 return dq->dq.oprid;
1032 uint32_t qbman_result_DQ_fqid(const struct qbman_result *dq)
1037 uint32_t qbman_result_DQ_byte_count(const struct qbman_result *dq)
1039 return dq->dq.fq_byte_cnt;
1042 uint32_t qbman_result_DQ_frame_count(const struct qbman_result *dq)
1044 return dq->dq.fq_frm_cnt;
1047 uint64_t qbman_result_DQ_fqd_ctx(const struct qbman_result *dq)
1049 return dq->dq.fqd_ctx;
1052 const struct qbman_fd *qbman_result_DQ_fd(const struct qbman_result *dq)
1054 return (const struct qbman_fd *)&dq->dq.fd[0];
1057 /**************************************/
1058 /* Parsing state-change notifications */
1059 /**************************************/
1060 uint8_t qbman_result_SCN_state(const struct qbman_result *scn)
1062 return scn->scn.state;
1065 uint32_t qbman_result_SCN_rid(const struct qbman_result *scn)
1067 return scn->scn.rid_tok;
1070 uint64_t qbman_result_SCN_ctx(const struct qbman_result *scn)
1072 return scn->scn.ctx;
1078 uint16_t qbman_result_bpscn_bpid(const struct qbman_result *scn)
1080 return (uint16_t)qbman_result_SCN_rid(scn) & 0x3FFF;
1083 int qbman_result_bpscn_has_free_bufs(const struct qbman_result *scn)
1085 return !(int)(qbman_result_SCN_state(scn) & 0x1);
1088 int qbman_result_bpscn_is_depleted(const struct qbman_result *scn)
1090 return (int)(qbman_result_SCN_state(scn) & 0x2);
1093 int qbman_result_bpscn_is_surplus(const struct qbman_result *scn)
1095 return (int)(qbman_result_SCN_state(scn) & 0x4);
1098 uint64_t qbman_result_bpscn_ctx(const struct qbman_result *scn)
1100 return qbman_result_SCN_ctx(scn);
1106 uint16_t qbman_result_cgcu_cgid(const struct qbman_result *scn)
1108 return (uint16_t)qbman_result_SCN_rid(scn) & 0xFFFF;
1111 uint64_t qbman_result_cgcu_icnt(const struct qbman_result *scn)
1113 return qbman_result_SCN_ctx(scn);
1116 /******************/
1117 /* Buffer release */
1118 /******************/
1119 #define QB_BR_RC_VALID_SHIFT 5
1120 #define QB_BR_RCDI_SHIFT 6
1122 void qbman_release_desc_clear(struct qbman_release_desc *d)
1124 memset(d, 0, sizeof(*d));
1125 d->br.verb = 1 << QB_BR_RC_VALID_SHIFT;
1128 void qbman_release_desc_set_bpid(struct qbman_release_desc *d, uint16_t bpid)
1133 void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable)
1136 d->br.verb |= 1 << QB_BR_RCDI_SHIFT;
1138 d->br.verb &= ~(1 << QB_BR_RCDI_SHIFT);
1141 #define RAR_IDX(rar) ((rar) & 0x7)
1142 #define RAR_VB(rar) ((rar) & 0x80)
1143 #define RAR_SUCCESS(rar) ((rar) & 0x100)
1145 int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
1146 const uint64_t *buffers, unsigned int num_buffers)
1149 const uint32_t *cl = qb_cl(d);
1150 uint32_t rar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_RAR);
1152 pr_debug("RAR=%08x\n", rar);
1153 if (!RAR_SUCCESS(rar))
1156 QBMAN_BUG_ON(!num_buffers || (num_buffers > 7));
1158 /* Start the release command */
1159 p = qbman_cena_write_start_wo_shadow(&s->sys,
1160 QBMAN_CENA_SWP_RCR(RAR_IDX(rar)));
1162 /* Copy the caller's buffer pointers to the command */
1163 u64_to_le32_copy(&p[2], buffers, num_buffers);
1165 /* Set the verb byte, have to substitute in the valid-bit and the number
1169 p[0] = cl[0] | RAR_VB(rar) | num_buffers;
1170 qbman_cena_write_complete_wo_shadow(&s->sys,
1171 QBMAN_CENA_SWP_RCR(RAR_IDX(rar)));
1176 /*******************/
1177 /* Buffer acquires */
1178 /*******************/
1179 struct qbman_acquire_desc {
1184 uint8_t reserved2[59];
1187 struct qbman_acquire_rslt {
1192 uint8_t reserved2[3];
1196 int qbman_swp_acquire(struct qbman_swp *s, uint16_t bpid, uint64_t *buffers,
1197 unsigned int num_buffers)
1199 struct qbman_acquire_desc *p;
1200 struct qbman_acquire_rslt *r;
1202 if (!num_buffers || (num_buffers > 7))
1205 /* Start the management command */
1206 p = qbman_swp_mc_start(s);
1211 /* Encode the caller-provided attributes */
1213 p->num = num_buffers;
1215 /* Complete the management command */
1216 r = qbman_swp_mc_complete(s, p, QBMAN_MC_ACQUIRE);
1218 pr_err("qbman: acquire from BPID %d failed, no response\n",
1223 /* Decode the outcome */
1224 QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != QBMAN_MC_ACQUIRE);
1226 /* Determine success or failure */
1227 if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
1228 pr_err("Acquire buffers from BPID 0x%x failed, code=0x%02x\n",
1233 QBMAN_BUG_ON(r->num > num_buffers);
1235 /* Copy the acquired buffers to the caller's array */
1236 u64_from_le32_copy(buffers, &r->buf[0], r->num);
1244 struct qbman_alt_fq_state_desc {
1246 uint8_t reserved[3];
1248 uint8_t reserved2[56];
1251 struct qbman_alt_fq_state_rslt {
1254 uint8_t reserved[62];
1257 #define ALT_FQ_FQID_MASK 0x00FFFFFF
1259 static int qbman_swp_alt_fq_state(struct qbman_swp *s, uint32_t fqid,
1260 uint8_t alt_fq_verb)
1262 struct qbman_alt_fq_state_desc *p;
1263 struct qbman_alt_fq_state_rslt *r;
1265 /* Start the management command */
1266 p = qbman_swp_mc_start(s);
1270 p->fqid = fqid & ALT_FQ_FQID_MASK;
1272 /* Complete the management command */
1273 r = qbman_swp_mc_complete(s, p, alt_fq_verb);
1275 pr_err("qbman: mgmt cmd failed, no response (verb=0x%x)\n",
1280 /* Decode the outcome */
1281 QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != alt_fq_verb);
1283 /* Determine success or failure */
1284 if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
1285 pr_err("ALT FQID %d failed: verb = 0x%08x, code = 0x%02x\n",
1286 fqid, alt_fq_verb, r->rslt);
1293 int qbman_swp_fq_schedule(struct qbman_swp *s, uint32_t fqid)
1295 return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_SCHEDULE);
1298 int qbman_swp_fq_force(struct qbman_swp *s, uint32_t fqid)
1300 return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_FORCE);
1303 int qbman_swp_fq_xon(struct qbman_swp *s, uint32_t fqid)
1305 return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XON);
1308 int qbman_swp_fq_xoff(struct qbman_swp *s, uint32_t fqid)
1310 return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XOFF);
1313 /**********************/
1314 /* Channel management */
1315 /**********************/
1317 struct qbman_cdan_ctrl_desc {
1325 uint8_t reserved3[48];
1329 struct qbman_cdan_ctrl_rslt {
1333 uint8_t reserved[60];
1336 /* Hide "ICD" for now as we don't use it, don't set it, and don't test it, so it
1337 * would be irresponsible to expose it.
1339 #define CODE_CDAN_WE_EN 0x1
1340 #define CODE_CDAN_WE_CTX 0x4
1342 static int qbman_swp_CDAN_set(struct qbman_swp *s, uint16_t channelid,
1343 uint8_t we_mask, uint8_t cdan_en,
1346 struct qbman_cdan_ctrl_desc *p;
1347 struct qbman_cdan_ctrl_rslt *r;
1349 /* Start the management command */
1350 p = qbman_swp_mc_start(s);
1354 /* Encode the caller-provided attributes */
1363 /* Complete the management command */
1364 r = qbman_swp_mc_complete(s, p, QBMAN_WQCHAN_CONFIGURE);
1366 pr_err("qbman: wqchan config failed, no response\n");
1370 /* Decode the outcome */
1371 QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK)
1372 != QBMAN_WQCHAN_CONFIGURE);
1374 /* Determine success or failure */
1375 if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
1376 pr_err("CDAN cQID %d failed: code = 0x%02x\n",
1377 channelid, r->rslt);
1384 int qbman_swp_CDAN_set_context(struct qbman_swp *s, uint16_t channelid,
1387 return qbman_swp_CDAN_set(s, channelid,
1392 int qbman_swp_CDAN_enable(struct qbman_swp *s, uint16_t channelid)
1394 return qbman_swp_CDAN_set(s, channelid,
1399 int qbman_swp_CDAN_disable(struct qbman_swp *s, uint16_t channelid)
1401 return qbman_swp_CDAN_set(s, channelid,
1406 int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s, uint16_t channelid,
1409 return qbman_swp_CDAN_set(s, channelid,
1410 CODE_CDAN_WE_EN | CODE_CDAN_WE_CTX,
1414 uint8_t qbman_get_dqrr_idx(const struct qbman_result *dqrr)
1416 return QBMAN_IDX_FROM_DQRR(dqrr);
1419 struct qbman_result *qbman_get_dqrr_from_idx(struct qbman_swp *s, uint8_t idx)
1421 struct qbman_result *dq;
1423 dq = qbman_cena_read(&s->sys, QBMAN_CENA_SWP_DQRR(idx));