drivers/bus/fslmc/qbman/qbman_portal.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
   4  *
   5  */
   6
   7 #include "qbman_portal.h"
   8
   9 /* QBMan portal management command codes */
  10 #define QBMAN_MC_ACQUIRE       0x30
  11 #define QBMAN_WQCHAN_CONFIGURE 0x46
  12
  13 /* CINH register offsets */
  14 #define QBMAN_CINH_SWP_EQCR_PI 0x800
  15 #define QBMAN_CINH_SWP_EQCR_CI 0x840
  16 #define QBMAN_CINH_SWP_EQAR    0x8c0
  17 #define QBMAN_CINH_SWP_DQPI    0xa00
  18 #define QBMAN_CINH_SWP_DCAP    0xac0
  19 #define QBMAN_CINH_SWP_SDQCR   0xb00
  20 #define QBMAN_CINH_SWP_RAR     0xcc0
  21 #define QBMAN_CINH_SWP_ISR     0xe00
  22 #define QBMAN_CINH_SWP_IER     0xe40
  23 #define QBMAN_CINH_SWP_ISDR    0xe80
  24 #define QBMAN_CINH_SWP_IIR     0xec0
  25 #define QBMAN_CINH_SWP_DQRR_ITR    0xa80
  26 #define QBMAN_CINH_SWP_ITPR    0xf40
  27
  28 /* CENA register offsets */
  29 #define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((uint32_t)(n) << 6))
  30 #define QBMAN_CENA_SWP_DQRR(n) (0x200 + ((uint32_t)(n) << 6))
  31 #define QBMAN_CENA_SWP_RCR(n)  (0x400 + ((uint32_t)(n) << 6))
  32 #define QBMAN_CENA_SWP_CR      0x600
  33 #define QBMAN_CENA_SWP_RR(vb)  (0x700 + ((uint32_t)(vb) >> 1))
  34 #define QBMAN_CENA_SWP_VDQCR   0x780
  35 #define QBMAN_CENA_SWP_EQCR_CI 0x840
  36
  37 /* Reverse mapping of QBMAN_CENA_SWP_DQRR() */
  38 #define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)p & 0x1ff) >> 6)
  39
  40 /* QBMan FQ management command codes */
  41 #define QBMAN_FQ_SCHEDULE       0x48
  42 #define QBMAN_FQ_FORCE          0x49
  43 #define QBMAN_FQ_XON            0x4d
  44 #define QBMAN_FQ_XOFF           0x4e
  45
  46 /*******************************/
  47 /* Pre-defined attribute codes */
  48 /*******************************/
  49
  50 #define QBMAN_RESPONSE_VERB_MASK   0x7f
  51
  52 /*************************/
  53 /* SDQCR attribute codes */
  54 /*************************/
  55 #define QB_SDQCR_FC_SHIFT   29
  56 #define QB_SDQCR_FC_MASK    0x1
  57 #define QB_SDQCR_DCT_SHIFT  24
  58 #define QB_SDQCR_DCT_MASK   0x3
  59 #define QB_SDQCR_TOK_SHIFT  16
  60 #define QB_SDQCR_TOK_MASK   0xff
  61 #define QB_SDQCR_SRC_SHIFT  0
  62 #define QB_SDQCR_SRC_MASK   0xffff
  63
  64 /* opaque token for static dequeues */
  65 #define QMAN_SDQCR_TOKEN    0xbb
  66
  67 enum qbman_sdqcr_dct {
  68         qbman_sdqcr_dct_null = 0,
  69         qbman_sdqcr_dct_prio_ics,
  70         qbman_sdqcr_dct_active_ics,
  71         qbman_sdqcr_dct_active
  72 };
  73
  74 enum qbman_sdqcr_fc {
  75         qbman_sdqcr_fc_one = 0,
  76         qbman_sdqcr_fc_up_to_3 = 1
  77 };
  78
  79 /* We need to keep track of which SWP triggered a pull command
  80  * so keep an array of portal IDs and use the token field to
  81  * be able to find the proper portal
  82  */
  83 #define MAX_QBMAN_PORTALS  64
  84 static struct qbman_swp *portal_idx_map[MAX_QBMAN_PORTALS];
  85
  86 /*********************************/
  87 /* Portal constructor/destructor */
  88 /*********************************/
  89
  90 /* Software portals should always be in the power-on state when we initialise,
  91  * due to the CCSR-based portal reset functionality that MC has.
  92  *
  93  * Erk! Turns out that QMan versions prior to 4.1 do not correctly reset DQRR
  94  * valid-bits, so we need to support a workaround where we don't trust
  95  * valid-bits when detecting new entries until any stale ring entries have been
  96  * overwritten at least once. The idea is that we read PI for the first few
  97  * entries, then switch to valid-bit after that. The trick is to clear the
  98  * bug-work-around boolean once the PI wraps around the ring for the first time.
  99  *
 100  * Note: this still carries a slight additional cost once the decrementer hits
 101  * zero.
 102  */
 103 struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
 104 {
 105         int ret;
 106         uint32_t eqcr_pi;
 107         struct qbman_swp *p = malloc(sizeof(*p));
 108
 109         if (!p)
 110                 return NULL;
 111         p->desc = *d;
 112 #ifdef QBMAN_CHECKING
 113         p->mc.check = swp_mc_can_start;
 114 #endif
 115         p->mc.valid_bit = QB_VALID_BIT;
 116         p->sdq = 0;
 117         p->sdq |= qbman_sdqcr_dct_prio_ics << QB_SDQCR_DCT_SHIFT;
 118         p->sdq |= qbman_sdqcr_fc_up_to_3 << QB_SDQCR_FC_SHIFT;
 119         p->sdq |= QMAN_SDQCR_TOKEN << QB_SDQCR_TOK_SHIFT;
 120
 121         atomic_set(&p->vdq.busy, 1);
 122         p->vdq.valid_bit = QB_VALID_BIT;
 123         p->dqrr.next_idx = 0;
 124         p->dqrr.valid_bit = QB_VALID_BIT;
 125         qman_version = p->desc.qman_version;
 126         if ((qman_version & 0xFFFF0000) < QMAN_REV_4100) {
 127                 p->dqrr.dqrr_size = 4;
 128                 p->dqrr.reset_bug = 1;
 129         } else {
 130                 p->dqrr.dqrr_size = 8;
 131                 p->dqrr.reset_bug = 0;
 132         }
 133
 134         ret = qbman_swp_sys_init(&p->sys, d, p->dqrr.dqrr_size);
 135         if (ret) {
 136                 free(p);
 137                 pr_err("qbman_swp_sys_init() failed %d\n", ret);
 138                 return NULL;
 139         }
 140         /* SDQCR needs to be initialized to 0 when no channels are
 141          * being dequeued from or else the QMan HW will indicate an
 142          * error.  The values that were calculated above will be
 143          * applied when dequeues from a specific channel are enabled.
 144          */
 145         qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_SDQCR, 0);
 146         eqcr_pi = qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_EQCR_PI);
 147         p->eqcr.pi = eqcr_pi & 0xF;
 148         p->eqcr.pi_vb = eqcr_pi & QB_VALID_BIT;
 149         p->eqcr.ci = qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_EQCR_CI) & 0xF;
 150         p->eqcr.available = QBMAN_EQCR_SIZE - qm_cyc_diff(QBMAN_EQCR_SIZE,
 151                                                 p->eqcr.ci, p->eqcr.pi);
 152
 153         portal_idx_map[p->desc.idx] = p;
 154         return p;
 155 }
 156
 157 void qbman_swp_finish(struct qbman_swp *p)
 158 {
 159 #ifdef QBMAN_CHECKING
 160         QBMAN_BUG_ON(p->mc.check != swp_mc_can_start);
 161 #endif
 162         qbman_swp_sys_finish(&p->sys);
 163         portal_idx_map[p->desc.idx] = NULL;
 164         free(p);
 165 }
 166
 167 const struct qbman_swp_desc *qbman_swp_get_desc(struct qbman_swp *p)
 168 {
 169         return &p->desc;
 170 }
 171
 172 /**************/
 173 /* Interrupts */
 174 /**************/
 175
 176 uint32_t qbman_swp_interrupt_get_vanish(struct qbman_swp *p)
 177 {
 178         return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_ISDR);
 179 }
 180
 181 void qbman_swp_interrupt_set_vanish(struct qbman_swp *p, uint32_t mask)
 182 {
 183         qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ISDR, mask);
 184 }
 185
 186 uint32_t qbman_swp_interrupt_read_status(struct qbman_swp *p)
 187 {
 188         return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_ISR);
 189 }
 190
 191 void qbman_swp_interrupt_clear_status(struct qbman_swp *p, uint32_t mask)
 192 {
 193         qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ISR, mask);
 194 }
 195
 196 uint32_t qbman_swp_dqrr_thrshld_read_status(struct qbman_swp *p)
 197 {
 198         return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_DQRR_ITR);
 199 }
 200
 201 void qbman_swp_dqrr_thrshld_write(struct qbman_swp *p, uint32_t mask)
 202 {
 203         qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_DQRR_ITR, mask);
 204 }
 205
 206 uint32_t qbman_swp_intr_timeout_read_status(struct qbman_swp *p)
 207 {
 208         return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_ITPR);
 209 }
 210
 211 void qbman_swp_intr_timeout_write(struct qbman_swp *p, uint32_t mask)
 212 {
 213         qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ITPR, mask);
 214 }
 215
 216 uint32_t qbman_swp_interrupt_get_trigger(struct qbman_swp *p)
 217 {
 218         return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_IER);
 219 }
 220
 221 void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, uint32_t mask)
 222 {
 223         qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_IER, mask);
 224 }
 225
 226 int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p)
 227 {
 228         return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_IIR);
 229 }
 230
 231 void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit)
 232 {
 233         qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_IIR, inhibit ? 0xffffffff : 0);
 234 }
 235
 236 /***********************/
 237 /* Management commands */
 238 /***********************/
 239
 240 /*
 241  * Internal code common to all types of management commands.
 242  */
 243
 244 void *qbman_swp_mc_start(struct qbman_swp *p)
 245 {
 246         void *ret;
 247 #ifdef QBMAN_CHECKING
 248         QBMAN_BUG_ON(p->mc.check != swp_mc_can_start);
 249 #endif
 250         ret = qbman_cena_write_start(&p->sys, QBMAN_CENA_SWP_CR);
 251 #ifdef QBMAN_CHECKING
 252         if (!ret)
 253                 p->mc.check = swp_mc_can_submit;
 254 #endif
 255         return ret;
 256 }
 257
 258 void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint8_t cmd_verb)
 259 {
 260         uint8_t *v = cmd;
 261 #ifdef QBMAN_CHECKING
 262         QBMAN_BUG_ON(!(p->mc.check != swp_mc_can_submit));
 263 #endif
 264         /* TBD: "|=" is going to hurt performance. Need to move as many fields
 265          * out of word zero, and for those that remain, the "OR" needs to occur
 266          * at the caller side. This debug check helps to catch cases where the
 267          * caller wants to OR but has forgotten to do so.
 268          */
 269         QBMAN_BUG_ON((*v & cmd_verb) != *v);
 270         *v = cmd_verb | p->mc.valid_bit;
 271         qbman_cena_write_complete(&p->sys, QBMAN_CENA_SWP_CR, cmd);
 272 #ifdef QBMAN_CHECKING
 273         p->mc.check = swp_mc_can_poll;
 274 #endif
 275 }
 276
 277 void *qbman_swp_mc_result(struct qbman_swp *p)
 278 {
 279         uint32_t *ret, verb;
 280 #ifdef QBMAN_CHECKING
 281         QBMAN_BUG_ON(p->mc.check != swp_mc_can_poll);
 282 #endif
 283         qbman_cena_invalidate_prefetch(&p->sys,
 284                                        QBMAN_CENA_SWP_RR(p->mc.valid_bit));
 285         ret = qbman_cena_read(&p->sys, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
 286         /* Remove the valid-bit - command completed if the rest is non-zero */
 287         verb = ret[0] & ~QB_VALID_BIT;
 288         if (!verb)
 289                 return NULL;
 290 #ifdef QBMAN_CHECKING
 291         p->mc.check = swp_mc_can_start;
 292 #endif
 293         p->mc.valid_bit ^= QB_VALID_BIT;
 294         return ret;
 295 }
 296
 297 /***********/
 298 /* Enqueue */
 299 /***********/
 300
 301 #define QB_ENQUEUE_CMD_OPTIONS_SHIFT    0
 302 enum qb_enqueue_commands {
 303         enqueue_empty = 0,
 304         enqueue_response_always = 1,
 305         enqueue_rejects_to_fq = 2
 306 };
 307
 308 #define QB_ENQUEUE_CMD_EC_OPTION_MASK        0x3
 309 #define QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT      2
 310 #define QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT 3
 311 #define QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT     4
 312 #define QB_ENQUEUE_CMD_DCA_PK_SHIFT          6
 313 #define QB_ENQUEUE_CMD_DCA_EN_SHIFT          7
 314 #define QB_ENQUEUE_CMD_NLIS_SHIFT            14
 315 #define QB_ENQUEUE_CMD_IS_NESN_SHIFT         15
 316
 317 void qbman_eq_desc_clear(struct qbman_eq_desc *d)
 318 {
 319         memset(d, 0, sizeof(*d));
 320 }
 321
 322 void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success)
 323 {
 324         d->eq.verb &= ~(1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT);
 325         if (respond_success)
 326                 d->eq.verb |= enqueue_response_always;
 327         else
 328                 d->eq.verb |= enqueue_rejects_to_fq;
 329 }
 330
 331 void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success,
 332                            uint16_t opr_id, uint16_t seqnum, int incomplete)
 333 {
 334         d->eq.verb |= 1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT;
 335         if (respond_success)
 336                 d->eq.verb |= enqueue_response_always;
 337         else
 338                 d->eq.verb |= enqueue_rejects_to_fq;
 339
 340         d->eq.orpid = opr_id;
 341         d->eq.seqnum = seqnum;
 342         if (incomplete)
 343                 d->eq.seqnum |= 1 << QB_ENQUEUE_CMD_NLIS_SHIFT;
 344         else
 345                 d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_NLIS_SHIFT);
 346 }
 347
 348 void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, uint16_t opr_id,
 349                                 uint16_t seqnum)
 350 {
 351         d->eq.verb |= 1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT;
 352         d->eq.verb &= ~QB_ENQUEUE_CMD_EC_OPTION_MASK;
 353         d->eq.orpid = opr_id;
 354         d->eq.seqnum = seqnum;
 355         d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_NLIS_SHIFT);
 356         d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_IS_NESN_SHIFT);
 357 }
 358
 359 void qbman_eq_desc_set_orp_nesn(struct qbman_eq_desc *d, uint16_t opr_id,
 360                                 uint16_t seqnum)
 361 {
 362         d->eq.verb |= 1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT;
 363         d->eq.verb &= ~QB_ENQUEUE_CMD_EC_OPTION_MASK;
 364         d->eq.orpid = opr_id;
 365         d->eq.seqnum = seqnum;
 366         d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_NLIS_SHIFT);
 367         d->eq.seqnum |= 1 << QB_ENQUEUE_CMD_IS_NESN_SHIFT;
 368 }
 369
 370 void qbman_eq_desc_set_response(struct qbman_eq_desc *d,
 371                                 dma_addr_t storage_phys,
 372                                 int stash)
 373 {
 374         d->eq.rsp_addr = storage_phys;
 375         d->eq.wae = stash;
 376 }
 377
 378 void qbman_eq_desc_set_token(struct qbman_eq_desc *d, uint8_t token)
 379 {
 380         d->eq.rspid = token;
 381 }
 382
 383 void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, uint32_t fqid)
 384 {
 385         d->eq.verb &= ~(1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT);
 386         d->eq.tgtid = fqid;
 387 }
 388
 389 void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid,
 390                           uint16_t qd_bin, uint8_t qd_prio)
 391 {
 392         d->eq.verb |= 1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT;
 393         d->eq.tgtid = qdid;
 394         d->eq.qdbin = qd_bin;
 395         d->eq.qpri = qd_prio;
 396 }
 397
 398 void qbman_eq_desc_set_eqdi(struct qbman_eq_desc *d, int enable)
 399 {
 400         if (enable)
 401                 d->eq.verb |= 1 << QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT;
 402         else
 403                 d->eq.verb &= ~(1 << QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT);
 404 }
 405
 406 void qbman_eq_desc_set_dca(struct qbman_eq_desc *d, int enable,
 407                            uint8_t dqrr_idx, int park)
 408 {
 409         if (enable) {
 410                 d->eq.dca = dqrr_idx;
 411                 if (park)
 412                         d->eq.dca |= 1 << QB_ENQUEUE_CMD_DCA_PK_SHIFT;
 413                 else
 414                         d->eq.dca &= ~(1 << QB_ENQUEUE_CMD_DCA_PK_SHIFT);
 415                 d->eq.dca |= 1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT;
 416         } else {
 417                 d->eq.dca &= ~(1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT);
 418         }
 419 }
 420
 421 #define EQAR_IDX(eqar)     ((eqar) & 0x7)
 422 #define EQAR_VB(eqar)      ((eqar) & 0x80)
 423 #define EQAR_SUCCESS(eqar) ((eqar) & 0x100)
 424
 425 static int qbman_swp_enqueue_array_mode(struct qbman_swp *s,
 426                                         const struct qbman_eq_desc *d,
 427                                         const struct qbman_fd *fd)
 428 {
 429         uint32_t *p;
 430         const uint32_t *cl = qb_cl(d);
 431         uint32_t eqar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_EQAR);
 432
 433         pr_debug("EQAR=%08x\n", eqar);
 434         if (!EQAR_SUCCESS(eqar))
 435                 return -EBUSY;
 436         p = qbman_cena_write_start_wo_shadow(&s->sys,
 437                                         QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
 438         memcpy(&p[1], &cl[1], 28);
 439         memcpy(&p[8], fd, sizeof(*fd));
 440         /* Set the verb byte, have to substitute in the valid-bit */
 441         lwsync();
 442         p[0] = cl[0] | EQAR_VB(eqar);
 443         qbman_cena_write_complete_wo_shadow(&s->sys,
 444                                         QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
 445         return 0;
 446 }
 447
 448 static int qbman_swp_enqueue_ring_mode(struct qbman_swp *s,
 449                                        const struct qbman_eq_desc *d,
 450                                        const struct qbman_fd *fd)
 451 {
 452         uint32_t *p;
 453         const uint32_t *cl = qb_cl(d);
 454         uint32_t eqcr_ci;
 455         uint8_t diff;
 456
 457         if (!s->eqcr.available) {
 458                 eqcr_ci = s->eqcr.ci;
 459                 s->eqcr.ci = qbman_cena_read_reg(&s->sys,
 460                                 QBMAN_CENA_SWP_EQCR_CI) & 0xF;
 461                 diff = qm_cyc_diff(QBMAN_EQCR_SIZE,
 462                                    eqcr_ci, s->eqcr.ci);
 463                 s->eqcr.available += diff;
 464                 if (!diff)
 465                         return -EBUSY;
 466         }
 467
 468         p = qbman_cena_write_start_wo_shadow(&s->sys,
 469                                         QBMAN_CENA_SWP_EQCR(s->eqcr.pi & 7));
 470         memcpy(&p[1], &cl[1], 28);
 471         memcpy(&p[8], fd, sizeof(*fd));
 472         lwsync();
 473
 474         /* Set the verb byte, have to substitute in the valid-bit */
 475         p[0] = cl[0] | s->eqcr.pi_vb;
 476         qbman_cena_write_complete_wo_shadow(&s->sys,
 477                                         QBMAN_CENA_SWP_EQCR(s->eqcr.pi & 7));
 478         s->eqcr.pi++;
 479         s->eqcr.pi &= 0xF;
 480         s->eqcr.available--;
 481         if (!(s->eqcr.pi & 7))
 482                 s->eqcr.pi_vb ^= QB_VALID_BIT;
 483
 484         return 0;
 485 }
 486
 487 int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,
 488                       const struct qbman_fd *fd)
 489 {
 490         if (s->sys.eqcr_mode == qman_eqcr_vb_array)
 491                 return qbman_swp_enqueue_array_mode(s, d, fd);
 492         else    /* Use ring mode by default */
 493                 return qbman_swp_enqueue_ring_mode(s, d, fd);
 494 }
 495
 496 int qbman_swp_enqueue_multiple(struct qbman_swp *s,
 497                                const struct qbman_eq_desc *d,
 498                                const struct qbman_fd *fd,
 499                                int num_frames)
 500 {
 501         uint32_t *p;
 502         const uint32_t *cl = qb_cl(d);
 503         uint32_t eqcr_ci, eqcr_pi;
 504         uint8_t diff;
 505         int i, num_enqueued = 0;
 506         uint64_t addr_cena;
 507
 508         if (!s->eqcr.available) {
 509                 eqcr_ci = s->eqcr.ci;
 510                 s->eqcr.ci = qbman_cena_read_reg(&s->sys,
 511                                 QBMAN_CENA_SWP_EQCR_CI) & 0xF;
 512                 diff = qm_cyc_diff(QBMAN_EQCR_SIZE,
 513                                    eqcr_ci, s->eqcr.ci);
 514                 s->eqcr.available += diff;
 515                 if (!diff)
 516                         return 0;
 517         }
 518
 519         eqcr_pi = s->eqcr.pi;
 520         num_enqueued = (s->eqcr.available < num_frames) ?
 521                         s->eqcr.available : num_frames;
 522         s->eqcr.available -= num_enqueued;
 523         /* Fill in the EQCR ring */
 524         for (i = 0; i < num_enqueued; i++) {
 525                 p = qbman_cena_write_start_wo_shadow(&s->sys,
 526                                         QBMAN_CENA_SWP_EQCR(eqcr_pi & 7));
 527                 memcpy(&p[1], &cl[1], 28);
 528                 memcpy(&p[8], &fd[i], sizeof(*fd));
 529                 eqcr_pi++;
 530                 eqcr_pi &= 0xF;
 531         }
 532
 533         lwsync();
 534
 535         /* Set the verb byte, have to substitute in the valid-bit */
 536         eqcr_pi = s->eqcr.pi;
 537         for (i = 0; i < num_enqueued; i++) {
 538                 p = qbman_cena_write_start_wo_shadow(&s->sys,
 539                                         QBMAN_CENA_SWP_EQCR(eqcr_pi & 7));
 540                 p[0] = cl[0] | s->eqcr.pi_vb;
 541                 eqcr_pi++;
 542                 eqcr_pi &= 0xF;
 543                 if (!(eqcr_pi & 7))
 544                         s->eqcr.pi_vb ^= QB_VALID_BIT;
 545         }
 546
 547         /* Flush all the cacheline without load/store in between */
 548         eqcr_pi = s->eqcr.pi;
 549         addr_cena = (uint64_t)s->sys.addr_cena;
 550         for (i = 0; i < num_enqueued; i++) {
 551                 dcbf((uint64_t *)(addr_cena +
 552                                 QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
 553                 eqcr_pi++;
 554                 eqcr_pi &= 0xF;
 555         }
 556         s->eqcr.pi = eqcr_pi;
 557
 558         return num_enqueued;
 559 }
 560
 561 int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s,
 562                                     const struct qbman_eq_desc *d,
 563                                     const struct qbman_fd *fd,
 564                                     int num_frames)
 565 {
 566         uint32_t *p;
 567         const uint32_t *cl;
 568         uint32_t eqcr_ci, eqcr_pi;
 569         uint8_t diff;
 570         int i, num_enqueued = 0;
 571         uint64_t addr_cena;
 572
 573         if (!s->eqcr.available) {
 574                 eqcr_ci = s->eqcr.ci;
 575                 s->eqcr.ci = qbman_cena_read_reg(&s->sys,
 576                                 QBMAN_CENA_SWP_EQCR_CI) & 0xF;
 577                 diff = qm_cyc_diff(QBMAN_EQCR_SIZE,
 578                                    eqcr_ci, s->eqcr.ci);
 579                 s->eqcr.available += diff;
 580                 if (!diff)
 581                         return 0;
 582         }
 583
 584         eqcr_pi = s->eqcr.pi;
 585         num_enqueued = (s->eqcr.available < num_frames) ?
 586                         s->eqcr.available : num_frames;
 587         s->eqcr.available -= num_enqueued;
 588         /* Fill in the EQCR ring */
 589         for (i = 0; i < num_enqueued; i++) {
 590                 p = qbman_cena_write_start_wo_shadow(&s->sys,
 591                                         QBMAN_CENA_SWP_EQCR(eqcr_pi & 7));
 592                 cl = qb_cl(&d[i]);
 593                 memcpy(&p[1], &cl[1], 28);
 594                 memcpy(&p[8], &fd[i], sizeof(*fd));
 595                 eqcr_pi++;
 596                 eqcr_pi &= 0xF;
 597         }
 598
 599         lwsync();
 600
 601         /* Set the verb byte, have to substitute in the valid-bit */
 602         eqcr_pi = s->eqcr.pi;
 603         for (i = 0; i < num_enqueued; i++) {
 604                 p = qbman_cena_write_start_wo_shadow(&s->sys,
 605                                         QBMAN_CENA_SWP_EQCR(eqcr_pi & 7));
 606                 cl = qb_cl(&d[i]);
 607                 p[0] = cl[0] | s->eqcr.pi_vb;
 608                 eqcr_pi++;
 609                 eqcr_pi &= 0xF;
 610                 if (!(eqcr_pi & 7))
 611                         s->eqcr.pi_vb ^= QB_VALID_BIT;
 612         }
 613
 614         /* Flush all the cacheline without load/store in between */
 615         eqcr_pi = s->eqcr.pi;
 616         addr_cena = (uint64_t)s->sys.addr_cena;
 617         for (i = 0; i < num_enqueued; i++) {
 618                 dcbf((uint64_t *)(addr_cena +
 619                                 QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
 620                 eqcr_pi++;
 621                 eqcr_pi &= 0xF;
 622         }
 623         s->eqcr.pi = eqcr_pi;
 624
 625         return num_enqueued;
 626 }
 627
 628 /*************************/
 629 /* Static (push) dequeue */
 630 /*************************/
 631
 632 void qbman_swp_push_get(struct qbman_swp *s, uint8_t channel_idx, int *enabled)
 633 {
 634         uint16_t src = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
 635
 636         QBMAN_BUG_ON(channel_idx > 15);
 637         *enabled = src | (1 << channel_idx);
 638 }
 639
 640 void qbman_swp_push_set(struct qbman_swp *s, uint8_t channel_idx, int enable)
 641 {
 642         uint16_t dqsrc;
 643
 644         QBMAN_BUG_ON(channel_idx > 15);
 645         if (enable)
 646                 s->sdq |= 1 << channel_idx;
 647         else
 648                 s->sdq &= ~(1 << channel_idx);
 649
 650         /* Read make the complete src map.  If no channels are enabled
 651          * the SDQCR must be 0 or else QMan will assert errors
 652          */
 653         dqsrc = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
 654         if (dqsrc != 0)
 655                 qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_SDQCR, s->sdq);
 656         else
 657                 qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_SDQCR, 0);
 658 }
 659
 660 /***************************/
 661 /* Volatile (pull) dequeue */
 662 /***************************/
 663
 664 /* These should be const, eventually */
 665 #define QB_VDQCR_VERB_DCT_SHIFT    0
 666 #define QB_VDQCR_VERB_DT_SHIFT     2
 667 #define QB_VDQCR_VERB_RLS_SHIFT    4
 668 #define QB_VDQCR_VERB_WAE_SHIFT    5
 669
 670 enum qb_pull_dt_e {
 671         qb_pull_dt_channel,
 672         qb_pull_dt_workqueue,
 673         qb_pull_dt_framequeue
 674 };
 675
 676 void qbman_pull_desc_clear(struct qbman_pull_desc *d)
 677 {
 678         memset(d, 0, sizeof(*d));
 679 }
 680
 681 void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
 682                                  struct qbman_result *storage,
 683                                  dma_addr_t storage_phys,
 684                                  int stash)
 685 {
 686         d->pull.rsp_addr_virt = (uint64_t)storage;
 687
 688         if (!storage) {
 689                 d->pull.verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT);
 690                 return;
 691         }
 692         d->pull.verb |= 1 << QB_VDQCR_VERB_RLS_SHIFT;
 693         if (stash)
 694                 d->pull.verb |= 1 << QB_VDQCR_VERB_WAE_SHIFT;
 695         else
 696                 d->pull.verb &= ~(1 << QB_VDQCR_VERB_WAE_SHIFT);
 697
 698         d->pull.rsp_addr = storage_phys;
 699 }
 700
 701 void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, uint8_t numframes)
 702 {
 703         d->pull.numf = numframes - 1;
 704 }
 705
 706 void qbman_pull_desc_set_token(struct qbman_pull_desc *d, uint8_t token)
 707 {
 708         d->pull.tok = token;
 709 }
 710
 711 void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, uint32_t fqid)
 712 {
 713         d->pull.verb |= 1 << QB_VDQCR_VERB_DCT_SHIFT;
 714         d->pull.verb |= qb_pull_dt_framequeue << QB_VDQCR_VERB_DT_SHIFT;
 715         d->pull.dq_src = fqid;
 716 }
 717
 718 void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, uint32_t wqid,
 719                             enum qbman_pull_type_e dct)
 720 {
 721         d->pull.verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
 722         d->pull.verb |= qb_pull_dt_workqueue << QB_VDQCR_VERB_DT_SHIFT;
 723         d->pull.dq_src = wqid;
 724 }
 725
 726 void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, uint32_t chid,
 727                                  enum qbman_pull_type_e dct)
 728 {
 729         d->pull.verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
 730         d->pull.verb |= qb_pull_dt_channel << QB_VDQCR_VERB_DT_SHIFT;
 731         d->pull.dq_src = chid;
 732 }
 733
 734 int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d)
 735 {
 736         uint32_t *p;
 737         uint32_t *cl = qb_cl(d);
 738
 739         if (!atomic_dec_and_test(&s->vdq.busy)) {
 740                 atomic_inc(&s->vdq.busy);
 741                 return -EBUSY;
 742         }
 743
 744         d->pull.tok = s->sys.idx + 1;
 745         s->vdq.storage = (void *)d->pull.rsp_addr_virt;
 746         p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR);
 747         memcpy(&p[1], &cl[1], 12);
 748
 749         /* Set the verb byte, have to substitute in the valid-bit */
 750         lwsync();
 751         p[0] = cl[0] | s->vdq.valid_bit;
 752         s->vdq.valid_bit ^= QB_VALID_BIT;
 753         qbman_cena_write_complete_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR);
 754
 755         return 0;
 756 }
 757
 758 /****************/
 759 /* Polling DQRR */
 760 /****************/
 761
 762 #define QMAN_DQRR_PI_MASK              0xf
 763
 764 #define QBMAN_RESULT_DQ        0x60
 765 #define QBMAN_RESULT_FQRN      0x21
 766 #define QBMAN_RESULT_FQRNI     0x22
 767 #define QBMAN_RESULT_FQPN      0x24
 768 #define QBMAN_RESULT_FQDAN     0x25
 769 #define QBMAN_RESULT_CDAN      0x26
 770 #define QBMAN_RESULT_CSCN_MEM  0x27
 771 #define QBMAN_RESULT_CGCU      0x28
 772 #define QBMAN_RESULT_BPSCN     0x29
 773 #define QBMAN_RESULT_CSCN_WQ   0x2a
 774
 775 /* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry
 776  * only once, so repeated calls can return a sequence of DQRR entries, without
 777  * requiring they be consumed immediately or in any particular order.
 778  */
 779 const struct qbman_result *qbman_swp_dqrr_next(struct qbman_swp *s)
 780 {
 781         uint32_t verb;
 782         uint32_t response_verb;
 783         uint32_t flags;
 784         const struct qbman_result *p;
 785
 786         /* Before using valid-bit to detect if something is there, we have to
 787          * handle the case of the DQRR reset bug...
 788          */
 789         if (unlikely(s->dqrr.reset_bug)) {
 790                 /* We pick up new entries by cache-inhibited producer index,
 791                  * which means that a non-coherent mapping would require us to
 792                  * invalidate and read *only* once that PI has indicated that
 793                  * there's an entry here. The first trip around the DQRR ring
 794                  * will be much less efficient than all subsequent trips around
 795                  * it...
 796                  */
 797                 uint8_t pi = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_DQPI) &
 798                              QMAN_DQRR_PI_MASK;
 799
 800                 /* there are new entries if pi != next_idx */
 801                 if (pi == s->dqrr.next_idx)
 802                         return NULL;
 803
 804                 /* if next_idx is/was the last ring index, and 'pi' is
 805                  * different, we can disable the workaround as all the ring
 806                  * entries have now been DMA'd to so valid-bit checking is
 807                  * repaired. Note: this logic needs to be based on next_idx
 808                  * (which increments one at a time), rather than on pi (which
 809                  * can burst and wrap-around between our snapshots of it).
 810                  */
 811                 QBMAN_BUG_ON((s->dqrr.dqrr_size - 1) < 0);
 812                 if (s->dqrr.next_idx == (s->dqrr.dqrr_size - 1u)) {
 813                         pr_debug("DEBUG: next_idx=%d, pi=%d, clear reset bug\n",
 814                                  s->dqrr.next_idx, pi);
 815                         s->dqrr.reset_bug = 0;
 816                 }
 817                 qbman_cena_invalidate_prefetch(&s->sys,
 818                                         QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
 819         }
 820         p = qbman_cena_read_wo_shadow(&s->sys,
 821                                       QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
 822         verb = p->dq.verb;
 823
 824         /* If the valid-bit isn't of the expected polarity, nothing there. Note,
 825          * in the DQRR reset bug workaround, we shouldn't need to skip these
 826          * check, because we've already determined that a new entry is available
 827          * and we've invalidated the cacheline before reading it, so the
 828          * valid-bit behaviour is repaired and should tell us what we already
 829          * knew from reading PI.
 830          */
 831         if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit)
 832                 return NULL;
 833
 834         /* There's something there. Move "next_idx" attention to the next ring
 835          * entry (and prefetch it) before returning what we found.
 836          */
 837         s->dqrr.next_idx++;
 838         if (s->dqrr.next_idx == s->dqrr.dqrr_size) {
 839                 s->dqrr.next_idx = 0;
 840                 s->dqrr.valid_bit ^= QB_VALID_BIT;
 841         }
 842         /* If this is the final response to a volatile dequeue command
 843          * indicate that the vdq is no longer busy
 844          */
 845         flags = p->dq.stat;
 846         response_verb = verb & QBMAN_RESPONSE_VERB_MASK;
 847         if ((response_verb == QBMAN_RESULT_DQ) &&
 848             (flags & QBMAN_DQ_STAT_VOLATILE) &&
 849             (flags & QBMAN_DQ_STAT_EXPIRED))
 850                 atomic_inc(&s->vdq.busy);
 851
 852         return p;
 853 }
 854
 855 /* Consume DQRR entries previously returned from qbman_swp_dqrr_next(). */
 856 void qbman_swp_dqrr_consume(struct qbman_swp *s,
 857                             const struct qbman_result *dq)
 858 {
 859         qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq));
 860 }
 861
 862 /*********************************/
 863 /* Polling user-provided storage */
 864 /*********************************/
 865 int qbman_result_has_new_result(struct qbman_swp *s,
 866                                 struct qbman_result *dq)
 867 {
 868         if (dq->dq.tok == 0)
 869                 return 0;
 870
 871         /*
 872          * Set token to be 0 so we will detect change back to 1
 873          * next time the looping is traversed. Const is cast away here
 874          * as we want users to treat the dequeue responses as read only.
 875          */
 876         ((struct qbman_result *)dq)->dq.tok = 0;
 877
 878         /*
 879          * VDQCR "no longer busy" hook - not quite the same as DQRR, because the
 880          * fact "VDQCR" shows busy doesn't mean that we hold the result that
 881          * makes it available. Eg. we may be looking at our 10th dequeue result,
 882          * having released VDQCR after the 1st result and it is now busy due to
 883          * some other command!
 884          */
 885         if (s->vdq.storage == dq) {
 886                 s->vdq.storage = NULL;
 887                 atomic_inc(&s->vdq.busy);
 888         }
 889
 890         return 1;
 891 }
 892
 893 int qbman_check_new_result(struct qbman_result *dq)
 894 {
 895         if (dq->dq.tok == 0)
 896                 return 0;
 897
 898         /*
 899          * Set token to be 0 so we will detect change back to 1
 900          * next time the looping is traversed. Const is cast away here
 901          * as we want users to treat the dequeue responses as read only.
 902          */
 903         ((struct qbman_result *)dq)->dq.tok = 0;
 904
 905         return 1;
 906 }
 907
 908 int qbman_check_command_complete(struct qbman_result *dq)
 909 {
 910         struct qbman_swp *s;
 911
 912         if (dq->dq.tok == 0)
 913                 return 0;
 914
 915         s = portal_idx_map[dq->dq.tok - 1];
 916         /*
 917          * VDQCR "no longer busy" hook - not quite the same as DQRR, because the
 918          * fact "VDQCR" shows busy doesn't mean that we hold the result that
 919          * makes it available. Eg. we may be looking at our 10th dequeue result,
 920          * having released VDQCR after the 1st result and it is now busy due to
 921          * some other command!
 922          */
 923         if (s->vdq.storage == dq) {
 924                 s->vdq.storage = NULL;
 925                 atomic_inc(&s->vdq.busy);
 926         }
 927
 928         return 1;
 929 }
 930
 931 /********************************/
 932 /* Categorising qbman results   */
 933 /********************************/
 934
 935 static inline int __qbman_result_is_x(const struct qbman_result *dq,
 936                                       uint8_t x)
 937 {
 938         uint8_t response_verb = dq->dq.verb & QBMAN_RESPONSE_VERB_MASK;
 939
 940         return (response_verb == x);
 941 }
 942
 943 int qbman_result_is_DQ(const struct qbman_result *dq)
 944 {
 945         return __qbman_result_is_x(dq, QBMAN_RESULT_DQ);
 946 }
 947
 948 int qbman_result_is_FQDAN(const struct qbman_result *dq)
 949 {
 950         return __qbman_result_is_x(dq, QBMAN_RESULT_FQDAN);
 951 }
 952
 953 int qbman_result_is_CDAN(const struct qbman_result *dq)
 954 {
 955         return __qbman_result_is_x(dq, QBMAN_RESULT_CDAN);
 956 }
 957
 958 int qbman_result_is_CSCN(const struct qbman_result *dq)
 959 {
 960         return __qbman_result_is_x(dq, QBMAN_RESULT_CSCN_MEM) ||
 961                 __qbman_result_is_x(dq, QBMAN_RESULT_CSCN_WQ);
 962 }
 963
 964 int qbman_result_is_BPSCN(const struct qbman_result *dq)
 965 {
 966         return __qbman_result_is_x(dq, QBMAN_RESULT_BPSCN);
 967 }
 968
 969 int qbman_result_is_CGCU(const struct qbman_result *dq)
 970 {
 971         return __qbman_result_is_x(dq, QBMAN_RESULT_CGCU);
 972 }
 973
 974 int qbman_result_is_FQRN(const struct qbman_result *dq)
 975 {
 976         return __qbman_result_is_x(dq, QBMAN_RESULT_FQRN);
 977 }
 978
 979 int qbman_result_is_FQRNI(const struct qbman_result *dq)
 980 {
 981         return __qbman_result_is_x(dq, QBMAN_RESULT_FQRNI);
 982 }
 983
 984 int qbman_result_is_FQPN(const struct qbman_result *dq)
 985 {
 986         return __qbman_result_is_x(dq, QBMAN_RESULT_FQPN);
 987 }
 988
 989 /*********************************/
 990 /* Parsing frame dequeue results */
 991 /*********************************/
 992
 993 /* These APIs assume qbman_result_is_DQ() is TRUE */
 994
 995 uint8_t qbman_result_DQ_flags(const struct qbman_result *dq)
 996 {
 997         return dq->dq.stat;
 998 }
 999
1000 uint16_t qbman_result_DQ_seqnum(const struct qbman_result *dq)
1001 {
1002         return dq->dq.seqnum;
1003 }
1004
1005 uint16_t qbman_result_DQ_odpid(const struct qbman_result *dq)
1006 {
1007         return dq->dq.oprid;
1008 }
1009
1010 uint32_t qbman_result_DQ_fqid(const struct qbman_result *dq)
1011 {
1012         return dq->dq.fqid;
1013 }
1014
1015 uint32_t qbman_result_DQ_byte_count(const struct qbman_result *dq)
1016 {
1017         return dq->dq.fq_byte_cnt;
1018 }
1019
1020 uint32_t qbman_result_DQ_frame_count(const struct qbman_result *dq)
1021 {
1022         return dq->dq.fq_frm_cnt;
1023 }
1024
1025 uint64_t qbman_result_DQ_fqd_ctx(const struct qbman_result *dq)
1026 {
1027         return dq->dq.fqd_ctx;
1028 }
1029
1030 const struct qbman_fd *qbman_result_DQ_fd(const struct qbman_result *dq)
1031 {
1032         return (const struct qbman_fd *)&dq->dq.fd[0];
1033 }
1034
1035 /**************************************/
1036 /* Parsing state-change notifications */
1037 /**************************************/
1038 uint8_t qbman_result_SCN_state(const struct qbman_result *scn)
1039 {
1040         return scn->scn.state;
1041 }
1042
1043 uint32_t qbman_result_SCN_rid(const struct qbman_result *scn)
1044 {
1045         return scn->scn.rid_tok;
1046 }
1047
1048 uint64_t qbman_result_SCN_ctx(const struct qbman_result *scn)
1049 {
1050         return scn->scn.ctx;
1051 }
1052
1053 /*****************/
1054 /* Parsing BPSCN */
1055 /*****************/
1056 uint16_t qbman_result_bpscn_bpid(const struct qbman_result *scn)
1057 {
1058         return (uint16_t)qbman_result_SCN_rid(scn) & 0x3FFF;
1059 }
1060
1061 int qbman_result_bpscn_has_free_bufs(const struct qbman_result *scn)
1062 {
1063         return !(int)(qbman_result_SCN_state(scn) & 0x1);
1064 }
1065
1066 int qbman_result_bpscn_is_depleted(const struct qbman_result *scn)
1067 {
1068         return (int)(qbman_result_SCN_state(scn) & 0x2);
1069 }
1070
1071 int qbman_result_bpscn_is_surplus(const struct qbman_result *scn)
1072 {
1073         return (int)(qbman_result_SCN_state(scn) & 0x4);
1074 }
1075
1076 uint64_t qbman_result_bpscn_ctx(const struct qbman_result *scn)
1077 {
1078         return qbman_result_SCN_ctx(scn);
1079 }
1080
1081 /*****************/
1082 /* Parsing CGCU  */
1083 /*****************/
1084 uint16_t qbman_result_cgcu_cgid(const struct qbman_result *scn)
1085 {
1086         return (uint16_t)qbman_result_SCN_rid(scn) & 0xFFFF;
1087 }
1088
1089 uint64_t qbman_result_cgcu_icnt(const struct qbman_result *scn)
1090 {
1091         return qbman_result_SCN_ctx(scn);
1092 }
1093
1094 /******************/
1095 /* Buffer release */
1096 /******************/
1097 #define QB_BR_RC_VALID_SHIFT  5
1098 #define QB_BR_RCDI_SHIFT      6
1099
1100 void qbman_release_desc_clear(struct qbman_release_desc *d)
1101 {
1102         memset(d, 0, sizeof(*d));
1103         d->br.verb = 1 << QB_BR_RC_VALID_SHIFT;
1104 }
1105
1106 void qbman_release_desc_set_bpid(struct qbman_release_desc *d, uint16_t bpid)
1107 {
1108         d->br.bpid = bpid;
1109 }
1110
1111 void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable)
1112 {
1113         if (enable)
1114                 d->br.verb |= 1 << QB_BR_RCDI_SHIFT;
1115         else
1116                 d->br.verb &= ~(1 << QB_BR_RCDI_SHIFT);
1117 }
1118
1119 #define RAR_IDX(rar)     ((rar) & 0x7)
1120 #define RAR_VB(rar)      ((rar) & 0x80)
1121 #define RAR_SUCCESS(rar) ((rar) & 0x100)
1122
1123 int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
1124                       const uint64_t *buffers, unsigned int num_buffers)
1125 {
1126         uint32_t *p;
1127         const uint32_t *cl = qb_cl(d);
1128         uint32_t rar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_RAR);
1129
1130         pr_debug("RAR=%08x\n", rar);
1131         if (!RAR_SUCCESS(rar))
1132                 return -EBUSY;
1133
1134         QBMAN_BUG_ON(!num_buffers || (num_buffers > 7));
1135
1136         /* Start the release command */
1137         p = qbman_cena_write_start_wo_shadow(&s->sys,
1138                                              QBMAN_CENA_SWP_RCR(RAR_IDX(rar)));
1139
1140         /* Copy the caller's buffer pointers to the command */
1141         u64_to_le32_copy(&p[2], buffers, num_buffers);
1142
1143         /* Set the verb byte, have to substitute in the valid-bit and the number
1144          * of buffers.
1145          */
1146         lwsync();
1147         p[0] = cl[0] | RAR_VB(rar) | num_buffers;
1148         qbman_cena_write_complete_wo_shadow(&s->sys,
1149                                             QBMAN_CENA_SWP_RCR(RAR_IDX(rar)));
1150
1151         return 0;
1152 }
1153
1154 /*******************/
1155 /* Buffer acquires */
1156 /*******************/
1157 struct qbman_acquire_desc {
1158         uint8_t verb;
1159         uint8_t reserved;
1160         uint16_t bpid;
1161         uint8_t num;
1162         uint8_t reserved2[59];
1163 };
1164
1165 struct qbman_acquire_rslt {
1166         uint8_t verb;
1167         uint8_t rslt;
1168         uint16_t reserved;
1169         uint8_t num;
1170         uint8_t reserved2[3];
1171         uint64_t buf[7];
1172 };
1173
1174 int qbman_swp_acquire(struct qbman_swp *s, uint16_t bpid, uint64_t *buffers,
1175                       unsigned int num_buffers)
1176 {
1177         struct qbman_acquire_desc *p;
1178         struct qbman_acquire_rslt *r;
1179
1180         if (!num_buffers || (num_buffers > 7))
1181                 return -EINVAL;
1182
1183         /* Start the management command */
1184         p = qbman_swp_mc_start(s);
1185
1186         if (!p)
1187                 return -EBUSY;
1188
1189         /* Encode the caller-provided attributes */
1190         p->bpid = bpid;
1191         p->num = num_buffers;
1192
1193         /* Complete the management command */
1194         r = qbman_swp_mc_complete(s, p, QBMAN_MC_ACQUIRE);
1195         if (unlikely(!r)) {
1196                 pr_err("qbman: acquire from BPID %d failed, no response\n",
1197                        bpid);
1198                 return -EIO;
1199         }
1200
1201         /* Decode the outcome */
1202         QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != QBMAN_MC_ACQUIRE);
1203
1204         /* Determine success or failure */
1205         if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
1206                 pr_err("Acquire buffers from BPID 0x%x failed, code=0x%02x\n",
1207                        bpid, r->rslt);
1208                 return -EIO;
1209         }
1210
1211         QBMAN_BUG_ON(r->num > num_buffers);
1212
1213         /* Copy the acquired buffers to the caller's array */
1214         u64_from_le32_copy(buffers, &r->buf[0], r->num);
1215
1216         return (int)r->num;
1217 }
1218
1219 /*****************/
1220 /* FQ management */
1221 /*****************/
1222 struct qbman_alt_fq_state_desc {
1223         uint8_t verb;
1224         uint8_t reserved[3];
1225         uint32_t fqid;
1226         uint8_t reserved2[56];
1227 };
1228
1229 struct qbman_alt_fq_state_rslt {
1230         uint8_t verb;
1231         uint8_t rslt;
1232         uint8_t reserved[62];
1233 };
1234
1235 #define ALT_FQ_FQID_MASK 0x00FFFFFF
1236
1237 static int qbman_swp_alt_fq_state(struct qbman_swp *s, uint32_t fqid,
1238                                   uint8_t alt_fq_verb)
1239 {
1240         struct qbman_alt_fq_state_desc *p;
1241         struct qbman_alt_fq_state_rslt *r;
1242
1243         /* Start the management command */
1244         p = qbman_swp_mc_start(s);
1245         if (!p)
1246                 return -EBUSY;
1247
1248         p->fqid = fqid & ALT_FQ_FQID_MASK;
1249
1250         /* Complete the management command */
1251         r = qbman_swp_mc_complete(s, p, alt_fq_verb);
1252         if (unlikely(!r)) {
1253                 pr_err("qbman: mgmt cmd failed, no response (verb=0x%x)\n",
1254                        alt_fq_verb);
1255                 return -EIO;
1256         }
1257
1258         /* Decode the outcome */
1259         QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != alt_fq_verb);
1260
1261         /* Determine success or failure */
1262         if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
1263                 pr_err("ALT FQID %d failed: verb = 0x%08x, code = 0x%02x\n",
1264                        fqid, alt_fq_verb, r->rslt);
1265                 return -EIO;
1266         }
1267
1268         return 0;
1269 }
1270
1271 int qbman_swp_fq_schedule(struct qbman_swp *s, uint32_t fqid)
1272 {
1273         return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_SCHEDULE);
1274 }
1275
1276 int qbman_swp_fq_force(struct qbman_swp *s, uint32_t fqid)
1277 {
1278         return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_FORCE);
1279 }
1280
1281 int qbman_swp_fq_xon(struct qbman_swp *s, uint32_t fqid)
1282 {
1283         return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XON);
1284 }
1285
1286 int qbman_swp_fq_xoff(struct qbman_swp *s, uint32_t fqid)
1287 {
1288         return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XOFF);
1289 }
1290
1291 /**********************/
1292 /* Channel management */
1293 /**********************/
1294
1295 struct qbman_cdan_ctrl_desc {
1296         uint8_t verb;
1297         uint8_t reserved;
1298         uint16_t ch;
1299         uint8_t we;
1300         uint8_t ctrl;
1301         uint16_t reserved2;
1302         uint64_t cdan_ctx;
1303         uint8_t reserved3[48];
1304
1305 };
1306
1307 struct qbman_cdan_ctrl_rslt {
1308         uint8_t verb;
1309         uint8_t rslt;
1310         uint16_t ch;
1311         uint8_t reserved[60];
1312 };
1313
1314 /* Hide "ICD" for now as we don't use it, don't set it, and don't test it, so it
1315  * would be irresponsible to expose it.
1316  */
1317 #define CODE_CDAN_WE_EN    0x1
1318 #define CODE_CDAN_WE_CTX   0x4
1319
1320 static int qbman_swp_CDAN_set(struct qbman_swp *s, uint16_t channelid,
1321                               uint8_t we_mask, uint8_t cdan_en,
1322                               uint64_t ctx)
1323 {
1324         struct qbman_cdan_ctrl_desc *p;
1325         struct qbman_cdan_ctrl_rslt *r;
1326
1327         /* Start the management command */
1328         p = qbman_swp_mc_start(s);
1329         if (!p)
1330                 return -EBUSY;
1331
1332         /* Encode the caller-provided attributes */
1333         p->ch = channelid;
1334         p->we = we_mask;
1335         if (cdan_en)
1336                 p->ctrl = 1;
1337         else
1338                 p->ctrl = 0;
1339         p->cdan_ctx = ctx;
1340
1341         /* Complete the management command */
1342         r = qbman_swp_mc_complete(s, p, QBMAN_WQCHAN_CONFIGURE);
1343         if (unlikely(!r)) {
1344                 pr_err("qbman: wqchan config failed, no response\n");
1345                 return -EIO;
1346         }
1347
1348         /* Decode the outcome */
1349         QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK)
1350                      != QBMAN_WQCHAN_CONFIGURE);
1351
1352         /* Determine success or failure */
1353         if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
1354                 pr_err("CDAN cQID %d failed: code = 0x%02x\n",
1355                        channelid, r->rslt);
1356                 return -EIO;
1357         }
1358
1359         return 0;
1360 }
1361
1362 int qbman_swp_CDAN_set_context(struct qbman_swp *s, uint16_t channelid,
1363                                uint64_t ctx)
1364 {
1365         return qbman_swp_CDAN_set(s, channelid,
1366                                   CODE_CDAN_WE_CTX,
1367                                   0, ctx);
1368 }
1369
1370 int qbman_swp_CDAN_enable(struct qbman_swp *s, uint16_t channelid)
1371 {
1372         return qbman_swp_CDAN_set(s, channelid,
1373                                   CODE_CDAN_WE_EN,
1374                                   1, 0);
1375 }
1376
1377 int qbman_swp_CDAN_disable(struct qbman_swp *s, uint16_t channelid)
1378 {
1379         return qbman_swp_CDAN_set(s, channelid,
1380                                   CODE_CDAN_WE_EN,
1381                                   0, 0);
1382 }
1383
1384 int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s, uint16_t channelid,
1385                                       uint64_t ctx)
1386 {
1387         return qbman_swp_CDAN_set(s, channelid,
1388                                   CODE_CDAN_WE_EN | CODE_CDAN_WE_CTX,
1389                                   1, ctx);
1390 }
1391
1392 uint8_t qbman_get_dqrr_idx(const struct qbman_result *dqrr)
1393 {
1394         return QBMAN_IDX_FROM_DQRR(dqrr);
1395 }
1396
1397 struct qbman_result *qbman_get_dqrr_from_idx(struct qbman_swp *s, uint8_t idx)
1398 {
1399         struct qbman_result *dq;
1400
1401         dq = qbman_cena_read(&s->sys, QBMAN_CENA_SWP_DQRR(idx));
1402         return dq;
1403 }