1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
6 /* qbman_sys_decl.h and qbman_sys.h are the two platform-specific files in the
7 * driver. They are only included via qbman_private.h, which is itself a
8 * platform-independent file and is included by all the other driver source.
10 * qbman_sys_decl.h is included prior to all other declarations and logic, and
11 * it exists to provide compatibility with any linux interfaces our
12 * single-source driver code is dependent on (eg. kmalloc). Ie. this file
13 * provides linux compatibility.
15 * This qbman_sys.h header, on the other hand, is included *after* any common
16 * and platform-neutral declarations and logic in qbman_private.h, and exists to
17 * implement any platform-specific logic of the qbman driver itself. Ie. it is
18 * *not* to provide linux compatibility.
21 #include "qbman_sys_decl.h"
23 #define CENA_WRITE_ENABLE 0
24 #define CINH_WRITE_ENABLE 1
26 /* Debugging assists */
27 static inline void __hexdump(unsigned long start, unsigned long end,
28 unsigned long p, size_t sz, const unsigned char *c)
35 pos += sprintf(buf + pos, "%08lx: ", start);
37 if ((start < p) || (start >= (p + sz)))
38 pos += sprintf(buf + pos, "..");
40 pos += sprintf(buf + pos, "%02x", *(c++));
41 if (!(++start & 15)) {
59 static inline void hexdump(const void *ptr, size_t sz)
61 unsigned long p = (unsigned long)ptr;
62 unsigned long start = p & ~15;
63 unsigned long end = (p + sz + 15) & ~15;
64 const unsigned char *c = ptr;
66 __hexdump(start, end, p, sz, c);
69 /* Currently, the CENA support code expects each 32-bit word to be written in
70 * host order, and these are converted to hardware (little-endian) order on
71 * command submission. However, 64-bit quantities are must be written (and read)
72 * as two 32-bit words with the least-significant word first, irrespective of
75 static inline void u64_to_le32_copy(void *d, const uint64_t *s,
79 const uint32_t *ss = (const uint32_t *)s;
82 /* TBD: the toolchain was choking on the use of 64-bit types up
83 * until recently so this works entirely with 32-bit variables.
84 * When 64-bit types become usable again, investigate better
87 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
98 static inline void u64_from_le32_copy(uint64_t *d, const void *s,
101 const uint32_t *ss = s;
102 uint32_t *dd = (uint32_t *)d;
105 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
119 struct qbman_swp_sys {
120 /* On GPP, the sys support for qbman_swp is here. The CENA region isi
121 * not an mmap() of the real portal registers, but an allocated
122 * place-holder, because the actual writes/reads to/from the portal are
123 * marshalled from these allocated areas using QBMan's "MC access
124 * registers". CINH accesses are atomic so there's no need for a
128 uint8_t __iomem *addr_cena;
129 uint8_t __iomem *addr_cinh;
131 enum qbman_eqcr_mode eqcr_mode;
134 /* P_OFFSET is (ACCESS_CMD,0,12) - offset within the portal
135 * C is (ACCESS_CMD,12,1) - is inhibited? (0==CENA, 1==CINH)
136 * SWP_IDX is (ACCESS_CMD,16,10) - Software portal index
137 * P is (ACCESS_CMD,28,1) - (0==special portal, 1==any portal)
138 * T is (ACCESS_CMD,29,1) - Command type (0==READ, 1==WRITE)
139 * E is (ACCESS_CMD,31,1) - Command execute (1 to issue, poll for 0==complete)
142 static inline void qbman_cinh_write(struct qbman_swp_sys *s, uint32_t offset,
145 __raw_writel(val, s->addr_cinh + offset);
146 #ifdef QBMAN_CINH_TRACE
147 pr_info("qbman_cinh_write(%p:%d:0x%03x) 0x%08x\n",
148 s->addr_cinh, s->idx, offset, val);
152 static inline uint32_t qbman_cinh_read(struct qbman_swp_sys *s, uint32_t offset)
154 uint32_t reg = __raw_readl(s->addr_cinh + offset);
155 #ifdef QBMAN_CINH_TRACE
156 pr_info("qbman_cinh_read(%p:%d:0x%03x) 0x%08x\n",
157 s->addr_cinh, s->idx, offset, reg);
162 static inline void *qbman_cena_write_start(struct qbman_swp_sys *s,
165 void *shadow = s->cena + offset;
167 #ifdef QBMAN_CENA_TRACE
168 pr_info("qbman_cena_write_start(%p:%d:0x%03x) %p\n",
169 s->addr_cena, s->idx, offset, shadow);
171 QBMAN_BUG_ON(offset & 63);
176 static inline void *qbman_cena_write_start_wo_shadow(struct qbman_swp_sys *s,
179 #ifdef QBMAN_CENA_TRACE
180 pr_info("qbman_cena_write_start(%p:%d:0x%03x)\n",
181 s->addr_cena, s->idx, offset);
183 QBMAN_BUG_ON(offset & 63);
185 return (s->addr_cena + offset);
187 return (s->addr_cinh + offset);
191 static inline void qbman_cena_write_complete(struct qbman_swp_sys *s,
192 uint32_t offset, void *cmd)
194 const uint32_t *shadow = cmd;
196 #ifdef QBMAN_CENA_TRACE
197 pr_info("qbman_cena_write_complete(%p:%d:0x%03x) %p\n",
198 s->addr_cena, s->idx, offset, shadow);
202 for (loop = 15; loop >= 1; loop--)
203 __raw_writel(shadow[loop], s->addr_cena +
206 __raw_writel(shadow[0], s->addr_cena + offset);
208 for (loop = 15; loop >= 1; loop--)
209 __raw_writel(shadow[loop], s->addr_cinh +
212 __raw_writel(shadow[0], s->addr_cinh + offset);
214 dcbf(s->addr_cena + offset);
217 static inline void qbman_cena_write_complete_wo_shadow(struct qbman_swp_sys *s,
220 #ifdef QBMAN_CENA_TRACE
221 pr_info("qbman_cena_write_complete(%p:%d:0x%03x)\n",
222 s->addr_cena, s->idx, offset);
224 dcbf(s->addr_cena + offset);
227 static inline uint32_t qbman_cena_read_reg(struct qbman_swp_sys *s,
230 return __raw_readl(s->addr_cena + offset);
233 static inline void *qbman_cena_read(struct qbman_swp_sys *s, uint32_t offset)
235 uint32_t *shadow = (uint32_t *)(s->cena + offset);
237 #ifdef QBMAN_CENA_TRACE
238 pr_info("qbman_cena_read(%p:%d:0x%03x) %p\n",
239 s->addr_cena, s->idx, offset, shadow);
243 for (loop = 0; loop < 16; loop++)
244 shadow[loop] = __raw_readl(s->addr_cena + offset
247 for (loop = 0; loop < 16; loop++)
248 shadow[loop] = __raw_readl(s->addr_cinh + offset
251 #ifdef QBMAN_CENA_TRACE
257 static inline void *qbman_cena_read_wo_shadow(struct qbman_swp_sys *s,
260 #ifdef QBMAN_CENA_TRACE
261 pr_info("qbman_cena_read(%p:%d:0x%03x)\n",
262 s->addr_cena, s->idx, offset);
264 return s->addr_cena + offset;
267 static inline void qbman_cena_invalidate(struct qbman_swp_sys *s,
270 dccivac(s->addr_cena + offset);
273 static inline void qbman_cena_invalidate_prefetch(struct qbman_swp_sys *s,
276 dccivac(s->addr_cena + offset);
277 prefetch_for_load(s->addr_cena + offset);
280 static inline void qbman_cena_prefetch(struct qbman_swp_sys *s,
283 prefetch_for_load(s->addr_cena + offset);
290 /* The SWP_CFG portal register is special, in that it is used by the
291 * platform-specific code rather than the platform-independent code in
292 * qbman_portal.c. So use of it is declared locally here.
294 #define QBMAN_CINH_SWP_CFG 0xd00
295 #define QBMAN_CINH_SWP_CFG 0xd00
296 #define SWP_CFG_DQRR_MF_SHIFT 20
297 #define SWP_CFG_EST_SHIFT 16
298 #define SWP_CFG_WN_SHIFT 14
299 #define SWP_CFG_RPM_SHIFT 12
300 #define SWP_CFG_DCM_SHIFT 10
301 #define SWP_CFG_EPM_SHIFT 8
302 #define SWP_CFG_SD_SHIFT 5
303 #define SWP_CFG_SP_SHIFT 4
304 #define SWP_CFG_SE_SHIFT 3
305 #define SWP_CFG_DP_SHIFT 2
306 #define SWP_CFG_DE_SHIFT 1
307 #define SWP_CFG_EP_SHIFT 0
309 static inline uint32_t qbman_set_swp_cfg(uint8_t max_fill, uint8_t wn,
310 uint8_t est, uint8_t rpm, uint8_t dcm,
311 uint8_t epm, int sd, int sp, int se,
312 int dp, int de, int ep)
316 reg = (max_fill << SWP_CFG_DQRR_MF_SHIFT |
317 est << SWP_CFG_EST_SHIFT |
318 wn << SWP_CFG_WN_SHIFT |
319 rpm << SWP_CFG_RPM_SHIFT |
320 dcm << SWP_CFG_DCM_SHIFT |
321 epm << SWP_CFG_EPM_SHIFT |
322 sd << SWP_CFG_SD_SHIFT |
323 sp << SWP_CFG_SP_SHIFT |
324 se << SWP_CFG_SE_SHIFT |
325 dp << SWP_CFG_DP_SHIFT |
326 de << SWP_CFG_DE_SHIFT |
327 ep << SWP_CFG_EP_SHIFT);
332 static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
333 const struct qbman_swp_desc *d,
338 uint8_t wn = CENA_WRITE_ENABLE;
340 uint8_t wn = CINH_WRITE_ENABLE;
343 s->addr_cena = d->cena_bar;
344 s->addr_cinh = d->cinh_bar;
345 s->idx = (uint32_t)d->idx;
346 s->cena = malloc(4096);
348 pr_err("Could not allocate page for cena shadow\n");
351 s->eqcr_mode = d->eqcr_mode;
352 QBMAN_BUG_ON(d->idx < 0);
353 #ifdef QBMAN_CHECKING
354 /* We should never be asked to initialise for a portal that isn't in
355 * the power-on state. (Ie. don't forget to reset portals when they are
358 reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
361 if (s->eqcr_mode == qman_eqcr_vb_array)
362 reg = qbman_set_swp_cfg(dqrr_size, wn, 0, 3, 2, 3, 1, 1, 1, 1,
365 reg = qbman_set_swp_cfg(dqrr_size, wn, 1, 3, 2, 2, 1, 1, 1, 1,
367 qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg);
368 reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
370 pr_err("The portal %d is not enabled!\n", s->idx);
377 static inline void qbman_swp_sys_finish(struct qbman_swp_sys *s)