4 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
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14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 /* qbman_sys_decl.h and qbman_sys.h are the two platform-specific files in the
29 * driver. They are only included via qbman_private.h, which is itself a
30 * platform-independent file and is included by all the other driver source.
32 * qbman_sys_decl.h is included prior to all other declarations and logic, and
33 * it exists to provide compatibility with any linux interfaces our
34 * single-source driver code is dependent on (eg. kmalloc). Ie. this file
35 * provides linux compatibility.
37 * This qbman_sys.h header, on the other hand, is included *after* any common
38 * and platform-neutral declarations and logic in qbman_private.h, and exists to
39 * implement any platform-specific logic of the qbman driver itself. Ie. it is
40 * *not* to provide linux compatibility.
43 /* Trace the 3 different classes of read/write access to QBMan. #undef as
46 #undef QBMAN_CCSR_TRACE
47 #undef QBMAN_CINH_TRACE
48 #undef QBMAN_CENA_TRACE
50 static inline void word_copy(void *d, const void *s, unsigned int cnt)
53 const uint32_t *ss = s;
59 /* Currently, the CENA support code expects each 32-bit word to be written in
60 * host order, and these are converted to hardware (little-endian) order on
61 * command submission. However, 64-bit quantities are must be written (and read)
62 * as two 32-bit words with the least-significant word first, irrespective of
65 static inline void u64_to_le32_copy(void *d, const uint64_t *s,
69 const uint32_t *ss = (const uint32_t *)s;
72 /* TBD: the toolchain was choking on the use of 64-bit types up
73 * until recently so this works entirely with 32-bit variables.
74 * When 64-bit types become usable again, investigate better
77 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
88 static inline void u64_from_le32_copy(uint64_t *d, const void *s,
91 const uint32_t *ss = s;
92 uint32_t *dd = (uint32_t *)d;
95 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
106 /* Convert a host-native 32bit value into little endian */
107 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
108 static inline uint32_t make_le32(uint32_t val)
110 return ((val & 0xff) << 24) | ((val & 0xff00) << 8) |
111 ((val & 0xff0000) >> 8) | ((val & 0xff000000) >> 24);
114 static inline uint32_t make_le24(uint32_t val)
116 return (((val & 0xff) << 16) | (val & 0xff00) |
117 ((val & 0xff0000) >> 16));
120 static inline void make_le32_n(uint32_t *val, unsigned int num)
123 *val = make_le32(*val);
129 #define make_le32(val) (val)
130 #define make_le24(val) (val)
131 #define make_le32_n(val, len) do {} while (0)
137 struct qbman_swp_sys {
138 /* On GPP, the sys support for qbman_swp is here. The CENA region isi
139 * not an mmap() of the real portal registers, but an allocated
140 * place-holder, because the actual writes/reads to/from the portal are
141 * marshalled from these allocated areas using QBMan's "MC access
142 * registers". CINH accesses are atomic so there's no need for a
146 uint8_t __iomem *addr_cena;
147 uint8_t __iomem *addr_cinh;
149 enum qbman_eqcr_mode eqcr_mode;
152 /* P_OFFSET is (ACCESS_CMD,0,12) - offset within the portal
153 * C is (ACCESS_CMD,12,1) - is inhibited? (0==CENA, 1==CINH)
154 * SWP_IDX is (ACCESS_CMD,16,10) - Software portal index
155 * P is (ACCESS_CMD,28,1) - (0==special portal, 1==any portal)
156 * T is (ACCESS_CMD,29,1) - Command type (0==READ, 1==WRITE)
157 * E is (ACCESS_CMD,31,1) - Command execute (1 to issue, poll for 0==complete)
160 static inline void qbman_cinh_write(struct qbman_swp_sys *s, uint32_t offset,
163 __raw_writel(val, s->addr_cinh + offset);
164 #ifdef QBMAN_CINH_TRACE
165 pr_info("qbman_cinh_write(%p:%d:0x%03x) 0x%08x\n",
166 s->addr_cinh, s->idx, offset, val);
170 static inline uint32_t qbman_cinh_read(struct qbman_swp_sys *s, uint32_t offset)
172 uint32_t reg = __raw_readl(s->addr_cinh + offset);
173 #ifdef QBMAN_CINH_TRACE
174 pr_info("qbman_cinh_read(%p:%d:0x%03x) 0x%08x\n",
175 s->addr_cinh, s->idx, offset, reg);
180 static inline void *qbman_cena_write_start(struct qbman_swp_sys *s,
183 void *shadow = s->cena + offset;
185 #ifdef QBMAN_CENA_TRACE
186 pr_info("qbman_cena_write_start(%p:%d:0x%03x) %p\n",
187 s->addr_cena, s->idx, offset, shadow);
189 QBMAN_BUG_ON(offset & 63);
194 static inline void *qbman_cena_write_start_wo_shadow(struct qbman_swp_sys *s,
197 #ifdef QBMAN_CENA_TRACE
198 pr_info("qbman_cena_write_start(%p:%d:0x%03x)\n",
199 s->addr_cena, s->idx, offset);
201 QBMAN_BUG_ON(offset & 63);
202 return (s->addr_cena + offset);
205 static inline void qbman_cena_write_complete(struct qbman_swp_sys *s,
206 uint32_t offset, void *cmd)
208 const uint32_t *shadow = cmd;
210 #ifdef QBMAN_CENA_TRACE
211 pr_info("qbman_cena_write_complete(%p:%d:0x%03x) %p\n",
212 s->addr_cena, s->idx, offset, shadow);
215 for (loop = 15; loop >= 1; loop--)
216 __raw_writel(shadow[loop], s->addr_cena +
219 __raw_writel(shadow[0], s->addr_cena + offset);
220 dcbf(s->addr_cena + offset);
223 static inline void qbman_cena_write_complete_wo_shadow(struct qbman_swp_sys *s,
226 #ifdef QBMAN_CENA_TRACE
227 pr_info("qbman_cena_write_complete(%p:%d:0x%03x)\n",
228 s->addr_cena, s->idx, offset);
231 dcbf(s->addr_cena + offset);
234 static inline uint32_t qbman_cena_read_reg(struct qbman_swp_sys *s,
237 return __raw_readl(s->addr_cena + offset);
240 static inline void *qbman_cena_read(struct qbman_swp_sys *s, uint32_t offset)
242 uint32_t *shadow = (uint32_t *)(s->cena + offset);
244 #ifdef QBMAN_CENA_TRACE
245 pr_info("qbman_cena_read(%p:%d:0x%03x) %p\n",
246 s->addr_cena, s->idx, offset, shadow);
249 for (loop = 0; loop < 16; loop++)
250 shadow[loop] = __raw_readl(s->addr_cena + offset
252 #ifdef QBMAN_CENA_TRACE
258 static inline void *qbman_cena_read_wo_shadow(struct qbman_swp_sys *s,
261 #ifdef QBMAN_CENA_TRACE
262 pr_info("qbman_cena_read(%p:%d:0x%03x) %p\n",
263 s->addr_cena, s->idx, offset, shadow);
266 #ifdef QBMAN_CENA_TRACE
269 return s->addr_cena + offset;
272 static inline void qbman_cena_invalidate(struct qbman_swp_sys *s,
275 dccivac(s->addr_cena + offset);
278 static inline void qbman_cena_invalidate_prefetch(struct qbman_swp_sys *s,
281 dccivac(s->addr_cena + offset);
282 prefetch_for_load(s->addr_cena + offset);
285 static inline void qbman_cena_prefetch(struct qbman_swp_sys *s,
288 prefetch_for_load(s->addr_cena + offset);
295 /* The SWP_CFG portal register is special, in that it is used by the
296 * platform-specific code rather than the platform-independent code in
297 * qbman_portal.c. So use of it is declared locally here.
299 #define QBMAN_CINH_SWP_CFG 0xd00
301 /* For MC portal use, we always configure with
302 * DQRR_MF is (SWP_CFG,20,3) - DQRR max fill (<- 0x4)
303 * EST is (SWP_CFG,16,3) - EQCR_CI stashing threshold (<- 0x2)
304 * RPM is (SWP_CFG,12,2) - RCR production notification mode (<- 0x3)
305 * DCM is (SWP_CFG,10,2) - DQRR consumption notification mode (<- 0x2)
306 * EPM is (SWP_CFG,8,2) - EQCR production notification mode (<- 0x2)
307 * SD is (SWP_CFG,5,1) - memory stashing drop enable (<- TRUE)
308 * SP is (SWP_CFG,4,1) - memory stashing priority (<- TRUE)
309 * SE is (SWP_CFG,3,1) - memory stashing enable (<- TRUE)
310 * DP is (SWP_CFG,2,1) - dequeue stashing priority (<- TRUE)
311 * DE is (SWP_CFG,1,1) - dequeue stashing enable (<- TRUE)
312 * EP is (SWP_CFG,0,1) - EQCR_CI stashing priority (<- TRUE)
314 static inline uint32_t qbman_set_swp_cfg(uint8_t max_fill, uint8_t wn,
315 uint8_t est, uint8_t rpm, uint8_t dcm,
316 uint8_t epm, int sd, int sp, int se,
317 int dp, int de, int ep)
321 reg = e32_uint8_t(20, (uint32_t)(3 + (max_fill >> 3)), max_fill) |
322 e32_uint8_t(16, 3, est) |
323 e32_uint8_t(12, 2, rpm) | e32_uint8_t(10, 2, dcm) |
324 e32_uint8_t(8, 2, epm) | e32_int(5, 1, sd) |
325 e32_int(4, 1, sp) | e32_int(3, 1, se) | e32_int(2, 1, dp) |
326 e32_int(1, 1, de) | e32_int(0, 1, ep) | e32_uint8_t(14, 1, wn);
330 static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
331 const struct qbman_swp_desc *d,
336 s->addr_cena = d->cena_bar;
337 s->addr_cinh = d->cinh_bar;
338 s->idx = (uint32_t)d->idx;
339 s->cena = (void *)get_zeroed_page(GFP_KERNEL);
341 pr_err("Could not allocate page for cena shadow\n");
344 s->eqcr_mode = d->eqcr_mode;
345 QBMAN_BUG_ON(d->idx < 0);
346 #ifdef QBMAN_CHECKING
347 /* We should never be asked to initialise for a portal that isn't in
348 * the power-on state. (Ie. don't forget to reset portals when they are
351 reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
354 if (s->eqcr_mode == qman_eqcr_vb_array)
355 reg = qbman_set_swp_cfg(dqrr_size, 0, 0, 3, 2, 3, 1, 1, 1, 1,
358 reg = qbman_set_swp_cfg(dqrr_size, 0, 2, 3, 2, 2, 1, 1, 1, 1,
360 qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg);
361 reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
363 pr_err("The portal %d is not enabled!\n", s->idx);
370 static inline void qbman_swp_sys_finish(struct qbman_swp_sys *s)
372 free_page((unsigned long)s->cena);
376 qbman_cena_write_start_wo_shadow_fast(struct qbman_swp_sys *s,
379 #ifdef QBMAN_CENA_TRACE
380 pr_info("qbman_cena_write_start(%p:%d:0x%03x)\n",
381 s->addr_cena, s->idx, offset);
383 QBMAN_BUG_ON(offset & 63);
384 return (s->addr_cena + offset);