4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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36 #include <linux/pci_regs.h>
37 #include <sys/eventfd.h>
38 #include <sys/socket.h>
39 #include <sys/ioctl.h>
45 #include <rte_bus_pci.h>
46 #include <rte_eal_memconfig.h>
47 #include <rte_malloc.h>
50 #include "eal_filesystem.h"
57 * PCI probing under linux (VFIO version)
59 * This code tries to determine if the PCI device is bound to VFIO driver,
60 * and initialize it (map BARs, set up interrupts) if that's the case.
62 * This file is only compiled if CONFIG_RTE_EAL_VFIO is set to "y".
67 #define PAGE_SIZE (sysconf(_SC_PAGESIZE))
68 #define PAGE_MASK (~(PAGE_SIZE - 1))
70 static struct rte_tailq_elem rte_vfio_tailq = {
71 .name = "VFIO_RESOURCE_LIST",
73 EAL_REGISTER_TAILQ(rte_vfio_tailq)
76 pci_vfio_read_config(const struct rte_intr_handle *intr_handle,
77 void *buf, size_t len, off_t offs)
79 return pread64(intr_handle->vfio_dev_fd, buf, len,
80 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
84 pci_vfio_write_config(const struct rte_intr_handle *intr_handle,
85 const void *buf, size_t len, off_t offs)
87 return pwrite64(intr_handle->vfio_dev_fd, buf, len,
88 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
91 /* get PCI BAR number where MSI-X interrupts are */
93 pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)
98 uint8_t cap_id, cap_offset;
100 /* read PCI capability pointer from config space */
101 ret = pread64(fd, ®, sizeof(reg),
102 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
103 PCI_CAPABILITY_LIST);
104 if (ret != sizeof(reg)) {
105 RTE_LOG(ERR, EAL, "Cannot read capability pointer from PCI "
110 /* we need first byte */
111 cap_offset = reg & 0xFF;
115 /* read PCI capability ID */
116 ret = pread64(fd, ®, sizeof(reg),
117 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
119 if (ret != sizeof(reg)) {
120 RTE_LOG(ERR, EAL, "Cannot read capability ID from PCI "
125 /* we need first byte */
128 /* if we haven't reached MSI-X, check next capability */
129 if (cap_id != PCI_CAP_ID_MSIX) {
130 ret = pread64(fd, ®, sizeof(reg),
131 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
133 if (ret != sizeof(reg)) {
134 RTE_LOG(ERR, EAL, "Cannot read capability pointer from PCI "
139 /* we need second byte */
140 cap_offset = (reg & 0xFF00) >> 8;
144 /* else, read table offset */
146 /* table offset resides in the next 4 bytes */
147 ret = pread64(fd, ®, sizeof(reg),
148 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
150 if (ret != sizeof(reg)) {
151 RTE_LOG(ERR, EAL, "Cannot read table offset from PCI config "
156 ret = pread64(fd, &flags, sizeof(flags),
157 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
159 if (ret != sizeof(flags)) {
160 RTE_LOG(ERR, EAL, "Cannot read table flags from PCI config "
165 msix_table->bar_index = reg & RTE_PCI_MSIX_TABLE_BIR;
166 msix_table->offset = reg & RTE_PCI_MSIX_TABLE_OFFSET;
168 16 * (1 + (flags & RTE_PCI_MSIX_FLAGS_QSIZE));
176 /* set PCI bus mastering */
178 pci_vfio_set_bus_master(int dev_fd, bool op)
183 ret = pread64(dev_fd, ®, sizeof(reg),
184 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
186 if (ret != sizeof(reg)) {
187 RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n");
192 /* set the master bit */
193 reg |= PCI_COMMAND_MASTER;
195 reg &= ~(PCI_COMMAND_MASTER);
197 ret = pwrite64(dev_fd, ®, sizeof(reg),
198 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
201 if (ret != sizeof(reg)) {
202 RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n");
209 /* set up interrupt support (but not enable interrupts) */
211 pci_vfio_setup_interrupts(struct rte_pci_device *dev, int vfio_dev_fd)
213 int i, ret, intr_idx;
214 enum rte_intr_mode intr_mode;
216 /* default to invalid index */
217 intr_idx = VFIO_PCI_NUM_IRQS;
219 /* Get default / configured intr_mode */
220 intr_mode = rte_eal_vfio_intr_mode();
222 /* get interrupt type from internal config (MSI-X by default, can be
223 * overridden from the command line
226 case RTE_INTR_MODE_MSIX:
227 intr_idx = VFIO_PCI_MSIX_IRQ_INDEX;
229 case RTE_INTR_MODE_MSI:
230 intr_idx = VFIO_PCI_MSI_IRQ_INDEX;
232 case RTE_INTR_MODE_LEGACY:
233 intr_idx = VFIO_PCI_INTX_IRQ_INDEX;
235 /* don't do anything if we want to automatically determine interrupt type */
236 case RTE_INTR_MODE_NONE:
239 RTE_LOG(ERR, EAL, " unknown default interrupt type!\n");
243 /* start from MSI-X interrupt type */
244 for (i = VFIO_PCI_MSIX_IRQ_INDEX; i >= 0; i--) {
245 struct vfio_irq_info irq = { .argsz = sizeof(irq) };
248 /* skip interrupt modes we don't want */
249 if (intr_mode != RTE_INTR_MODE_NONE &&
255 ret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);
257 RTE_LOG(ERR, EAL, " cannot get IRQ info, "
258 "error %i (%s)\n", errno, strerror(errno));
262 /* if this vector cannot be used with eventfd, fail if we explicitly
263 * specified interrupt type, otherwise continue */
264 if ((irq.flags & VFIO_IRQ_INFO_EVENTFD) == 0) {
265 if (intr_mode != RTE_INTR_MODE_NONE) {
267 " interrupt vector does not support eventfd!\n");
273 /* set up an eventfd for interrupts */
274 fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);
276 RTE_LOG(ERR, EAL, " cannot set up eventfd, "
277 "error %i (%s)\n", errno, strerror(errno));
281 dev->intr_handle.fd = fd;
282 dev->intr_handle.vfio_dev_fd = vfio_dev_fd;
285 case VFIO_PCI_MSIX_IRQ_INDEX:
286 intr_mode = RTE_INTR_MODE_MSIX;
287 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
289 case VFIO_PCI_MSI_IRQ_INDEX:
290 intr_mode = RTE_INTR_MODE_MSI;
291 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSI;
293 case VFIO_PCI_INTX_IRQ_INDEX:
294 intr_mode = RTE_INTR_MODE_LEGACY;
295 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_LEGACY;
298 RTE_LOG(ERR, EAL, " unknown interrupt type!\n");
305 /* if we're here, we haven't found a suitable interrupt vector */
310 pci_vfio_is_ioport_bar(int vfio_dev_fd, int bar_index)
315 ret = pread64(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar),
316 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX)
317 + PCI_BASE_ADDRESS_0 + bar_index*4);
318 if (ret != sizeof(ioport_bar)) {
319 RTE_LOG(ERR, EAL, "Cannot read command (%x) from config space!\n",
320 PCI_BASE_ADDRESS_0 + bar_index*4);
324 return (ioport_bar & PCI_BASE_ADDRESS_SPACE_IO) != 0;
328 pci_vfio_setup_device(struct rte_pci_device *dev, int vfio_dev_fd)
330 if (pci_vfio_setup_interrupts(dev, vfio_dev_fd) != 0) {
331 RTE_LOG(ERR, EAL, "Error setting up interrupts!\n");
335 /* set bus mastering for the device */
336 if (pci_vfio_set_bus_master(vfio_dev_fd, true)) {
337 RTE_LOG(ERR, EAL, "Cannot set up bus mastering!\n");
341 /* Reset the device */
342 if (ioctl(vfio_dev_fd, VFIO_DEVICE_RESET)) {
343 RTE_LOG(ERR, EAL, "Unable to reset device! Error: %d (%s)\n",
344 errno, strerror(errno));
352 pci_vfio_mmap_bar(int vfio_dev_fd, struct mapped_pci_resource *vfio_res,
353 int bar_index, int additional_flags)
356 unsigned long offset, size;
359 struct pci_msix_table *msix_table = &vfio_res->msix_table;
360 struct pci_map *bar = &vfio_res->maps[bar_index];
366 if (msix_table->bar_index == bar_index) {
368 * VFIO will not let us map the MSI-X table,
369 * but we can map around it.
371 uint32_t table_start = msix_table->offset;
372 uint32_t table_end = table_start + msix_table->size;
373 table_end = (table_end + ~PAGE_MASK) & PAGE_MASK;
374 table_start &= PAGE_MASK;
376 if (table_start == 0 && table_end >= bar->size) {
377 /* Cannot map this BAR */
378 RTE_LOG(DEBUG, EAL, "Skipping BAR%d\n", bar_index);
384 memreg[0].offset = bar->offset;
385 memreg[0].size = table_start;
386 memreg[1].offset = bar->offset + table_end;
387 memreg[1].size = bar->size - table_end;
390 "Trying to map BAR%d that contains the MSI-X "
391 "table. Trying offsets: "
392 "0x%04lx:0x%04lx, 0x%04lx:0x%04lx\n", bar_index,
393 memreg[0].offset, memreg[0].size,
394 memreg[1].offset, memreg[1].size);
396 memreg[0].offset = bar->offset;
397 memreg[0].size = bar->size;
400 /* reserve the address using an inaccessible mapping */
401 bar_addr = mmap(bar->addr, bar->size, 0, MAP_PRIVATE |
402 MAP_ANONYMOUS | additional_flags, -1, 0);
403 if (bar_addr != MAP_FAILED) {
404 void *map_addr = NULL;
405 if (memreg[0].size) {
406 /* actual map of first part */
407 map_addr = pci_map_resource(bar_addr, vfio_dev_fd,
413 /* if there's a second part, try to map it */
414 if (map_addr != MAP_FAILED
415 && memreg[1].offset && memreg[1].size) {
416 void *second_addr = RTE_PTR_ADD(bar_addr,
418 (uintptr_t)bar->offset);
419 map_addr = pci_map_resource(second_addr,
426 if (map_addr == MAP_FAILED || !map_addr) {
427 munmap(bar_addr, bar->size);
428 bar_addr = MAP_FAILED;
429 RTE_LOG(ERR, EAL, "Failed to map pci BAR%d\n",
435 "Failed to create inaccessible mapping for BAR%d\n",
440 bar->addr = bar_addr;
445 pci_vfio_map_resource_primary(struct rte_pci_device *dev)
447 struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
448 char pci_addr[PATH_MAX] = {0};
450 struct rte_pci_addr *loc = &dev->addr;
452 struct mapped_pci_resource *vfio_res = NULL;
453 struct mapped_pci_res_list *vfio_res_list =
454 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
456 struct pci_map *maps;
458 dev->intr_handle.fd = -1;
459 dev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
461 /* store PCI address string */
462 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
463 loc->domain, loc->bus, loc->devid, loc->function);
465 ret = vfio_setup_device(pci_get_sysfs_path(), pci_addr,
466 &vfio_dev_fd, &device_info);
470 /* allocate vfio_res and get region info */
471 vfio_res = rte_zmalloc("VFIO_RES", sizeof(*vfio_res), 0);
472 if (vfio_res == NULL) {
474 "%s(): cannot store uio mmap details\n", __func__);
475 goto err_vfio_dev_fd;
477 memcpy(&vfio_res->pci_addr, &dev->addr, sizeof(vfio_res->pci_addr));
479 /* get number of registers (up to BAR5) */
480 vfio_res->nb_maps = RTE_MIN((int) device_info.num_regions,
481 VFIO_PCI_BAR5_REGION_INDEX + 1);
484 maps = vfio_res->maps;
486 vfio_res->msix_table.bar_index = -1;
487 /* get MSI-X BAR, if any (we have to know where it is because we can't
488 * easily mmap it when using VFIO)
490 ret = pci_vfio_get_msix_bar(vfio_dev_fd, &vfio_res->msix_table);
492 RTE_LOG(ERR, EAL, " %s cannot get MSI-X BAR number!\n",
494 goto err_vfio_dev_fd;
497 for (i = 0; i < (int) vfio_res->nb_maps; i++) {
498 struct vfio_region_info reg = { .argsz = sizeof(reg) };
503 ret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ®);
505 RTE_LOG(ERR, EAL, " %s cannot get device region info "
506 "error %i (%s)\n", pci_addr, errno, strerror(errno));
510 /* chk for io port region */
511 ret = pci_vfio_is_ioport_bar(vfio_dev_fd, i);
515 RTE_LOG(INFO, EAL, "Ignore mapping IO port bar(%d)\n",
520 /* skip non-mmapable BARs */
521 if ((reg.flags & VFIO_REGION_INFO_FLAG_MMAP) == 0)
524 /* try mapping somewhere close to the end of hugepages */
525 if (pci_map_addr == NULL)
526 pci_map_addr = pci_find_max_end_va();
528 bar_addr = pci_map_addr;
529 pci_map_addr = RTE_PTR_ADD(bar_addr, (size_t) reg.size);
531 maps[i].addr = bar_addr;
532 maps[i].offset = reg.offset;
533 maps[i].size = reg.size;
534 maps[i].path = NULL; /* vfio doesn't have per-resource paths */
536 ret = pci_vfio_mmap_bar(vfio_dev_fd, vfio_res, i, 0);
538 RTE_LOG(ERR, EAL, " %s mapping BAR%i failed: %s\n",
539 pci_addr, i, strerror(errno));
543 dev->mem_resource[i].addr = maps[i].addr;
546 if (pci_vfio_setup_device(dev, vfio_dev_fd) < 0) {
547 RTE_LOG(ERR, EAL, " %s setup device failed\n", pci_addr);
551 TAILQ_INSERT_TAIL(vfio_res_list, vfio_res, next);
562 pci_vfio_map_resource_secondary(struct rte_pci_device *dev)
564 struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
565 char pci_addr[PATH_MAX] = {0};
567 struct rte_pci_addr *loc = &dev->addr;
569 struct mapped_pci_resource *vfio_res = NULL;
570 struct mapped_pci_res_list *vfio_res_list =
571 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
573 struct pci_map *maps;
575 dev->intr_handle.fd = -1;
576 dev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
578 /* store PCI address string */
579 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
580 loc->domain, loc->bus, loc->devid, loc->function);
582 ret = vfio_setup_device(pci_get_sysfs_path(), pci_addr,
583 &vfio_dev_fd, &device_info);
587 /* if we're in a secondary process, just find our tailq entry */
588 TAILQ_FOREACH(vfio_res, vfio_res_list, next) {
589 if (pci_addr_cmp(&vfio_res->pci_addr,
594 /* if we haven't found our tailq entry, something's wrong */
595 if (vfio_res == NULL) {
596 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
598 goto err_vfio_dev_fd;
602 maps = vfio_res->maps;
604 for (i = 0; i < (int) vfio_res->nb_maps; i++) {
605 ret = pci_vfio_mmap_bar(vfio_dev_fd, vfio_res, i, MAP_FIXED);
607 RTE_LOG(ERR, EAL, " %s mapping BAR%i failed: %s\n",
608 pci_addr, i, strerror(errno));
609 goto err_vfio_dev_fd;
612 dev->mem_resource[i].addr = maps[i].addr;
622 * map the PCI resources of a PCI device in virtual memory (VFIO version).
623 * primary and secondary processes follow almost exactly the same path
626 pci_vfio_map_resource(struct rte_pci_device *dev)
628 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
629 return pci_vfio_map_resource_primary(dev);
631 return pci_vfio_map_resource_secondary(dev);
635 pci_vfio_unmap_resource(struct rte_pci_device *dev)
637 char pci_addr[PATH_MAX] = {0};
638 struct rte_pci_addr *loc = &dev->addr;
640 struct mapped_pci_resource *vfio_res = NULL;
641 struct mapped_pci_res_list *vfio_res_list;
643 struct pci_map *maps;
645 /* store PCI address string */
646 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
647 loc->domain, loc->bus, loc->devid, loc->function);
650 if (close(dev->intr_handle.fd) < 0) {
651 RTE_LOG(INFO, EAL, "Error when closing eventfd file descriptor for %s\n",
656 if (pci_vfio_set_bus_master(dev->intr_handle.vfio_dev_fd, false)) {
657 RTE_LOG(ERR, EAL, " %s cannot unset bus mastering for PCI device!\n",
662 ret = vfio_release_device(pci_get_sysfs_path(), pci_addr,
663 dev->intr_handle.vfio_dev_fd);
666 "%s(): cannot release device\n", __func__);
670 vfio_res_list = RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
672 TAILQ_FOREACH(vfio_res, vfio_res_list, next) {
673 if (memcmp(&vfio_res->pci_addr, &dev->addr, sizeof(dev->addr)))
677 /* if we haven't found our tailq entry, something's wrong */
678 if (vfio_res == NULL) {
679 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
685 maps = vfio_res->maps;
687 RTE_LOG(INFO, EAL, "Releasing pci mapped resource for %s\n",
689 for (i = 0; i < (int) vfio_res->nb_maps; i++) {
692 * We do not need to be aware of MSI-X table BAR mappings as
693 * when mapping. Just using current maps array is enough
696 RTE_LOG(INFO, EAL, "Calling pci_unmap_resource for %s at %p\n",
697 pci_addr, maps[i].addr);
698 pci_unmap_resource(maps[i].addr, maps[i].size);
702 TAILQ_REMOVE(vfio_res_list, vfio_res, next);
708 pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,
709 struct rte_pci_ioport *p)
711 if (bar < VFIO_PCI_BAR0_REGION_INDEX ||
712 bar > VFIO_PCI_BAR5_REGION_INDEX) {
713 RTE_LOG(ERR, EAL, "invalid bar (%d)!\n", bar);
718 p->base = VFIO_GET_REGION_ADDR(bar);
723 pci_vfio_ioport_read(struct rte_pci_ioport *p,
724 void *data, size_t len, off_t offset)
726 const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
728 if (pread64(intr_handle->vfio_dev_fd, data,
729 len, p->base + offset) <= 0)
731 "Can't read from PCI bar (%" PRIu64 ") : offset (%x)\n",
732 VFIO_GET_REGION_IDX(p->base), (int)offset);
736 pci_vfio_ioport_write(struct rte_pci_ioport *p,
737 const void *data, size_t len, off_t offset)
739 const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
741 if (pwrite64(intr_handle->vfio_dev_fd, data,
742 len, p->base + offset) <= 0)
744 "Can't write to PCI bar (%" PRIu64 ") : offset (%x)\n",
745 VFIO_GET_REGION_IDX(p->base), (int)offset);
749 pci_vfio_ioport_unmap(struct rte_pci_ioport *p)
756 pci_vfio_is_enabled(void)
758 return vfio_is_enabled("vfio_pci");