1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2014 Intel Corporation
7 #include <linux/pci_regs.h>
8 #include <sys/eventfd.h>
9 #include <sys/socket.h>
10 #include <sys/ioctl.h>
16 #include <rte_bus_pci.h>
17 #include <rte_eal_paging.h>
18 #include <rte_malloc.h>
22 #include <rte_spinlock.h>
23 #include <rte_tailq.h>
25 #include "eal_filesystem.h"
32 * PCI probing under linux (VFIO version)
34 * This code tries to determine if the PCI device is bound to VFIO driver,
35 * and initialize it (map BARs, set up interrupts) if that's the case.
42 #define PAGE_SIZE (sysconf(_SC_PAGESIZE))
44 #define PAGE_MASK (~(PAGE_SIZE - 1))
46 static struct rte_tailq_elem rte_vfio_tailq = {
47 .name = "VFIO_RESOURCE_LIST",
49 EAL_REGISTER_TAILQ(rte_vfio_tailq)
52 pci_vfio_read_config(const struct rte_intr_handle *intr_handle,
53 void *buf, size_t len, off_t offs)
55 return pread64(intr_handle->vfio_dev_fd, buf, len,
56 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
60 pci_vfio_write_config(const struct rte_intr_handle *intr_handle,
61 const void *buf, size_t len, off_t offs)
63 return pwrite64(intr_handle->vfio_dev_fd, buf, len,
64 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
67 /* get PCI BAR number where MSI-X interrupts are */
69 pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)
74 uint8_t cap_id, cap_offset;
76 /* read PCI capability pointer from config space */
77 ret = pread64(fd, ®, sizeof(reg),
78 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
80 if (ret != sizeof(reg)) {
81 RTE_LOG(ERR, EAL, "Cannot read capability pointer from PCI "
86 /* we need first byte */
87 cap_offset = reg & 0xFF;
91 /* read PCI capability ID */
92 ret = pread64(fd, ®, sizeof(reg),
93 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
95 if (ret != sizeof(reg)) {
96 RTE_LOG(ERR, EAL, "Cannot read capability ID from PCI "
101 /* we need first byte */
104 /* if we haven't reached MSI-X, check next capability */
105 if (cap_id != PCI_CAP_ID_MSIX) {
106 ret = pread64(fd, ®, sizeof(reg),
107 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
109 if (ret != sizeof(reg)) {
110 RTE_LOG(ERR, EAL, "Cannot read capability pointer from PCI "
115 /* we need second byte */
116 cap_offset = (reg & 0xFF00) >> 8;
120 /* else, read table offset */
122 /* table offset resides in the next 4 bytes */
123 ret = pread64(fd, ®, sizeof(reg),
124 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
126 if (ret != sizeof(reg)) {
127 RTE_LOG(ERR, EAL, "Cannot read table offset from PCI config "
132 ret = pread64(fd, &flags, sizeof(flags),
133 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
135 if (ret != sizeof(flags)) {
136 RTE_LOG(ERR, EAL, "Cannot read table flags from PCI config "
141 msix_table->bar_index = reg & RTE_PCI_MSIX_TABLE_BIR;
142 msix_table->offset = reg & RTE_PCI_MSIX_TABLE_OFFSET;
144 16 * (1 + (flags & RTE_PCI_MSIX_FLAGS_QSIZE));
152 /* enable PCI bus memory space */
154 pci_vfio_enable_bus_memory(int dev_fd)
159 ret = pread64(dev_fd, &cmd, sizeof(cmd),
160 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
163 if (ret != sizeof(cmd)) {
164 RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n");
168 if (cmd & PCI_COMMAND_MEMORY)
171 cmd |= PCI_COMMAND_MEMORY;
172 ret = pwrite64(dev_fd, &cmd, sizeof(cmd),
173 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
176 if (ret != sizeof(cmd)) {
177 RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n");
184 /* set PCI bus mastering */
186 pci_vfio_set_bus_master(int dev_fd, bool op)
191 ret = pread64(dev_fd, ®, sizeof(reg),
192 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
194 if (ret != sizeof(reg)) {
195 RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n");
200 /* set the master bit */
201 reg |= PCI_COMMAND_MASTER;
203 reg &= ~(PCI_COMMAND_MASTER);
205 ret = pwrite64(dev_fd, ®, sizeof(reg),
206 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
209 if (ret != sizeof(reg)) {
210 RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n");
217 /* set up interrupt support (but not enable interrupts) */
219 pci_vfio_setup_interrupts(struct rte_pci_device *dev, int vfio_dev_fd)
221 int i, ret, intr_idx;
222 enum rte_intr_mode intr_mode;
224 /* default to invalid index */
225 intr_idx = VFIO_PCI_NUM_IRQS;
227 /* Get default / configured intr_mode */
228 intr_mode = rte_eal_vfio_intr_mode();
230 /* get interrupt type from internal config (MSI-X by default, can be
231 * overridden from the command line
234 case RTE_INTR_MODE_MSIX:
235 intr_idx = VFIO_PCI_MSIX_IRQ_INDEX;
237 case RTE_INTR_MODE_MSI:
238 intr_idx = VFIO_PCI_MSI_IRQ_INDEX;
240 case RTE_INTR_MODE_LEGACY:
241 intr_idx = VFIO_PCI_INTX_IRQ_INDEX;
243 /* don't do anything if we want to automatically determine interrupt type */
244 case RTE_INTR_MODE_NONE:
247 RTE_LOG(ERR, EAL, " unknown default interrupt type!\n");
251 /* start from MSI-X interrupt type */
252 for (i = VFIO_PCI_MSIX_IRQ_INDEX; i >= 0; i--) {
253 struct vfio_irq_info irq = { .argsz = sizeof(irq) };
256 /* skip interrupt modes we don't want */
257 if (intr_mode != RTE_INTR_MODE_NONE &&
263 ret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);
265 RTE_LOG(ERR, EAL, " cannot get IRQ info, "
266 "error %i (%s)\n", errno, strerror(errno));
270 /* if this vector cannot be used with eventfd, fail if we explicitly
271 * specified interrupt type, otherwise continue */
272 if ((irq.flags & VFIO_IRQ_INFO_EVENTFD) == 0) {
273 if (intr_mode != RTE_INTR_MODE_NONE) {
275 " interrupt vector does not support eventfd!\n");
281 /* set up an eventfd for interrupts */
282 fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);
284 RTE_LOG(ERR, EAL, " cannot set up eventfd, "
285 "error %i (%s)\n", errno, strerror(errno));
289 dev->intr_handle.fd = fd;
290 dev->intr_handle.vfio_dev_fd = vfio_dev_fd;
293 case VFIO_PCI_MSIX_IRQ_INDEX:
294 intr_mode = RTE_INTR_MODE_MSIX;
295 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
297 case VFIO_PCI_MSI_IRQ_INDEX:
298 intr_mode = RTE_INTR_MODE_MSI;
299 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSI;
301 case VFIO_PCI_INTX_IRQ_INDEX:
302 intr_mode = RTE_INTR_MODE_LEGACY;
303 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_LEGACY;
306 RTE_LOG(ERR, EAL, " unknown interrupt type!\n");
313 /* if we're here, we haven't found a suitable interrupt vector */
317 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
319 * Spinlock for device hot-unplug failure handling.
320 * If it tries to access bus or device, such as handle sigbus on bus
321 * or handle memory failure for device, just need to use this lock.
322 * It could protect the bus and the device to avoid race condition.
324 static rte_spinlock_t failure_handle_lock = RTE_SPINLOCK_INITIALIZER;
327 pci_vfio_req_handler(void *param)
331 struct rte_device *device = (struct rte_device *)param;
333 rte_spinlock_lock(&failure_handle_lock);
334 bus = rte_bus_find_by_device(device);
336 RTE_LOG(ERR, EAL, "Cannot find bus for device (%s)\n",
342 * vfio kernel module request user space to release allocated
343 * resources before device be deleted in kernel, so it can directly
344 * call the vfio bus hot-unplug handler to process it.
346 ret = bus->hot_unplug_handler(device);
349 "Can not handle hot-unplug for device (%s)\n",
352 rte_spinlock_unlock(&failure_handle_lock);
355 /* enable notifier (only enable req now) */
357 pci_vfio_enable_notifier(struct rte_pci_device *dev, int vfio_dev_fd)
362 /* set up an eventfd for req notifier */
363 fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);
365 RTE_LOG(ERR, EAL, "Cannot set up eventfd, error %i (%s)\n",
366 errno, strerror(errno));
370 dev->vfio_req_intr_handle.fd = fd;
371 dev->vfio_req_intr_handle.type = RTE_INTR_HANDLE_VFIO_REQ;
372 dev->vfio_req_intr_handle.vfio_dev_fd = vfio_dev_fd;
374 ret = rte_intr_callback_register(&dev->vfio_req_intr_handle,
375 pci_vfio_req_handler,
376 (void *)&dev->device);
378 RTE_LOG(ERR, EAL, "Fail to register req notifier handler.\n");
382 ret = rte_intr_enable(&dev->vfio_req_intr_handle);
384 RTE_LOG(ERR, EAL, "Fail to enable req notifier.\n");
385 ret = rte_intr_callback_unregister(&dev->vfio_req_intr_handle,
386 pci_vfio_req_handler,
387 (void *)&dev->device);
390 "Fail to unregister req notifier handler.\n");
398 dev->vfio_req_intr_handle.fd = -1;
399 dev->vfio_req_intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
400 dev->vfio_req_intr_handle.vfio_dev_fd = -1;
405 /* disable notifier (only disable req now) */
407 pci_vfio_disable_notifier(struct rte_pci_device *dev)
411 ret = rte_intr_disable(&dev->vfio_req_intr_handle);
413 RTE_LOG(ERR, EAL, "fail to disable req notifier.\n");
417 ret = rte_intr_callback_unregister(&dev->vfio_req_intr_handle,
418 pci_vfio_req_handler,
419 (void *)&dev->device);
422 "fail to unregister req notifier handler.\n");
426 close(dev->vfio_req_intr_handle.fd);
428 dev->vfio_req_intr_handle.fd = -1;
429 dev->vfio_req_intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
430 dev->vfio_req_intr_handle.vfio_dev_fd = -1;
437 pci_vfio_is_ioport_bar(int vfio_dev_fd, int bar_index)
442 ret = pread64(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar),
443 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX)
444 + PCI_BASE_ADDRESS_0 + bar_index*4);
445 if (ret != sizeof(ioport_bar)) {
446 RTE_LOG(ERR, EAL, "Cannot read command (%x) from config space!\n",
447 PCI_BASE_ADDRESS_0 + bar_index*4);
451 return (ioport_bar & PCI_BASE_ADDRESS_SPACE_IO) != 0;
455 pci_rte_vfio_setup_device(struct rte_pci_device *dev, int vfio_dev_fd)
457 if (pci_vfio_setup_interrupts(dev, vfio_dev_fd) != 0) {
458 RTE_LOG(ERR, EAL, "Error setting up interrupts!\n");
462 if (pci_vfio_enable_bus_memory(vfio_dev_fd)) {
463 RTE_LOG(ERR, EAL, "Cannot enable bus memory!\n");
467 /* set bus mastering for the device */
468 if (pci_vfio_set_bus_master(vfio_dev_fd, true)) {
469 RTE_LOG(ERR, EAL, "Cannot set up bus mastering!\n");
474 * Reset the device. If the device is not capable of resetting,
475 * then it updates errno as EINVAL.
477 if (ioctl(vfio_dev_fd, VFIO_DEVICE_RESET) && errno != EINVAL) {
478 RTE_LOG(ERR, EAL, "Unable to reset device! Error: %d (%s)\n",
479 errno, strerror(errno));
487 pci_vfio_mmap_bar(int vfio_dev_fd, struct mapped_pci_resource *vfio_res,
488 int bar_index, int additional_flags)
495 struct pci_msix_table *msix_table = &vfio_res->msix_table;
496 struct pci_map *bar = &vfio_res->maps[bar_index];
498 if (bar->size == 0) {
499 RTE_LOG(DEBUG, EAL, "Bar size is 0, skip BAR%d\n", bar_index);
503 if (msix_table->bar_index == bar_index) {
505 * VFIO will not let us map the MSI-X table,
506 * but we can map around it.
508 uint32_t table_start = msix_table->offset;
509 uint32_t table_end = table_start + msix_table->size;
510 table_end = RTE_ALIGN(table_end, PAGE_SIZE);
511 table_start = RTE_ALIGN_FLOOR(table_start, PAGE_SIZE);
513 /* If page-aligned start of MSI-X table is less than the
514 * actual MSI-X table start address, reassign to the actual
517 if (table_start < msix_table->offset)
518 table_start = msix_table->offset;
520 if (table_start == 0 && table_end >= bar->size) {
521 /* Cannot map this BAR */
522 RTE_LOG(DEBUG, EAL, "Skipping BAR%d\n", bar_index);
528 memreg[0].offset = bar->offset;
529 memreg[0].size = table_start;
530 if (bar->size < table_end) {
532 * If MSI-X table end is beyond BAR end, don't attempt
533 * to perform second mapping.
535 memreg[1].offset = 0;
538 memreg[1].offset = bar->offset + table_end;
539 memreg[1].size = bar->size - table_end;
543 "Trying to map BAR%d that contains the MSI-X "
544 "table. Trying offsets: "
545 "0x%04" PRIx64 ":0x%04zx, 0x%04" PRIx64 ":0x%04zx\n",
547 memreg[0].offset, memreg[0].size,
548 memreg[1].offset, memreg[1].size);
550 memreg[0].offset = bar->offset;
551 memreg[0].size = bar->size;
554 /* reserve the address using an inaccessible mapping */
555 bar_addr = mmap(bar->addr, bar->size, 0, MAP_PRIVATE |
556 MAP_ANONYMOUS | additional_flags, -1, 0);
557 if (bar_addr != MAP_FAILED) {
558 void *map_addr = NULL;
559 if (memreg[0].size) {
560 /* actual map of first part */
561 map_addr = pci_map_resource(bar_addr, vfio_dev_fd,
564 RTE_MAP_FORCE_ADDRESS);
568 * Regarding "memreg[0].size == 0":
569 * If this BAR has MSI-X table, memreg[0].size (the
570 * first part or the part before the table) can
571 * legitimately be 0 for hardware using vector table
572 * offset 0 (i.e. first part does not exist).
574 * When memreg[0].size is 0, "mapping the first part"
575 * never happens, and map_addr is NULL at this
576 * point. So check that mapping has been actually
579 /* if there's a second part, try to map it */
580 if ((map_addr != NULL || memreg[0].size == 0)
581 && memreg[1].offset && memreg[1].size) {
582 void *second_addr = RTE_PTR_ADD(bar_addr,
583 (uintptr_t)(memreg[1].offset -
585 map_addr = pci_map_resource(second_addr,
589 RTE_MAP_FORCE_ADDRESS);
592 if (map_addr == NULL) {
593 munmap(bar_addr, bar->size);
594 bar_addr = MAP_FAILED;
595 RTE_LOG(ERR, EAL, "Failed to map pci BAR%d\n",
601 "Failed to create inaccessible mapping for BAR%d\n",
606 bar->addr = bar_addr;
611 * region info may contain capability headers, so we need to keep reallocating
612 * the memory until we match allocated memory size with argsz.
615 pci_vfio_get_region_info(int vfio_dev_fd, struct vfio_region_info **info,
618 struct vfio_region_info *ri;
619 size_t argsz = sizeof(*ri);
622 ri = malloc(sizeof(*ri));
624 RTE_LOG(ERR, EAL, "Cannot allocate memory for region info\n");
628 memset(ri, 0, argsz);
632 ret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ri);
637 if (ri->argsz != argsz) {
638 struct vfio_region_info *tmp;
641 tmp = realloc(ri, argsz);
644 /* realloc failed but the ri is still there */
646 RTE_LOG(ERR, EAL, "Cannot reallocate memory for region info\n");
657 static struct vfio_info_cap_header *
658 pci_vfio_info_cap(struct vfio_region_info *info, int cap)
660 struct vfio_info_cap_header *h;
663 if ((info->flags & RTE_VFIO_INFO_FLAG_CAPS) == 0) {
664 /* VFIO info does not advertise capabilities */
668 offset = VFIO_CAP_OFFSET(info);
669 while (offset != 0) {
670 h = RTE_PTR_ADD(info, offset);
679 pci_vfio_msix_is_mappable(int vfio_dev_fd, int msix_region)
681 struct vfio_region_info *info;
684 ret = pci_vfio_get_region_info(vfio_dev_fd, &info, msix_region);
688 ret = pci_vfio_info_cap(info, RTE_VFIO_CAP_MSIX_MAPPABLE) != NULL;
698 pci_vfio_map_resource_primary(struct rte_pci_device *dev)
700 struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
701 char pci_addr[PATH_MAX] = {0};
703 struct rte_pci_addr *loc = &dev->addr;
705 struct mapped_pci_resource *vfio_res = NULL;
706 struct mapped_pci_res_list *vfio_res_list =
707 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
709 struct pci_map *maps;
711 dev->intr_handle.fd = -1;
712 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
713 dev->vfio_req_intr_handle.fd = -1;
716 /* store PCI address string */
717 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
718 loc->domain, loc->bus, loc->devid, loc->function);
720 ret = rte_vfio_setup_device(rte_pci_get_sysfs_path(), pci_addr,
721 &vfio_dev_fd, &device_info);
725 /* allocate vfio_res and get region info */
726 vfio_res = rte_zmalloc("VFIO_RES", sizeof(*vfio_res), 0);
727 if (vfio_res == NULL) {
729 "%s(): cannot store vfio mmap details\n", __func__);
730 goto err_vfio_dev_fd;
732 memcpy(&vfio_res->pci_addr, &dev->addr, sizeof(vfio_res->pci_addr));
734 /* get number of registers (up to BAR5) */
735 vfio_res->nb_maps = RTE_MIN((int) device_info.num_regions,
736 VFIO_PCI_BAR5_REGION_INDEX + 1);
739 maps = vfio_res->maps;
741 vfio_res->msix_table.bar_index = -1;
742 /* get MSI-X BAR, if any (we have to know where it is because we can't
743 * easily mmap it when using VFIO)
745 ret = pci_vfio_get_msix_bar(vfio_dev_fd, &vfio_res->msix_table);
747 RTE_LOG(ERR, EAL, " %s cannot get MSI-X BAR number!\n",
751 /* if we found our MSI-X BAR region, check if we can mmap it */
752 if (vfio_res->msix_table.bar_index != -1) {
753 int ret = pci_vfio_msix_is_mappable(vfio_dev_fd,
754 vfio_res->msix_table.bar_index);
756 RTE_LOG(ERR, EAL, "Couldn't check if MSI-X BAR is mappable\n");
758 } else if (ret != 0) {
759 /* we can map it, so we don't care where it is */
760 RTE_LOG(DEBUG, EAL, "VFIO reports MSI-X BAR as mappable\n");
761 vfio_res->msix_table.bar_index = -1;
765 for (i = 0; i < (int) vfio_res->nb_maps; i++) {
766 struct vfio_region_info *reg = NULL;
769 ret = pci_vfio_get_region_info(vfio_dev_fd, ®, i);
771 RTE_LOG(ERR, EAL, " %s cannot get device region info "
772 "error %i (%s)\n", pci_addr, errno,
777 /* chk for io port region */
778 ret = pci_vfio_is_ioport_bar(vfio_dev_fd, i);
783 RTE_LOG(INFO, EAL, "Ignore mapping IO port bar(%d)\n",
789 /* skip non-mmapable BARs */
790 if ((reg->flags & VFIO_REGION_INFO_FLAG_MMAP) == 0) {
795 /* try mapping somewhere close to the end of hugepages */
796 if (pci_map_addr == NULL)
797 pci_map_addr = pci_find_max_end_va();
799 bar_addr = pci_map_addr;
800 pci_map_addr = RTE_PTR_ADD(bar_addr, (size_t) reg->size);
802 pci_map_addr = RTE_PTR_ALIGN(pci_map_addr,
803 sysconf(_SC_PAGE_SIZE));
805 maps[i].addr = bar_addr;
806 maps[i].offset = reg->offset;
807 maps[i].size = reg->size;
808 maps[i].path = NULL; /* vfio doesn't have per-resource paths */
810 ret = pci_vfio_mmap_bar(vfio_dev_fd, vfio_res, i, 0);
812 RTE_LOG(ERR, EAL, " %s mapping BAR%i failed: %s\n",
813 pci_addr, i, strerror(errno));
818 dev->mem_resource[i].addr = maps[i].addr;
823 if (pci_rte_vfio_setup_device(dev, vfio_dev_fd) < 0) {
824 RTE_LOG(ERR, EAL, " %s setup device failed\n", pci_addr);
828 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
829 if (pci_vfio_enable_notifier(dev, vfio_dev_fd) != 0) {
830 RTE_LOG(ERR, EAL, "Error setting up notifier!\n");
835 TAILQ_INSERT_TAIL(vfio_res_list, vfio_res, next);
846 pci_vfio_map_resource_secondary(struct rte_pci_device *dev)
848 struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
849 char pci_addr[PATH_MAX] = {0};
851 struct rte_pci_addr *loc = &dev->addr;
853 struct mapped_pci_resource *vfio_res = NULL;
854 struct mapped_pci_res_list *vfio_res_list =
855 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
857 struct pci_map *maps;
859 dev->intr_handle.fd = -1;
860 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
861 dev->vfio_req_intr_handle.fd = -1;
864 /* store PCI address string */
865 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
866 loc->domain, loc->bus, loc->devid, loc->function);
868 /* if we're in a secondary process, just find our tailq entry */
869 TAILQ_FOREACH(vfio_res, vfio_res_list, next) {
870 if (rte_pci_addr_cmp(&vfio_res->pci_addr,
875 /* if we haven't found our tailq entry, something's wrong */
876 if (vfio_res == NULL) {
877 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
882 ret = rte_vfio_setup_device(rte_pci_get_sysfs_path(), pci_addr,
883 &vfio_dev_fd, &device_info);
888 maps = vfio_res->maps;
890 for (i = 0; i < (int) vfio_res->nb_maps; i++) {
891 ret = pci_vfio_mmap_bar(vfio_dev_fd, vfio_res, i, MAP_FIXED);
893 RTE_LOG(ERR, EAL, " %s mapping BAR%i failed: %s\n",
894 pci_addr, i, strerror(errno));
895 goto err_vfio_dev_fd;
898 dev->mem_resource[i].addr = maps[i].addr;
901 /* we need save vfio_dev_fd, so it can be used during release */
902 dev->intr_handle.vfio_dev_fd = vfio_dev_fd;
903 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
904 dev->vfio_req_intr_handle.vfio_dev_fd = vfio_dev_fd;
914 * map the PCI resources of a PCI device in virtual memory (VFIO version).
915 * primary and secondary processes follow almost exactly the same path
918 pci_vfio_map_resource(struct rte_pci_device *dev)
920 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
921 return pci_vfio_map_resource_primary(dev);
923 return pci_vfio_map_resource_secondary(dev);
926 static struct mapped_pci_resource *
927 find_and_unmap_vfio_resource(struct mapped_pci_res_list *vfio_res_list,
928 struct rte_pci_device *dev,
929 const char *pci_addr)
931 struct mapped_pci_resource *vfio_res = NULL;
932 struct pci_map *maps;
936 TAILQ_FOREACH(vfio_res, vfio_res_list, next) {
937 if (rte_pci_addr_cmp(&vfio_res->pci_addr, &dev->addr))
942 if (vfio_res == NULL)
945 RTE_LOG(INFO, EAL, "Releasing pci mapped resource for %s\n",
948 maps = vfio_res->maps;
949 for (i = 0; i < (int) vfio_res->nb_maps; i++) {
952 * We do not need to be aware of MSI-X table BAR mappings as
953 * when mapping. Just using current maps array is enough
956 RTE_LOG(INFO, EAL, "Calling pci_unmap_resource for %s at %p\n",
957 pci_addr, maps[i].addr);
958 pci_unmap_resource(maps[i].addr, maps[i].size);
966 pci_vfio_unmap_resource_primary(struct rte_pci_device *dev)
968 char pci_addr[PATH_MAX] = {0};
969 struct rte_pci_addr *loc = &dev->addr;
970 struct mapped_pci_resource *vfio_res = NULL;
971 struct mapped_pci_res_list *vfio_res_list;
974 /* store PCI address string */
975 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
976 loc->domain, loc->bus, loc->devid, loc->function);
978 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
979 ret = pci_vfio_disable_notifier(dev);
981 RTE_LOG(ERR, EAL, "fail to disable req notifier.\n");
986 if (close(dev->intr_handle.fd) < 0) {
987 RTE_LOG(INFO, EAL, "Error when closing eventfd file descriptor for %s\n",
992 if (pci_vfio_set_bus_master(dev->intr_handle.vfio_dev_fd, false)) {
993 RTE_LOG(ERR, EAL, " %s cannot unset bus mastering for PCI device!\n",
998 ret = rte_vfio_release_device(rte_pci_get_sysfs_path(), pci_addr,
999 dev->intr_handle.vfio_dev_fd);
1002 "%s(): cannot release device\n", __func__);
1007 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
1008 vfio_res = find_and_unmap_vfio_resource(vfio_res_list, dev, pci_addr);
1010 /* if we haven't found our tailq entry, something's wrong */
1011 if (vfio_res == NULL) {
1012 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
1017 TAILQ_REMOVE(vfio_res_list, vfio_res, next);
1023 pci_vfio_unmap_resource_secondary(struct rte_pci_device *dev)
1025 char pci_addr[PATH_MAX] = {0};
1026 struct rte_pci_addr *loc = &dev->addr;
1027 struct mapped_pci_resource *vfio_res = NULL;
1028 struct mapped_pci_res_list *vfio_res_list;
1031 /* store PCI address string */
1032 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
1033 loc->domain, loc->bus, loc->devid, loc->function);
1035 ret = rte_vfio_release_device(rte_pci_get_sysfs_path(), pci_addr,
1036 dev->intr_handle.vfio_dev_fd);
1039 "%s(): cannot release device\n", __func__);
1044 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
1045 vfio_res = find_and_unmap_vfio_resource(vfio_res_list, dev, pci_addr);
1047 /* if we haven't found our tailq entry, something's wrong */
1048 if (vfio_res == NULL) {
1049 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
1058 pci_vfio_unmap_resource(struct rte_pci_device *dev)
1060 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1061 return pci_vfio_unmap_resource_primary(dev);
1063 return pci_vfio_unmap_resource_secondary(dev);
1067 pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,
1068 struct rte_pci_ioport *p)
1070 if (bar < VFIO_PCI_BAR0_REGION_INDEX ||
1071 bar > VFIO_PCI_BAR5_REGION_INDEX) {
1072 RTE_LOG(ERR, EAL, "invalid bar (%d)!\n", bar);
1077 p->base = VFIO_GET_REGION_ADDR(bar);
1082 pci_vfio_ioport_read(struct rte_pci_ioport *p,
1083 void *data, size_t len, off_t offset)
1085 const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
1087 if (pread64(intr_handle->vfio_dev_fd, data,
1088 len, p->base + offset) <= 0)
1090 "Can't read from PCI bar (%" PRIu64 ") : offset (%x)\n",
1091 VFIO_GET_REGION_IDX(p->base), (int)offset);
1095 pci_vfio_ioport_write(struct rte_pci_ioport *p,
1096 const void *data, size_t len, off_t offset)
1098 const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
1100 if (pwrite64(intr_handle->vfio_dev_fd, data,
1101 len, p->base + offset) <= 0)
1103 "Can't write to PCI bar (%" PRIu64 ") : offset (%x)\n",
1104 VFIO_GET_REGION_IDX(p->base), (int)offset);
1108 pci_vfio_ioport_unmap(struct rte_pci_ioport *p)
1115 pci_vfio_is_enabled(void)
1117 return rte_vfio_is_enabled("vfio_pci");