1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2014 Intel Corporation
7 #include <linux/pci_regs.h>
8 #include <sys/eventfd.h>
9 #include <sys/socket.h>
10 #include <sys/ioctl.h>
16 #include <rte_bus_pci.h>
17 #include <rte_eal_memconfig.h>
18 #include <rte_malloc.h>
23 #include "eal_filesystem.h"
30 * PCI probing under linux (VFIO version)
32 * This code tries to determine if the PCI device is bound to VFIO driver,
33 * and initialize it (map BARs, set up interrupts) if that's the case.
35 * This file is only compiled if CONFIG_RTE_EAL_VFIO is set to "y".
40 #define PAGE_SIZE (sysconf(_SC_PAGESIZE))
41 #define PAGE_MASK (~(PAGE_SIZE - 1))
43 static struct rte_tailq_elem rte_vfio_tailq = {
44 .name = "VFIO_RESOURCE_LIST",
46 EAL_REGISTER_TAILQ(rte_vfio_tailq)
49 pci_vfio_read_config(const struct rte_intr_handle *intr_handle,
50 void *buf, size_t len, off_t offs)
52 return pread64(intr_handle->vfio_dev_fd, buf, len,
53 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
57 pci_vfio_write_config(const struct rte_intr_handle *intr_handle,
58 const void *buf, size_t len, off_t offs)
60 return pwrite64(intr_handle->vfio_dev_fd, buf, len,
61 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
64 /* get PCI BAR number where MSI-X interrupts are */
66 pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)
71 uint8_t cap_id, cap_offset;
73 /* read PCI capability pointer from config space */
74 ret = pread64(fd, ®, sizeof(reg),
75 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
77 if (ret != sizeof(reg)) {
78 RTE_LOG(ERR, EAL, "Cannot read capability pointer from PCI "
83 /* we need first byte */
84 cap_offset = reg & 0xFF;
88 /* read PCI capability ID */
89 ret = pread64(fd, ®, sizeof(reg),
90 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
92 if (ret != sizeof(reg)) {
93 RTE_LOG(ERR, EAL, "Cannot read capability ID from PCI "
98 /* we need first byte */
101 /* if we haven't reached MSI-X, check next capability */
102 if (cap_id != PCI_CAP_ID_MSIX) {
103 ret = pread64(fd, ®, sizeof(reg),
104 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
106 if (ret != sizeof(reg)) {
107 RTE_LOG(ERR, EAL, "Cannot read capability pointer from PCI "
112 /* we need second byte */
113 cap_offset = (reg & 0xFF00) >> 8;
117 /* else, read table offset */
119 /* table offset resides in the next 4 bytes */
120 ret = pread64(fd, ®, sizeof(reg),
121 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
123 if (ret != sizeof(reg)) {
124 RTE_LOG(ERR, EAL, "Cannot read table offset from PCI config "
129 ret = pread64(fd, &flags, sizeof(flags),
130 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
132 if (ret != sizeof(flags)) {
133 RTE_LOG(ERR, EAL, "Cannot read table flags from PCI config "
138 msix_table->bar_index = reg & RTE_PCI_MSIX_TABLE_BIR;
139 msix_table->offset = reg & RTE_PCI_MSIX_TABLE_OFFSET;
141 16 * (1 + (flags & RTE_PCI_MSIX_FLAGS_QSIZE));
149 /* set PCI bus mastering */
151 pci_vfio_set_bus_master(int dev_fd, bool op)
156 ret = pread64(dev_fd, ®, sizeof(reg),
157 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
159 if (ret != sizeof(reg)) {
160 RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n");
165 /* set the master bit */
166 reg |= PCI_COMMAND_MASTER;
168 reg &= ~(PCI_COMMAND_MASTER);
170 ret = pwrite64(dev_fd, ®, sizeof(reg),
171 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
174 if (ret != sizeof(reg)) {
175 RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n");
182 /* set up interrupt support (but not enable interrupts) */
184 pci_vfio_setup_interrupts(struct rte_pci_device *dev, int vfio_dev_fd)
186 int i, ret, intr_idx;
187 enum rte_intr_mode intr_mode;
189 /* default to invalid index */
190 intr_idx = VFIO_PCI_NUM_IRQS;
192 /* Get default / configured intr_mode */
193 intr_mode = rte_eal_vfio_intr_mode();
195 /* get interrupt type from internal config (MSI-X by default, can be
196 * overridden from the command line
199 case RTE_INTR_MODE_MSIX:
200 intr_idx = VFIO_PCI_MSIX_IRQ_INDEX;
202 case RTE_INTR_MODE_MSI:
203 intr_idx = VFIO_PCI_MSI_IRQ_INDEX;
205 case RTE_INTR_MODE_LEGACY:
206 intr_idx = VFIO_PCI_INTX_IRQ_INDEX;
208 /* don't do anything if we want to automatically determine interrupt type */
209 case RTE_INTR_MODE_NONE:
212 RTE_LOG(ERR, EAL, " unknown default interrupt type!\n");
216 /* start from MSI-X interrupt type */
217 for (i = VFIO_PCI_MSIX_IRQ_INDEX; i >= 0; i--) {
218 struct vfio_irq_info irq = { .argsz = sizeof(irq) };
221 /* skip interrupt modes we don't want */
222 if (intr_mode != RTE_INTR_MODE_NONE &&
228 ret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);
230 RTE_LOG(ERR, EAL, " cannot get IRQ info, "
231 "error %i (%s)\n", errno, strerror(errno));
235 /* if this vector cannot be used with eventfd, fail if we explicitly
236 * specified interrupt type, otherwise continue */
237 if ((irq.flags & VFIO_IRQ_INFO_EVENTFD) == 0) {
238 if (intr_mode != RTE_INTR_MODE_NONE) {
240 " interrupt vector does not support eventfd!\n");
246 /* set up an eventfd for interrupts */
247 fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);
249 RTE_LOG(ERR, EAL, " cannot set up eventfd, "
250 "error %i (%s)\n", errno, strerror(errno));
254 dev->intr_handle.fd = fd;
255 dev->intr_handle.vfio_dev_fd = vfio_dev_fd;
258 case VFIO_PCI_MSIX_IRQ_INDEX:
259 intr_mode = RTE_INTR_MODE_MSIX;
260 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
262 case VFIO_PCI_MSI_IRQ_INDEX:
263 intr_mode = RTE_INTR_MODE_MSI;
264 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSI;
266 case VFIO_PCI_INTX_IRQ_INDEX:
267 intr_mode = RTE_INTR_MODE_LEGACY;
268 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_LEGACY;
271 RTE_LOG(ERR, EAL, " unknown interrupt type!\n");
278 /* if we're here, we haven't found a suitable interrupt vector */
282 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
284 pci_vfio_req_handler(void *param)
288 struct rte_device *device = (struct rte_device *)param;
290 bus = rte_bus_find_by_device(device);
292 RTE_LOG(ERR, EAL, "Cannot find bus for device (%s)\n",
298 * vfio kernel module request user space to release allocated
299 * resources before device be deleted in kernel, so it can directly
300 * call the vfio bus hot-unplug handler to process it.
302 ret = bus->hot_unplug_handler(device);
305 "Can not handle hot-unplug for device (%s)\n",
309 /* enable notifier (only enable req now) */
311 pci_vfio_enable_notifier(struct rte_pci_device *dev, int vfio_dev_fd)
316 /* set up an eventfd for req notifier */
317 fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);
319 RTE_LOG(ERR, EAL, "Cannot set up eventfd, error %i (%s)\n",
320 errno, strerror(errno));
324 dev->vfio_req_intr_handle.fd = fd;
325 dev->vfio_req_intr_handle.type = RTE_INTR_HANDLE_VFIO_REQ;
326 dev->vfio_req_intr_handle.vfio_dev_fd = vfio_dev_fd;
328 ret = rte_intr_callback_register(&dev->vfio_req_intr_handle,
329 pci_vfio_req_handler,
330 (void *)&dev->device);
332 RTE_LOG(ERR, EAL, "Fail to register req notifier handler.\n");
336 ret = rte_intr_enable(&dev->vfio_req_intr_handle);
338 RTE_LOG(ERR, EAL, "Fail to enable req notifier.\n");
339 ret = rte_intr_callback_unregister(&dev->vfio_req_intr_handle,
340 pci_vfio_req_handler,
341 (void *)&dev->device);
344 "Fail to unregister req notifier handler.\n");
352 dev->vfio_req_intr_handle.fd = -1;
353 dev->vfio_req_intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
354 dev->vfio_req_intr_handle.vfio_dev_fd = -1;
359 /* disable notifier (only disable req now) */
361 pci_vfio_disable_notifier(struct rte_pci_device *dev)
365 ret = rte_intr_disable(&dev->vfio_req_intr_handle);
367 RTE_LOG(ERR, EAL, "fail to disable req notifier.\n");
371 ret = rte_intr_callback_unregister(&dev->vfio_req_intr_handle,
372 pci_vfio_req_handler,
373 (void *)&dev->device);
376 "fail to unregister req notifier handler.\n");
380 close(dev->vfio_req_intr_handle.fd);
382 dev->vfio_req_intr_handle.fd = -1;
383 dev->vfio_req_intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
384 dev->vfio_req_intr_handle.vfio_dev_fd = -1;
391 pci_vfio_is_ioport_bar(int vfio_dev_fd, int bar_index)
396 ret = pread64(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar),
397 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX)
398 + PCI_BASE_ADDRESS_0 + bar_index*4);
399 if (ret != sizeof(ioport_bar)) {
400 RTE_LOG(ERR, EAL, "Cannot read command (%x) from config space!\n",
401 PCI_BASE_ADDRESS_0 + bar_index*4);
405 return (ioport_bar & PCI_BASE_ADDRESS_SPACE_IO) != 0;
409 pci_rte_vfio_setup_device(struct rte_pci_device *dev, int vfio_dev_fd)
411 if (pci_vfio_setup_interrupts(dev, vfio_dev_fd) != 0) {
412 RTE_LOG(ERR, EAL, "Error setting up interrupts!\n");
416 /* set bus mastering for the device */
417 if (pci_vfio_set_bus_master(vfio_dev_fd, true)) {
418 RTE_LOG(ERR, EAL, "Cannot set up bus mastering!\n");
423 * Reset the device. If the device is not capable of resetting,
424 * then it updates errno as EINVAL.
426 if (ioctl(vfio_dev_fd, VFIO_DEVICE_RESET) && errno != EINVAL) {
427 RTE_LOG(ERR, EAL, "Unable to reset device! Error: %d (%s)\n",
428 errno, strerror(errno));
436 pci_vfio_mmap_bar(int vfio_dev_fd, struct mapped_pci_resource *vfio_res,
437 int bar_index, int additional_flags)
440 unsigned long offset, size;
443 struct pci_msix_table *msix_table = &vfio_res->msix_table;
444 struct pci_map *bar = &vfio_res->maps[bar_index];
450 if (msix_table->bar_index == bar_index) {
452 * VFIO will not let us map the MSI-X table,
453 * but we can map around it.
455 uint32_t table_start = msix_table->offset;
456 uint32_t table_end = table_start + msix_table->size;
457 table_end = (table_end + ~PAGE_MASK) & PAGE_MASK;
458 table_start &= PAGE_MASK;
460 if (table_start == 0 && table_end >= bar->size) {
461 /* Cannot map this BAR */
462 RTE_LOG(DEBUG, EAL, "Skipping BAR%d\n", bar_index);
468 memreg[0].offset = bar->offset;
469 memreg[0].size = table_start;
470 memreg[1].offset = bar->offset + table_end;
471 memreg[1].size = bar->size - table_end;
474 "Trying to map BAR%d that contains the MSI-X "
475 "table. Trying offsets: "
476 "0x%04lx:0x%04lx, 0x%04lx:0x%04lx\n", bar_index,
477 memreg[0].offset, memreg[0].size,
478 memreg[1].offset, memreg[1].size);
480 memreg[0].offset = bar->offset;
481 memreg[0].size = bar->size;
484 /* reserve the address using an inaccessible mapping */
485 bar_addr = mmap(bar->addr, bar->size, 0, MAP_PRIVATE |
486 MAP_ANONYMOUS | additional_flags, -1, 0);
487 if (bar_addr != MAP_FAILED) {
488 void *map_addr = NULL;
489 if (memreg[0].size) {
490 /* actual map of first part */
491 map_addr = pci_map_resource(bar_addr, vfio_dev_fd,
497 /* if there's a second part, try to map it */
498 if (map_addr != MAP_FAILED
499 && memreg[1].offset && memreg[1].size) {
500 void *second_addr = RTE_PTR_ADD(bar_addr,
502 (uintptr_t)bar->offset);
503 map_addr = pci_map_resource(second_addr,
510 if (map_addr == MAP_FAILED || !map_addr) {
511 munmap(bar_addr, bar->size);
512 bar_addr = MAP_FAILED;
513 RTE_LOG(ERR, EAL, "Failed to map pci BAR%d\n",
519 "Failed to create inaccessible mapping for BAR%d\n",
524 bar->addr = bar_addr;
529 * region info may contain capability headers, so we need to keep reallocating
530 * the memory until we match allocated memory size with argsz.
533 pci_vfio_get_region_info(int vfio_dev_fd, struct vfio_region_info **info,
536 struct vfio_region_info *ri;
537 size_t argsz = sizeof(*ri);
540 ri = malloc(sizeof(*ri));
542 RTE_LOG(ERR, EAL, "Cannot allocate memory for region info\n");
546 memset(ri, 0, argsz);
550 ret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ri);
555 if (ri->argsz != argsz) {
556 struct vfio_region_info *tmp;
559 tmp = realloc(ri, argsz);
562 /* realloc failed but the ri is still there */
564 RTE_LOG(ERR, EAL, "Cannot reallocate memory for region info\n");
575 static struct vfio_info_cap_header *
576 pci_vfio_info_cap(struct vfio_region_info *info, int cap)
578 struct vfio_info_cap_header *h;
581 if ((info->flags & RTE_VFIO_INFO_FLAG_CAPS) == 0) {
582 /* VFIO info does not advertise capabilities */
586 offset = VFIO_CAP_OFFSET(info);
587 while (offset != 0) {
588 h = RTE_PTR_ADD(info, offset);
597 pci_vfio_msix_is_mappable(int vfio_dev_fd, int msix_region)
599 struct vfio_region_info *info;
602 ret = pci_vfio_get_region_info(vfio_dev_fd, &info, msix_region);
606 ret = pci_vfio_info_cap(info, RTE_VFIO_CAP_MSIX_MAPPABLE) != NULL;
616 pci_vfio_map_resource_primary(struct rte_pci_device *dev)
618 struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
619 char pci_addr[PATH_MAX] = {0};
621 struct rte_pci_addr *loc = &dev->addr;
623 struct mapped_pci_resource *vfio_res = NULL;
624 struct mapped_pci_res_list *vfio_res_list =
625 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
627 struct pci_map *maps;
629 dev->intr_handle.fd = -1;
630 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
631 dev->vfio_req_intr_handle.fd = -1;
634 /* store PCI address string */
635 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
636 loc->domain, loc->bus, loc->devid, loc->function);
638 ret = rte_vfio_setup_device(rte_pci_get_sysfs_path(), pci_addr,
639 &vfio_dev_fd, &device_info);
643 /* allocate vfio_res and get region info */
644 vfio_res = rte_zmalloc("VFIO_RES", sizeof(*vfio_res), 0);
645 if (vfio_res == NULL) {
647 "%s(): cannot store uio mmap details\n", __func__);
648 goto err_vfio_dev_fd;
650 memcpy(&vfio_res->pci_addr, &dev->addr, sizeof(vfio_res->pci_addr));
652 /* get number of registers (up to BAR5) */
653 vfio_res->nb_maps = RTE_MIN((int) device_info.num_regions,
654 VFIO_PCI_BAR5_REGION_INDEX + 1);
657 maps = vfio_res->maps;
659 vfio_res->msix_table.bar_index = -1;
660 /* get MSI-X BAR, if any (we have to know where it is because we can't
661 * easily mmap it when using VFIO)
663 ret = pci_vfio_get_msix_bar(vfio_dev_fd, &vfio_res->msix_table);
665 RTE_LOG(ERR, EAL, " %s cannot get MSI-X BAR number!\n",
669 /* if we found our MSI-X BAR region, check if we can mmap it */
670 if (vfio_res->msix_table.bar_index != -1) {
671 int ret = pci_vfio_msix_is_mappable(vfio_dev_fd,
672 vfio_res->msix_table.bar_index);
674 RTE_LOG(ERR, EAL, "Couldn't check if MSI-X BAR is mappable\n");
676 } else if (ret != 0) {
677 /* we can map it, so we don't care where it is */
678 RTE_LOG(DEBUG, EAL, "VFIO reports MSI-X BAR as mappable\n");
679 vfio_res->msix_table.bar_index = -1;
683 for (i = 0; i < (int) vfio_res->nb_maps; i++) {
684 struct vfio_region_info *reg = NULL;
687 ret = pci_vfio_get_region_info(vfio_dev_fd, ®, i);
689 RTE_LOG(ERR, EAL, " %s cannot get device region info "
690 "error %i (%s)\n", pci_addr, errno,
695 /* chk for io port region */
696 ret = pci_vfio_is_ioport_bar(vfio_dev_fd, i);
701 RTE_LOG(INFO, EAL, "Ignore mapping IO port bar(%d)\n",
707 /* skip non-mmapable BARs */
708 if ((reg->flags & VFIO_REGION_INFO_FLAG_MMAP) == 0) {
713 /* try mapping somewhere close to the end of hugepages */
714 if (pci_map_addr == NULL)
715 pci_map_addr = pci_find_max_end_va();
717 bar_addr = pci_map_addr;
718 pci_map_addr = RTE_PTR_ADD(bar_addr, (size_t) reg->size);
720 maps[i].addr = bar_addr;
721 maps[i].offset = reg->offset;
722 maps[i].size = reg->size;
723 maps[i].path = NULL; /* vfio doesn't have per-resource paths */
725 ret = pci_vfio_mmap_bar(vfio_dev_fd, vfio_res, i, 0);
727 RTE_LOG(ERR, EAL, " %s mapping BAR%i failed: %s\n",
728 pci_addr, i, strerror(errno));
733 dev->mem_resource[i].addr = maps[i].addr;
738 if (pci_rte_vfio_setup_device(dev, vfio_dev_fd) < 0) {
739 RTE_LOG(ERR, EAL, " %s setup device failed\n", pci_addr);
743 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
744 if (pci_vfio_enable_notifier(dev, vfio_dev_fd) != 0) {
745 RTE_LOG(ERR, EAL, "Error setting up notifier!\n");
750 TAILQ_INSERT_TAIL(vfio_res_list, vfio_res, next);
761 pci_vfio_map_resource_secondary(struct rte_pci_device *dev)
763 struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
764 char pci_addr[PATH_MAX] = {0};
766 struct rte_pci_addr *loc = &dev->addr;
768 struct mapped_pci_resource *vfio_res = NULL;
769 struct mapped_pci_res_list *vfio_res_list =
770 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
772 struct pci_map *maps;
774 dev->intr_handle.fd = -1;
775 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
776 dev->vfio_req_intr_handle.fd = -1;
779 /* store PCI address string */
780 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
781 loc->domain, loc->bus, loc->devid, loc->function);
783 ret = rte_vfio_setup_device(rte_pci_get_sysfs_path(), pci_addr,
784 &vfio_dev_fd, &device_info);
788 /* if we're in a secondary process, just find our tailq entry */
789 TAILQ_FOREACH(vfio_res, vfio_res_list, next) {
790 if (rte_pci_addr_cmp(&vfio_res->pci_addr,
795 /* if we haven't found our tailq entry, something's wrong */
796 if (vfio_res == NULL) {
797 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
799 goto err_vfio_dev_fd;
803 maps = vfio_res->maps;
805 for (i = 0; i < (int) vfio_res->nb_maps; i++) {
806 ret = pci_vfio_mmap_bar(vfio_dev_fd, vfio_res, i, MAP_FIXED);
808 RTE_LOG(ERR, EAL, " %s mapping BAR%i failed: %s\n",
809 pci_addr, i, strerror(errno));
810 goto err_vfio_dev_fd;
813 dev->mem_resource[i].addr = maps[i].addr;
816 /* we need save vfio_dev_fd, so it can be used during release */
817 dev->intr_handle.vfio_dev_fd = vfio_dev_fd;
818 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
819 dev->vfio_req_intr_handle.vfio_dev_fd = vfio_dev_fd;
829 * map the PCI resources of a PCI device in virtual memory (VFIO version).
830 * primary and secondary processes follow almost exactly the same path
833 pci_vfio_map_resource(struct rte_pci_device *dev)
835 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
836 return pci_vfio_map_resource_primary(dev);
838 return pci_vfio_map_resource_secondary(dev);
841 static struct mapped_pci_resource *
842 find_and_unmap_vfio_resource(struct mapped_pci_res_list *vfio_res_list,
843 struct rte_pci_device *dev,
844 const char *pci_addr)
846 struct mapped_pci_resource *vfio_res = NULL;
847 struct pci_map *maps;
851 TAILQ_FOREACH(vfio_res, vfio_res_list, next) {
852 if (rte_pci_addr_cmp(&vfio_res->pci_addr, &dev->addr))
857 if (vfio_res == NULL)
860 RTE_LOG(INFO, EAL, "Releasing pci mapped resource for %s\n",
863 maps = vfio_res->maps;
864 for (i = 0; i < (int) vfio_res->nb_maps; i++) {
867 * We do not need to be aware of MSI-X table BAR mappings as
868 * when mapping. Just using current maps array is enough
871 RTE_LOG(INFO, EAL, "Calling pci_unmap_resource for %s at %p\n",
872 pci_addr, maps[i].addr);
873 pci_unmap_resource(maps[i].addr, maps[i].size);
881 pci_vfio_unmap_resource_primary(struct rte_pci_device *dev)
883 char pci_addr[PATH_MAX] = {0};
884 struct rte_pci_addr *loc = &dev->addr;
885 struct mapped_pci_resource *vfio_res = NULL;
886 struct mapped_pci_res_list *vfio_res_list;
889 /* store PCI address string */
890 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
891 loc->domain, loc->bus, loc->devid, loc->function);
893 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
894 ret = pci_vfio_disable_notifier(dev);
896 RTE_LOG(ERR, EAL, "fail to disable req notifier.\n");
901 if (close(dev->intr_handle.fd) < 0) {
902 RTE_LOG(INFO, EAL, "Error when closing eventfd file descriptor for %s\n",
907 if (pci_vfio_set_bus_master(dev->intr_handle.vfio_dev_fd, false)) {
908 RTE_LOG(ERR, EAL, " %s cannot unset bus mastering for PCI device!\n",
913 ret = rte_vfio_release_device(rte_pci_get_sysfs_path(), pci_addr,
914 dev->intr_handle.vfio_dev_fd);
917 "%s(): cannot release device\n", __func__);
922 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
923 vfio_res = find_and_unmap_vfio_resource(vfio_res_list, dev, pci_addr);
925 /* if we haven't found our tailq entry, something's wrong */
926 if (vfio_res == NULL) {
927 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
932 TAILQ_REMOVE(vfio_res_list, vfio_res, next);
938 pci_vfio_unmap_resource_secondary(struct rte_pci_device *dev)
940 char pci_addr[PATH_MAX] = {0};
941 struct rte_pci_addr *loc = &dev->addr;
942 struct mapped_pci_resource *vfio_res = NULL;
943 struct mapped_pci_res_list *vfio_res_list;
946 /* store PCI address string */
947 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
948 loc->domain, loc->bus, loc->devid, loc->function);
950 ret = rte_vfio_release_device(rte_pci_get_sysfs_path(), pci_addr,
951 dev->intr_handle.vfio_dev_fd);
954 "%s(): cannot release device\n", __func__);
959 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
960 vfio_res = find_and_unmap_vfio_resource(vfio_res_list, dev, pci_addr);
962 /* if we haven't found our tailq entry, something's wrong */
963 if (vfio_res == NULL) {
964 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
973 pci_vfio_unmap_resource(struct rte_pci_device *dev)
975 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
976 return pci_vfio_unmap_resource_primary(dev);
978 return pci_vfio_unmap_resource_secondary(dev);
982 pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,
983 struct rte_pci_ioport *p)
985 if (bar < VFIO_PCI_BAR0_REGION_INDEX ||
986 bar > VFIO_PCI_BAR5_REGION_INDEX) {
987 RTE_LOG(ERR, EAL, "invalid bar (%d)!\n", bar);
992 p->base = VFIO_GET_REGION_ADDR(bar);
997 pci_vfio_ioport_read(struct rte_pci_ioport *p,
998 void *data, size_t len, off_t offset)
1000 const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
1002 if (pread64(intr_handle->vfio_dev_fd, data,
1003 len, p->base + offset) <= 0)
1005 "Can't read from PCI bar (%" PRIu64 ") : offset (%x)\n",
1006 VFIO_GET_REGION_IDX(p->base), (int)offset);
1010 pci_vfio_ioport_write(struct rte_pci_ioport *p,
1011 const void *data, size_t len, off_t offset)
1013 const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
1015 if (pwrite64(intr_handle->vfio_dev_fd, data,
1016 len, p->base + offset) <= 0)
1018 "Can't write to PCI bar (%" PRIu64 ") : offset (%x)\n",
1019 VFIO_GET_REGION_IDX(p->base), (int)offset);
1023 pci_vfio_ioport_unmap(struct rte_pci_ioport *p)
1030 pci_vfio_is_enabled(void)
1032 return rte_vfio_is_enabled("vfio_pci");