1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2014 Intel Corporation
7 #include <linux/pci_regs.h>
8 #include <sys/eventfd.h>
9 #include <sys/socket.h>
10 #include <sys/ioctl.h>
16 #include <rte_bus_pci.h>
17 #include <rte_eal_paging.h>
18 #include <rte_malloc.h>
22 #include <rte_spinlock.h>
23 #include <rte_tailq.h>
25 #include "eal_filesystem.h"
32 * PCI probing under linux (VFIO version)
34 * This code tries to determine if the PCI device is bound to VFIO driver,
35 * and initialize it (map BARs, set up interrupts) if that's the case.
41 static struct rte_tailq_elem rte_vfio_tailq = {
42 .name = "VFIO_RESOURCE_LIST",
44 EAL_REGISTER_TAILQ(rte_vfio_tailq)
47 pci_vfio_read_config(const struct rte_intr_handle *intr_handle,
48 void *buf, size_t len, off_t offs)
50 return pread64(intr_handle->vfio_dev_fd, buf, len,
51 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
55 pci_vfio_write_config(const struct rte_intr_handle *intr_handle,
56 const void *buf, size_t len, off_t offs)
58 return pwrite64(intr_handle->vfio_dev_fd, buf, len,
59 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
62 /* get PCI BAR number where MSI-X interrupts are */
64 pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)
69 uint8_t cap_id, cap_offset;
71 /* read PCI capability pointer from config space */
72 ret = pread64(fd, ®, sizeof(reg),
73 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
75 if (ret != sizeof(reg)) {
76 RTE_LOG(ERR, EAL, "Cannot read capability pointer from PCI "
81 /* we need first byte */
82 cap_offset = reg & 0xFF;
86 /* read PCI capability ID */
87 ret = pread64(fd, ®, sizeof(reg),
88 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
90 if (ret != sizeof(reg)) {
91 RTE_LOG(ERR, EAL, "Cannot read capability ID from PCI "
96 /* we need first byte */
99 /* if we haven't reached MSI-X, check next capability */
100 if (cap_id != PCI_CAP_ID_MSIX) {
101 ret = pread64(fd, ®, sizeof(reg),
102 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
104 if (ret != sizeof(reg)) {
105 RTE_LOG(ERR, EAL, "Cannot read capability pointer from PCI "
110 /* we need second byte */
111 cap_offset = (reg & 0xFF00) >> 8;
115 /* else, read table offset */
117 /* table offset resides in the next 4 bytes */
118 ret = pread64(fd, ®, sizeof(reg),
119 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
121 if (ret != sizeof(reg)) {
122 RTE_LOG(ERR, EAL, "Cannot read table offset from PCI config "
127 ret = pread64(fd, &flags, sizeof(flags),
128 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
130 if (ret != sizeof(flags)) {
131 RTE_LOG(ERR, EAL, "Cannot read table flags from PCI config "
136 msix_table->bar_index = reg & RTE_PCI_MSIX_TABLE_BIR;
137 msix_table->offset = reg & RTE_PCI_MSIX_TABLE_OFFSET;
139 16 * (1 + (flags & RTE_PCI_MSIX_FLAGS_QSIZE));
147 /* enable PCI bus memory space */
149 pci_vfio_enable_bus_memory(int dev_fd)
154 ret = pread64(dev_fd, &cmd, sizeof(cmd),
155 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
158 if (ret != sizeof(cmd)) {
159 RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n");
163 if (cmd & PCI_COMMAND_MEMORY)
166 cmd |= PCI_COMMAND_MEMORY;
167 ret = pwrite64(dev_fd, &cmd, sizeof(cmd),
168 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
171 if (ret != sizeof(cmd)) {
172 RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n");
179 /* set PCI bus mastering */
181 pci_vfio_set_bus_master(int dev_fd, bool op)
186 ret = pread64(dev_fd, ®, sizeof(reg),
187 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
189 if (ret != sizeof(reg)) {
190 RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n");
195 /* set the master bit */
196 reg |= PCI_COMMAND_MASTER;
198 reg &= ~(PCI_COMMAND_MASTER);
200 ret = pwrite64(dev_fd, ®, sizeof(reg),
201 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
204 if (ret != sizeof(reg)) {
205 RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n");
212 /* set up interrupt support (but not enable interrupts) */
214 pci_vfio_setup_interrupts(struct rte_pci_device *dev, int vfio_dev_fd)
216 int i, ret, intr_idx;
217 enum rte_intr_mode intr_mode;
219 /* default to invalid index */
220 intr_idx = VFIO_PCI_NUM_IRQS;
222 /* Get default / configured intr_mode */
223 intr_mode = rte_eal_vfio_intr_mode();
225 /* get interrupt type from internal config (MSI-X by default, can be
226 * overridden from the command line
229 case RTE_INTR_MODE_MSIX:
230 intr_idx = VFIO_PCI_MSIX_IRQ_INDEX;
232 case RTE_INTR_MODE_MSI:
233 intr_idx = VFIO_PCI_MSI_IRQ_INDEX;
235 case RTE_INTR_MODE_LEGACY:
236 intr_idx = VFIO_PCI_INTX_IRQ_INDEX;
238 /* don't do anything if we want to automatically determine interrupt type */
239 case RTE_INTR_MODE_NONE:
242 RTE_LOG(ERR, EAL, " unknown default interrupt type!\n");
246 /* start from MSI-X interrupt type */
247 for (i = VFIO_PCI_MSIX_IRQ_INDEX; i >= 0; i--) {
248 struct vfio_irq_info irq = { .argsz = sizeof(irq) };
251 /* skip interrupt modes we don't want */
252 if (intr_mode != RTE_INTR_MODE_NONE &&
258 ret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);
260 RTE_LOG(ERR, EAL, " cannot get IRQ info, "
261 "error %i (%s)\n", errno, strerror(errno));
265 /* if this vector cannot be used with eventfd, fail if we explicitly
266 * specified interrupt type, otherwise continue */
267 if ((irq.flags & VFIO_IRQ_INFO_EVENTFD) == 0) {
268 if (intr_mode != RTE_INTR_MODE_NONE) {
270 " interrupt vector does not support eventfd!\n");
276 /* set up an eventfd for interrupts */
277 fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);
279 RTE_LOG(ERR, EAL, " cannot set up eventfd, "
280 "error %i (%s)\n", errno, strerror(errno));
284 dev->intr_handle.fd = fd;
285 dev->intr_handle.vfio_dev_fd = vfio_dev_fd;
288 case VFIO_PCI_MSIX_IRQ_INDEX:
289 intr_mode = RTE_INTR_MODE_MSIX;
290 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
292 case VFIO_PCI_MSI_IRQ_INDEX:
293 intr_mode = RTE_INTR_MODE_MSI;
294 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSI;
296 case VFIO_PCI_INTX_IRQ_INDEX:
297 intr_mode = RTE_INTR_MODE_LEGACY;
298 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_LEGACY;
301 RTE_LOG(ERR, EAL, " unknown interrupt type!\n");
308 /* if we're here, we haven't found a suitable interrupt vector */
312 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
314 * Spinlock for device hot-unplug failure handling.
315 * If it tries to access bus or device, such as handle sigbus on bus
316 * or handle memory failure for device, just need to use this lock.
317 * It could protect the bus and the device to avoid race condition.
319 static rte_spinlock_t failure_handle_lock = RTE_SPINLOCK_INITIALIZER;
322 pci_vfio_req_handler(void *param)
326 struct rte_device *device = (struct rte_device *)param;
328 rte_spinlock_lock(&failure_handle_lock);
329 bus = rte_bus_find_by_device(device);
331 RTE_LOG(ERR, EAL, "Cannot find bus for device (%s)\n",
337 * vfio kernel module request user space to release allocated
338 * resources before device be deleted in kernel, so it can directly
339 * call the vfio bus hot-unplug handler to process it.
341 ret = bus->hot_unplug_handler(device);
344 "Can not handle hot-unplug for device (%s)\n",
347 rte_spinlock_unlock(&failure_handle_lock);
350 /* enable notifier (only enable req now) */
352 pci_vfio_enable_notifier(struct rte_pci_device *dev, int vfio_dev_fd)
357 /* set up an eventfd for req notifier */
358 fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);
360 RTE_LOG(ERR, EAL, "Cannot set up eventfd, error %i (%s)\n",
361 errno, strerror(errno));
365 dev->vfio_req_intr_handle.fd = fd;
366 dev->vfio_req_intr_handle.type = RTE_INTR_HANDLE_VFIO_REQ;
367 dev->vfio_req_intr_handle.vfio_dev_fd = vfio_dev_fd;
369 ret = rte_intr_callback_register(&dev->vfio_req_intr_handle,
370 pci_vfio_req_handler,
371 (void *)&dev->device);
373 RTE_LOG(ERR, EAL, "Fail to register req notifier handler.\n");
377 ret = rte_intr_enable(&dev->vfio_req_intr_handle);
379 RTE_LOG(ERR, EAL, "Fail to enable req notifier.\n");
380 ret = rte_intr_callback_unregister(&dev->vfio_req_intr_handle,
381 pci_vfio_req_handler,
382 (void *)&dev->device);
385 "Fail to unregister req notifier handler.\n");
393 dev->vfio_req_intr_handle.fd = -1;
394 dev->vfio_req_intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
395 dev->vfio_req_intr_handle.vfio_dev_fd = -1;
400 /* disable notifier (only disable req now) */
402 pci_vfio_disable_notifier(struct rte_pci_device *dev)
406 ret = rte_intr_disable(&dev->vfio_req_intr_handle);
408 RTE_LOG(ERR, EAL, "fail to disable req notifier.\n");
412 ret = rte_intr_callback_unregister_sync(&dev->vfio_req_intr_handle,
413 pci_vfio_req_handler,
414 (void *)&dev->device);
417 "fail to unregister req notifier handler.\n");
421 close(dev->vfio_req_intr_handle.fd);
423 dev->vfio_req_intr_handle.fd = -1;
424 dev->vfio_req_intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
425 dev->vfio_req_intr_handle.vfio_dev_fd = -1;
432 pci_vfio_is_ioport_bar(int vfio_dev_fd, int bar_index)
437 ret = pread64(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar),
438 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX)
439 + PCI_BASE_ADDRESS_0 + bar_index*4);
440 if (ret != sizeof(ioport_bar)) {
441 RTE_LOG(ERR, EAL, "Cannot read command (%x) from config space!\n",
442 PCI_BASE_ADDRESS_0 + bar_index*4);
446 return (ioport_bar & PCI_BASE_ADDRESS_SPACE_IO) != 0;
450 pci_rte_vfio_setup_device(struct rte_pci_device *dev, int vfio_dev_fd)
452 if (pci_vfio_setup_interrupts(dev, vfio_dev_fd) != 0) {
453 RTE_LOG(ERR, EAL, "Error setting up interrupts!\n");
457 if (pci_vfio_enable_bus_memory(vfio_dev_fd)) {
458 RTE_LOG(ERR, EAL, "Cannot enable bus memory!\n");
462 /* set bus mastering for the device */
463 if (pci_vfio_set_bus_master(vfio_dev_fd, true)) {
464 RTE_LOG(ERR, EAL, "Cannot set up bus mastering!\n");
469 * Reset the device. If the device is not capable of resetting,
470 * then it updates errno as EINVAL.
472 if (ioctl(vfio_dev_fd, VFIO_DEVICE_RESET) && errno != EINVAL) {
473 RTE_LOG(ERR, EAL, "Unable to reset device! Error: %d (%s)\n",
474 errno, strerror(errno));
482 pci_vfio_mmap_bar(int vfio_dev_fd, struct mapped_pci_resource *vfio_res,
483 int bar_index, int additional_flags)
490 struct pci_msix_table *msix_table = &vfio_res->msix_table;
491 struct pci_map *bar = &vfio_res->maps[bar_index];
493 if (bar->size == 0) {
494 RTE_LOG(DEBUG, EAL, "Bar size is 0, skip BAR%d\n", bar_index);
498 if (msix_table->bar_index == bar_index) {
500 * VFIO will not let us map the MSI-X table,
501 * but we can map around it.
503 uint32_t table_start = msix_table->offset;
504 uint32_t table_end = table_start + msix_table->size;
505 table_end = RTE_ALIGN(table_end, rte_mem_page_size());
506 table_start = RTE_ALIGN_FLOOR(table_start, rte_mem_page_size());
508 /* If page-aligned start of MSI-X table is less than the
509 * actual MSI-X table start address, reassign to the actual
512 if (table_start < msix_table->offset)
513 table_start = msix_table->offset;
515 if (table_start == 0 && table_end >= bar->size) {
516 /* Cannot map this BAR */
517 RTE_LOG(DEBUG, EAL, "Skipping BAR%d\n", bar_index);
523 memreg[0].offset = bar->offset;
524 memreg[0].size = table_start;
525 if (bar->size < table_end) {
527 * If MSI-X table end is beyond BAR end, don't attempt
528 * to perform second mapping.
530 memreg[1].offset = 0;
533 memreg[1].offset = bar->offset + table_end;
534 memreg[1].size = bar->size - table_end;
538 "Trying to map BAR%d that contains the MSI-X "
539 "table. Trying offsets: "
540 "0x%04" PRIx64 ":0x%04zx, 0x%04" PRIx64 ":0x%04zx\n",
542 memreg[0].offset, memreg[0].size,
543 memreg[1].offset, memreg[1].size);
545 memreg[0].offset = bar->offset;
546 memreg[0].size = bar->size;
549 /* reserve the address using an inaccessible mapping */
550 bar_addr = mmap(bar->addr, bar->size, 0, MAP_PRIVATE |
551 MAP_ANONYMOUS | additional_flags, -1, 0);
552 if (bar_addr != MAP_FAILED) {
553 void *map_addr = NULL;
554 if (memreg[0].size) {
555 /* actual map of first part */
556 map_addr = pci_map_resource(bar_addr, vfio_dev_fd,
559 RTE_MAP_FORCE_ADDRESS);
563 * Regarding "memreg[0].size == 0":
564 * If this BAR has MSI-X table, memreg[0].size (the
565 * first part or the part before the table) can
566 * legitimately be 0 for hardware using vector table
567 * offset 0 (i.e. first part does not exist).
569 * When memreg[0].size is 0, "mapping the first part"
570 * never happens, and map_addr is NULL at this
571 * point. So check that mapping has been actually
574 /* if there's a second part, try to map it */
575 if ((map_addr != NULL || memreg[0].size == 0)
576 && memreg[1].offset && memreg[1].size) {
577 void *second_addr = RTE_PTR_ADD(bar_addr,
578 (uintptr_t)(memreg[1].offset -
580 map_addr = pci_map_resource(second_addr,
584 RTE_MAP_FORCE_ADDRESS);
587 if (map_addr == NULL) {
588 munmap(bar_addr, bar->size);
589 bar_addr = MAP_FAILED;
590 RTE_LOG(ERR, EAL, "Failed to map pci BAR%d\n",
596 "Failed to create inaccessible mapping for BAR%d\n",
601 bar->addr = bar_addr;
606 * region info may contain capability headers, so we need to keep reallocating
607 * the memory until we match allocated memory size with argsz.
610 pci_vfio_get_region_info(int vfio_dev_fd, struct vfio_region_info **info,
613 struct vfio_region_info *ri;
614 size_t argsz = sizeof(*ri);
617 ri = malloc(sizeof(*ri));
619 RTE_LOG(ERR, EAL, "Cannot allocate memory for region info\n");
623 memset(ri, 0, argsz);
627 ret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ri);
632 if (ri->argsz != argsz) {
633 struct vfio_region_info *tmp;
636 tmp = realloc(ri, argsz);
639 /* realloc failed but the ri is still there */
641 RTE_LOG(ERR, EAL, "Cannot reallocate memory for region info\n");
652 static struct vfio_info_cap_header *
653 pci_vfio_info_cap(struct vfio_region_info *info, int cap)
655 struct vfio_info_cap_header *h;
658 if ((info->flags & RTE_VFIO_INFO_FLAG_CAPS) == 0) {
659 /* VFIO info does not advertise capabilities */
663 offset = VFIO_CAP_OFFSET(info);
664 while (offset != 0) {
665 h = RTE_PTR_ADD(info, offset);
674 pci_vfio_msix_is_mappable(int vfio_dev_fd, int msix_region)
676 struct vfio_region_info *info;
679 ret = pci_vfio_get_region_info(vfio_dev_fd, &info, msix_region);
683 ret = pci_vfio_info_cap(info, RTE_VFIO_CAP_MSIX_MAPPABLE) != NULL;
693 pci_vfio_map_resource_primary(struct rte_pci_device *dev)
695 struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
696 char pci_addr[PATH_MAX] = {0};
698 struct rte_pci_addr *loc = &dev->addr;
700 struct mapped_pci_resource *vfio_res = NULL;
701 struct mapped_pci_res_list *vfio_res_list =
702 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
704 struct pci_map *maps;
706 dev->intr_handle.fd = -1;
707 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
708 dev->vfio_req_intr_handle.fd = -1;
711 /* store PCI address string */
712 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
713 loc->domain, loc->bus, loc->devid, loc->function);
715 ret = rte_vfio_setup_device(rte_pci_get_sysfs_path(), pci_addr,
716 &vfio_dev_fd, &device_info);
720 /* allocate vfio_res and get region info */
721 vfio_res = rte_zmalloc("VFIO_RES", sizeof(*vfio_res), 0);
722 if (vfio_res == NULL) {
724 "%s(): cannot store vfio mmap details\n", __func__);
725 goto err_vfio_dev_fd;
727 memcpy(&vfio_res->pci_addr, &dev->addr, sizeof(vfio_res->pci_addr));
729 /* get number of registers (up to BAR5) */
730 vfio_res->nb_maps = RTE_MIN((int) device_info.num_regions,
731 VFIO_PCI_BAR5_REGION_INDEX + 1);
734 maps = vfio_res->maps;
736 vfio_res->msix_table.bar_index = -1;
737 /* get MSI-X BAR, if any (we have to know where it is because we can't
738 * easily mmap it when using VFIO)
740 ret = pci_vfio_get_msix_bar(vfio_dev_fd, &vfio_res->msix_table);
742 RTE_LOG(ERR, EAL, " %s cannot get MSI-X BAR number!\n",
746 /* if we found our MSI-X BAR region, check if we can mmap it */
747 if (vfio_res->msix_table.bar_index != -1) {
748 int ret = pci_vfio_msix_is_mappable(vfio_dev_fd,
749 vfio_res->msix_table.bar_index);
751 RTE_LOG(ERR, EAL, "Couldn't check if MSI-X BAR is mappable\n");
753 } else if (ret != 0) {
754 /* we can map it, so we don't care where it is */
755 RTE_LOG(DEBUG, EAL, "VFIO reports MSI-X BAR as mappable\n");
756 vfio_res->msix_table.bar_index = -1;
760 for (i = 0; i < vfio_res->nb_maps; i++) {
761 struct vfio_region_info *reg = NULL;
764 ret = pci_vfio_get_region_info(vfio_dev_fd, ®, i);
766 RTE_LOG(ERR, EAL, " %s cannot get device region info "
767 "error %i (%s)\n", pci_addr, errno,
772 /* chk for io port region */
773 ret = pci_vfio_is_ioport_bar(vfio_dev_fd, i);
778 RTE_LOG(INFO, EAL, "Ignore mapping IO port bar(%d)\n",
784 /* skip non-mmapable BARs */
785 if ((reg->flags & VFIO_REGION_INFO_FLAG_MMAP) == 0) {
790 /* try mapping somewhere close to the end of hugepages */
791 if (pci_map_addr == NULL)
792 pci_map_addr = pci_find_max_end_va();
794 bar_addr = pci_map_addr;
795 pci_map_addr = RTE_PTR_ADD(bar_addr, (size_t) reg->size);
797 pci_map_addr = RTE_PTR_ALIGN(pci_map_addr,
798 sysconf(_SC_PAGE_SIZE));
800 maps[i].addr = bar_addr;
801 maps[i].offset = reg->offset;
802 maps[i].size = reg->size;
803 maps[i].path = NULL; /* vfio doesn't have per-resource paths */
805 ret = pci_vfio_mmap_bar(vfio_dev_fd, vfio_res, i, 0);
807 RTE_LOG(ERR, EAL, " %s mapping BAR%i failed: %s\n",
808 pci_addr, i, strerror(errno));
813 dev->mem_resource[i].addr = maps[i].addr;
818 if (pci_rte_vfio_setup_device(dev, vfio_dev_fd) < 0) {
819 RTE_LOG(ERR, EAL, " %s setup device failed\n", pci_addr);
823 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
824 if (pci_vfio_enable_notifier(dev, vfio_dev_fd) != 0) {
825 RTE_LOG(ERR, EAL, "Error setting up notifier!\n");
830 TAILQ_INSERT_TAIL(vfio_res_list, vfio_res, next);
836 rte_vfio_release_device(rte_pci_get_sysfs_path(),
837 pci_addr, vfio_dev_fd);
842 pci_vfio_map_resource_secondary(struct rte_pci_device *dev)
844 struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
845 char pci_addr[PATH_MAX] = {0};
847 struct rte_pci_addr *loc = &dev->addr;
849 struct mapped_pci_resource *vfio_res = NULL;
850 struct mapped_pci_res_list *vfio_res_list =
851 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
853 struct pci_map *maps;
855 dev->intr_handle.fd = -1;
856 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
857 dev->vfio_req_intr_handle.fd = -1;
860 /* store PCI address string */
861 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
862 loc->domain, loc->bus, loc->devid, loc->function);
864 /* if we're in a secondary process, just find our tailq entry */
865 TAILQ_FOREACH(vfio_res, vfio_res_list, next) {
866 if (rte_pci_addr_cmp(&vfio_res->pci_addr,
871 /* if we haven't found our tailq entry, something's wrong */
872 if (vfio_res == NULL) {
873 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
878 ret = rte_vfio_setup_device(rte_pci_get_sysfs_path(), pci_addr,
879 &vfio_dev_fd, &device_info);
884 maps = vfio_res->maps;
886 for (i = 0; i < vfio_res->nb_maps; i++) {
887 ret = pci_vfio_mmap_bar(vfio_dev_fd, vfio_res, i, MAP_FIXED);
889 RTE_LOG(ERR, EAL, " %s mapping BAR%i failed: %s\n",
890 pci_addr, i, strerror(errno));
891 goto err_vfio_dev_fd;
894 dev->mem_resource[i].addr = maps[i].addr;
897 /* we need save vfio_dev_fd, so it can be used during release */
898 dev->intr_handle.vfio_dev_fd = vfio_dev_fd;
899 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
900 dev->vfio_req_intr_handle.vfio_dev_fd = vfio_dev_fd;
905 rte_vfio_release_device(rte_pci_get_sysfs_path(),
906 pci_addr, vfio_dev_fd);
911 * map the PCI resources of a PCI device in virtual memory (VFIO version).
912 * primary and secondary processes follow almost exactly the same path
915 pci_vfio_map_resource(struct rte_pci_device *dev)
917 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
918 return pci_vfio_map_resource_primary(dev);
920 return pci_vfio_map_resource_secondary(dev);
923 static struct mapped_pci_resource *
924 find_and_unmap_vfio_resource(struct mapped_pci_res_list *vfio_res_list,
925 struct rte_pci_device *dev,
926 const char *pci_addr)
928 struct mapped_pci_resource *vfio_res = NULL;
929 struct pci_map *maps;
933 TAILQ_FOREACH(vfio_res, vfio_res_list, next) {
934 if (rte_pci_addr_cmp(&vfio_res->pci_addr, &dev->addr))
939 if (vfio_res == NULL)
942 RTE_LOG(INFO, EAL, "Releasing pci mapped resource for %s\n",
945 maps = vfio_res->maps;
946 for (i = 0; i < vfio_res->nb_maps; i++) {
949 * We do not need to be aware of MSI-X table BAR mappings as
950 * when mapping. Just using current maps array is enough
953 RTE_LOG(INFO, EAL, "Calling pci_unmap_resource for %s at %p\n",
954 pci_addr, maps[i].addr);
955 pci_unmap_resource(maps[i].addr, maps[i].size);
963 pci_vfio_unmap_resource_primary(struct rte_pci_device *dev)
965 char pci_addr[PATH_MAX] = {0};
966 struct rte_pci_addr *loc = &dev->addr;
967 struct mapped_pci_resource *vfio_res = NULL;
968 struct mapped_pci_res_list *vfio_res_list;
971 /* store PCI address string */
972 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
973 loc->domain, loc->bus, loc->devid, loc->function);
975 #ifdef HAVE_VFIO_DEV_REQ_INTERFACE
976 ret = pci_vfio_disable_notifier(dev);
978 RTE_LOG(ERR, EAL, "fail to disable req notifier.\n");
983 if (close(dev->intr_handle.fd) < 0) {
984 RTE_LOG(INFO, EAL, "Error when closing eventfd file descriptor for %s\n",
989 if (pci_vfio_set_bus_master(dev->intr_handle.vfio_dev_fd, false)) {
990 RTE_LOG(ERR, EAL, " %s cannot unset bus mastering for PCI device!\n",
995 ret = rte_vfio_release_device(rte_pci_get_sysfs_path(), pci_addr,
996 dev->intr_handle.vfio_dev_fd);
999 "%s(): cannot release device\n", __func__);
1004 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
1005 vfio_res = find_and_unmap_vfio_resource(vfio_res_list, dev, pci_addr);
1007 /* if we haven't found our tailq entry, something's wrong */
1008 if (vfio_res == NULL) {
1009 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
1014 TAILQ_REMOVE(vfio_res_list, vfio_res, next);
1020 pci_vfio_unmap_resource_secondary(struct rte_pci_device *dev)
1022 char pci_addr[PATH_MAX] = {0};
1023 struct rte_pci_addr *loc = &dev->addr;
1024 struct mapped_pci_resource *vfio_res = NULL;
1025 struct mapped_pci_res_list *vfio_res_list;
1028 /* store PCI address string */
1029 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
1030 loc->domain, loc->bus, loc->devid, loc->function);
1032 ret = rte_vfio_release_device(rte_pci_get_sysfs_path(), pci_addr,
1033 dev->intr_handle.vfio_dev_fd);
1036 "%s(): cannot release device\n", __func__);
1041 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
1042 vfio_res = find_and_unmap_vfio_resource(vfio_res_list, dev, pci_addr);
1044 /* if we haven't found our tailq entry, something's wrong */
1045 if (vfio_res == NULL) {
1046 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
1055 pci_vfio_unmap_resource(struct rte_pci_device *dev)
1057 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1058 return pci_vfio_unmap_resource_primary(dev);
1060 return pci_vfio_unmap_resource_secondary(dev);
1064 pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,
1065 struct rte_pci_ioport *p)
1067 if (bar < VFIO_PCI_BAR0_REGION_INDEX ||
1068 bar > VFIO_PCI_BAR5_REGION_INDEX) {
1069 RTE_LOG(ERR, EAL, "invalid bar (%d)!\n", bar);
1074 p->base = VFIO_GET_REGION_ADDR(bar);
1079 pci_vfio_ioport_read(struct rte_pci_ioport *p,
1080 void *data, size_t len, off_t offset)
1082 const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
1084 if (pread64(intr_handle->vfio_dev_fd, data,
1085 len, p->base + offset) <= 0)
1087 "Can't read from PCI bar (%" PRIu64 ") : offset (%x)\n",
1088 VFIO_GET_REGION_IDX(p->base), (int)offset);
1092 pci_vfio_ioport_write(struct rte_pci_ioport *p,
1093 const void *data, size_t len, off_t offset)
1095 const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
1097 if (pwrite64(intr_handle->vfio_dev_fd, data,
1098 len, p->base + offset) <= 0)
1100 "Can't write to PCI bar (%" PRIu64 ") : offset (%x)\n",
1101 VFIO_GET_REGION_IDX(p->base), (int)offset);
1105 pci_vfio_ioport_unmap(struct rte_pci_ioport *p)
1112 pci_vfio_is_enabled(void)
1114 return rte_vfio_is_enabled("vfio_pci");