1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
10 #define NPA_AF_BLK_RST (0x0ull)
11 #define NPA_AF_CONST (0x10ull)
12 #define NPA_AF_CONST1 (0x18ull)
13 #define NPA_AF_LF_RST (0x20ull)
14 #define NPA_AF_GEN_CFG (0x30ull)
15 #define NPA_AF_NDC_CFG (0x40ull)
16 #define NPA_AF_NDC_SYNC (0x50ull)
17 #define NPA_AF_INP_CTL (0xd0ull)
18 #define NPA_AF_ACTIVE_CYCLES_PC (0xf0ull)
19 #define NPA_AF_AVG_DELAY (0x100ull)
20 #define NPA_AF_GEN_INT (0x140ull)
21 #define NPA_AF_GEN_INT_W1S (0x148ull)
22 #define NPA_AF_GEN_INT_ENA_W1S (0x150ull)
23 #define NPA_AF_GEN_INT_ENA_W1C (0x158ull)
24 #define NPA_AF_RVU_INT (0x160ull)
25 #define NPA_AF_RVU_INT_W1S (0x168ull)
26 #define NPA_AF_RVU_INT_ENA_W1S (0x170ull)
27 #define NPA_AF_RVU_INT_ENA_W1C (0x178ull)
28 #define NPA_AF_ERR_INT (0x180ull)
29 #define NPA_AF_ERR_INT_W1S (0x188ull)
30 #define NPA_AF_ERR_INT_ENA_W1S (0x190ull)
31 #define NPA_AF_ERR_INT_ENA_W1C (0x198ull)
32 #define NPA_AF_RAS (0x1a0ull)
33 #define NPA_AF_RAS_W1S (0x1a8ull)
34 #define NPA_AF_RAS_ENA_W1S (0x1b0ull)
35 #define NPA_AF_RAS_ENA_W1C (0x1b8ull)
36 #define NPA_AF_AQ_CFG (0x600ull)
37 #define NPA_AF_AQ_BASE (0x610ull)
38 #define NPA_AF_AQ_STATUS (0x620ull)
39 #define NPA_AF_AQ_DOOR (0x630ull)
40 #define NPA_AF_AQ_DONE_WAIT (0x640ull)
41 #define NPA_AF_AQ_DONE (0x650ull)
42 #define NPA_AF_AQ_DONE_ACK (0x660ull)
43 #define NPA_AF_AQ_DONE_TIMER (0x670ull)
44 #define NPA_AF_AQ_DONE_INT (0x680ull)
45 #define NPA_AF_AQ_DONE_ENA_W1S (0x690ull)
46 #define NPA_AF_AQ_DONE_ENA_W1C (0x698ull)
47 #define NPA_AF_BATCH_CTL (0x6a0ull) /* [CN10K, .) */
48 #define NPA_AF_BATCH_ACCEPT_CTL (0x6a8ull) /* [CN10K, .) */
49 #define NPA_AF_BATCH_ERR_DATA0 (0x6c0ull) /* [CN10K, .) */
50 #define NPA_AF_BATCH_ERR_DATA1 (0x6c8ull) /* [CN10K, .) */
51 #define NPA_AF_LFX_AURAS_CFG(a) (0x4000ull | (uint64_t)(a) << 18)
52 #define NPA_AF_LFX_LOC_AURAS_BASE(a) (0x4010ull | (uint64_t)(a) << 18)
53 #define NPA_AF_LFX_QINTS_CFG(a) (0x4100ull | (uint64_t)(a) << 18)
54 #define NPA_AF_LFX_QINTS_BASE(a) (0x4110ull | (uint64_t)(a) << 18)
55 #define NPA_PRIV_AF_INT_CFG (0x10000ull)
56 #define NPA_PRIV_LFX_CFG(a) (0x10010ull | (uint64_t)(a) << 8)
57 #define NPA_PRIV_LFX_INT_CFG(a) (0x10020ull | (uint64_t)(a) << 8)
58 #define NPA_AF_RVU_LF_CFG_DEBUG (0x10030ull)
59 #define NPA_AF_DTX_FILTER_CTL (0x10040ull)
61 #define NPA_LF_AURA_OP_ALLOCX(a) (0x10ull | (uint64_t)(a) << 3)
62 #define NPA_LF_AURA_OP_FREE0 (0x20ull)
63 #define NPA_LF_AURA_OP_FREE1 (0x28ull)
64 #define NPA_LF_AURA_OP_CNT (0x30ull)
65 #define NPA_LF_AURA_OP_LIMIT (0x50ull)
66 #define NPA_LF_AURA_OP_INT (0x60ull)
67 #define NPA_LF_AURA_OP_THRESH (0x70ull)
68 #define NPA_LF_POOL_OP_PC (0x100ull)
69 #define NPA_LF_POOL_OP_AVAILABLE (0x110ull)
70 #define NPA_LF_POOL_OP_PTR_START0 (0x120ull)
71 #define NPA_LF_POOL_OP_PTR_START1 (0x128ull)
72 #define NPA_LF_POOL_OP_PTR_END0 (0x130ull)
73 #define NPA_LF_POOL_OP_PTR_END1 (0x138ull)
74 #define NPA_LF_POOL_OP_INT (0x160ull)
75 #define NPA_LF_POOL_OP_THRESH (0x170ull)
76 #define NPA_LF_ERR_INT (0x200ull)
77 #define NPA_LF_ERR_INT_W1S (0x208ull)
78 #define NPA_LF_ERR_INT_ENA_W1C (0x210ull)
79 #define NPA_LF_ERR_INT_ENA_W1S (0x218ull)
80 #define NPA_LF_RAS (0x220ull)
81 #define NPA_LF_RAS_W1S (0x228ull)
82 #define NPA_LF_RAS_ENA_W1C (0x230ull)
83 #define NPA_LF_RAS_ENA_W1S (0x238ull)
84 #define NPA_LF_QINTX_CNT(a) (0x300ull | (uint64_t)(a) << 12)
85 #define NPA_LF_QINTX_INT(a) (0x310ull | (uint64_t)(a) << 12)
86 #define NPA_LF_QINTX_ENA_W1S(a) (0x320ull | (uint64_t)(a) << 12)
87 #define NPA_LF_QINTX_ENA_W1C(a) (0x330ull | (uint64_t)(a) << 12)
88 #define NPA_LF_AURA_BATCH_ALLOC (0x340ull) /* [CN10K, .) */
89 #define NPA_LF_AURA_BATCH_FREE0 (0x400ull) /* [CN10K, .) */
90 #define NPA_LF_AURA_BATCH_FREEX(a) \
91 (0x400ull | (uint64_t)(a) << 3) /* [CN10K, .) */
95 #define NPA_AF_BATCH_FAIL_BATCH_PASS (0x0ull) /* [CN10K, .) */
96 #define NPA_AF_BATCH_FAIL_BATCH_CNT_OOR (0x1ull) /* [CN10K, .) */
97 #define NPA_AF_BATCH_FAIL_BATCH_STORE_FAIL (0x2ull) /* [CN10K, .) */
99 #define NPA_AQ_COMP_NOTDONE (0x0ull)
100 #define NPA_AQ_COMP_GOOD (0x1ull)
101 #define NPA_AQ_COMP_SWERR (0x2ull)
102 #define NPA_AQ_COMP_CTX_POISON (0x3ull)
103 #define NPA_AQ_COMP_CTX_FAULT (0x4ull)
104 #define NPA_AQ_COMP_LOCKERR (0x5ull)
106 #define NPA_AF_INT_VEC_RVU (0x0ull)
107 #define NPA_AF_INT_VEC_GEN (0x1ull)
108 #define NPA_AF_INT_VEC_AQ_DONE (0x2ull)
109 #define NPA_AF_INT_VEC_AF_ERR (0x3ull)
110 #define NPA_AF_INT_VEC_POISON (0x4ull)
112 #define NPA_AQ_INSTOP_NOP (0x0ull)
113 #define NPA_AQ_INSTOP_INIT (0x1ull)
114 #define NPA_AQ_INSTOP_WRITE (0x2ull)
115 #define NPA_AQ_INSTOP_READ (0x3ull)
116 #define NPA_AQ_INSTOP_LOCK (0x4ull)
117 #define NPA_AQ_INSTOP_UNLOCK (0x5ull)
119 #define NPA_AQ_CTYPE_AURA (0x0ull)
120 #define NPA_AQ_CTYPE_POOL (0x1ull)
122 #define NPA_BPINTF_NIX0_RX (0x0ull)
123 #define NPA_BPINTF_NIX1_RX (0x1ull)
125 #define NPA_AURA_ERR_INT_AURA_FREE_UNDER (0x0ull)
126 #define NPA_AURA_ERR_INT_AURA_ADD_OVER (0x1ull)
127 #define NPA_AURA_ERR_INT_AURA_ADD_UNDER (0x2ull)
128 #define NPA_AURA_ERR_INT_POOL_DIS (0x3ull)
129 #define NPA_AURA_ERR_INT_R4 (0x4ull)
130 #define NPA_AURA_ERR_INT_R5 (0x5ull)
131 #define NPA_AURA_ERR_INT_R6 (0x6ull)
132 #define NPA_AURA_ERR_INT_R7 (0x7ull)
134 #define NPA_LF_INT_VEC_ERR_INT (0x40ull)
135 #define NPA_LF_INT_VEC_POISON (0x41ull)
136 #define NPA_LF_INT_VEC_QINT_END (0x3full)
137 #define NPA_LF_INT_VEC_QINT_START (0x0ull)
139 #define NPA_INPQ_SSO (0x4ull)
140 #define NPA_INPQ_TIM (0x5ull)
141 #define NPA_INPQ_DPI (0x6ull)
142 #define NPA_INPQ_AURA_OP (0xeull)
143 #define NPA_INPQ_INTERNAL_RSV (0xfull)
144 #define NPA_INPQ_NIX0_RX (0x0ull)
145 #define NPA_INPQ_NIX1_RX (0x2ull)
146 #define NPA_INPQ_NIX0_TX (0x1ull)
147 #define NPA_INPQ_NIX1_TX (0x3ull)
148 #define NPA_INPQ_R_END (0xdull)
149 #define NPA_INPQ_R_START (0x7ull)
151 #define NPA_POOL_ERR_INT_OVFLS (0x0ull)
152 #define NPA_POOL_ERR_INT_RANGE (0x1ull)
153 #define NPA_POOL_ERR_INT_PERR (0x2ull)
154 #define NPA_POOL_ERR_INT_R3 (0x3ull)
155 #define NPA_POOL_ERR_INT_R4 (0x4ull)
156 #define NPA_POOL_ERR_INT_R5 (0x5ull)
157 #define NPA_POOL_ERR_INT_R6 (0x6ull)
158 #define NPA_POOL_ERR_INT_R7 (0x7ull)
160 #define NPA_NDC0_PORT_AURA0 (0x0ull)
161 #define NPA_NDC0_PORT_AURA1 (0x1ull)
162 #define NPA_NDC0_PORT_POOL0 (0x2ull)
163 #define NPA_NDC0_PORT_POOL1 (0x3ull)
164 #define NPA_NDC0_PORT_STACK0 (0x4ull)
165 #define NPA_NDC0_PORT_STACK1 (0x5ull)
167 #define NPA_LF_ERR_INT_AURA_DIS (0x0ull)
168 #define NPA_LF_ERR_INT_AURA_OOR (0x1ull)
169 #define NPA_LF_ERR_INT_AURA_FAULT (0xcull)
170 #define NPA_LF_ERR_INT_POOL_FAULT (0xdull)
171 #define NPA_LF_ERR_INT_STACK_FAULT (0xeull)
172 #define NPA_LF_ERR_INT_QINT_FAULT (0xfull)
174 #define NPA_BATCH_ALLOC_RESULT_ACCEPTED (0x0ull) /* [CN10K, .) */
175 #define NPA_BATCH_ALLOC_RESULT_WAIT (0x1ull) /* [CN10K, .) */
176 #define NPA_BATCH_ALLOC_RESULT_ERR (0x2ull) /* [CN10K, .) */
177 #define NPA_BATCH_ALLOC_RESULT_NOCORE (0x3ull) /* [CN10K, .) */
178 #define NPA_BATCH_ALLOC_RESULT_NOCORE_WAIT (0x4ull) /* [CN10K, .) */
180 #define NPA_BATCH_ALLOC_CCODE_INVAL (0x0ull) /* [CN10K, .) */
181 #define NPA_BATCH_ALLOC_CCODE_VAL (0x1ull) /* [CN10K, .) */
182 #define NPA_BATCH_ALLOC_CCODE_VAL_NULL (0x2ull) /* [CN10K, .) */
184 #define NPA_INPQ_ENAS_REMOTE_PORT (0x0ull) /* [CN10K, .) */
185 #define NPA_INPQ_ENAS_RESP_DISABLE (0x702ull) /* [CN10K, .) */
186 #define NPA_INPQ_ENAS_NOTIF_DISABLE (0x7cfull) /* [CN10K, .) */
188 /* Structures definitions */
190 /* NPA admin queue instruction structure */
191 struct npa_aq_inst_s {
195 uint64_t rsvd_23_17 : 7;
196 uint64_t cindex : 20;
197 uint64_t rsvd_62_44 : 19;
198 uint64_t doneint : 1;
199 uint64_t res_addr : 64; /* W1 */
202 /* NPA admin queue result structure */
203 struct npa_aq_res_s {
206 uint64_t compcode : 8;
207 uint64_t doneint : 1;
208 uint64_t rsvd_63_17 : 47;
209 uint64_t rsvd_127_64 : 64; /* W1 */
212 /* NPA aura operation write data structure */
213 struct npa_aura_op_wdata_s {
215 uint64_t rsvd_62_20 : 43;
219 /* NPA aura context structure */
221 uint64_t pool_addr : 64; /* W0 */
223 uint64_t rsvd_66_65 : 2;
224 uint64_t pool_caching : 1;
225 uint64_t pool_way_mask : 16;
226 uint64_t avg_con : 9;
227 uint64_t rsvd_93 : 1;
228 uint64_t pool_drop_ena : 1;
229 uint64_t aura_drop_ena : 1;
231 uint64_t rsvd_103_98 : 6;
232 uint64_t aura_drop : 8;
234 uint64_t rsvd_119_118 : 2;
235 uint64_t avg_level : 8;
237 uint64_t rsvd_167_164 : 4;
238 uint64_t nix0_bpid : 9;
239 uint64_t rsvd_179_177 : 3;
240 uint64_t nix1_bpid : 9;
241 uint64_t rsvd_191_189 : 3;
243 uint64_t rsvd_231_228 : 4;
245 uint64_t rsvd_242_240 : 3;
246 uint64_t fc_be : 1; /* [CN10K, .) */
248 uint64_t fc_up_crossing : 1;
249 uint64_t fc_stype : 2;
250 uint64_t fc_hyst_bits : 4;
251 uint64_t rsvd_255_252 : 4;
252 uint64_t fc_addr : 64; /* W4 */
253 uint64_t pool_drop : 8;
254 uint64_t update_time : 16;
255 uint64_t err_int : 8;
256 uint64_t err_int_ena : 8;
257 uint64_t thresh_int : 1;
258 uint64_t thresh_int_ena : 1;
259 uint64_t thresh_up : 1;
260 uint64_t rsvd_363 : 1;
261 uint64_t thresh_qint_idx : 7;
262 uint64_t rsvd_371 : 1;
263 uint64_t err_qint_idx : 7;
264 uint64_t rsvd_383_379 : 5;
265 uint64_t thresh : 36;
266 uint64_t rsvd_423_420 : 4;
267 uint64_t fc_msh_dst : 11; /* [CN10K, .) */
268 uint64_t rsvd_447_435 : 13;
269 uint64_t rsvd_511_448 : 64; /* W7 */
272 /* NPA pool context structure */
274 uint64_t stack_base : 64; /* W0 */
276 uint64_t nat_align : 1;
277 uint64_t rsvd_67_66 : 2;
278 uint64_t stack_caching : 1;
279 uint64_t rsvd_71_69 : 3;
280 uint64_t stack_way_mask : 16;
281 uint64_t buf_offset : 12;
282 uint64_t rsvd_103_100 : 4;
283 uint64_t buf_size : 11;
284 uint64_t rsvd_127_115 : 13;
285 uint64_t stack_max_pages : 32;
286 uint64_t stack_pages : 32;
288 uint64_t rsvd_255_240 : 16;
289 uint64_t stack_offset : 4;
290 uint64_t rsvd_263_260 : 4;
292 uint64_t rsvd_271_270 : 2;
293 uint64_t avg_level : 8;
294 uint64_t avg_con : 9;
296 uint64_t fc_stype : 2;
297 uint64_t fc_hyst_bits : 4;
298 uint64_t fc_up_crossing : 1;
299 uint64_t fc_be : 1; /* [CN10K, .) */
300 uint64_t rsvd_299_298 : 2;
301 uint64_t update_time : 16;
302 uint64_t rsvd_319_316 : 4;
303 uint64_t fc_addr : 64; /* W5 */
304 uint64_t ptr_start : 64; /* W6 */
305 uint64_t ptr_end : 64; /* W7 */
306 uint64_t rsvd_535_512 : 24;
307 uint64_t err_int : 8;
308 uint64_t err_int_ena : 8;
309 uint64_t thresh_int : 1;
310 uint64_t thresh_int_ena : 1;
311 uint64_t thresh_up : 1;
312 uint64_t rsvd_555 : 1;
313 uint64_t thresh_qint_idx : 7;
314 uint64_t rsvd_563 : 1;
315 uint64_t err_qint_idx : 7;
316 uint64_t rsvd_575_571 : 5;
317 uint64_t thresh : 36;
318 uint64_t rsvd_615_612 : 4;
319 uint64_t fc_msh_dst : 11; /* [CN10K, .) */
320 uint64_t rsvd_639_627 : 13;
321 uint64_t rsvd_703_640 : 64; /* W10 */
322 uint64_t rsvd_767_704 : 64; /* W11 */
323 uint64_t rsvd_831_768 : 64; /* W12 */
324 uint64_t rsvd_895_832 : 64; /* W13 */
325 uint64_t rsvd_959_896 : 64; /* W14 */
326 uint64_t rsvd_1023_960 : 64; /* W15 */
329 /* NPA queue interrupt context hardware structure */
330 struct npa_qint_hw_s {
332 uint32_t rsvd_30_22 : 9;
336 /* NPA batch allocate compare hardware structure */
337 struct npa_batch_alloc_compare_s {
339 uint64_t rsvd_31_20 : 12;
341 uint64_t rsvd_47_42 : 6;
343 uint64_t rsvd_61_50 : 12;
344 uint64_t dis_wait : 1;
348 /* NPA batch alloc dma write status structure */
349 struct npa_batch_alloc_status_s {
352 uint8_t rsvd_7_7 : 1;
356 ALLOC_RESULT_ACCEPTED = 0,
357 ALLOC_RESULT_WAIT = 1,
358 ALLOC_RESULT_ERR = 2,
359 ALLOC_RESULT_NOCORE = 3,
360 ALLOC_RESULT_NOCORE_WAIT = 4,
361 } npa_batch_alloc_result_e;
364 ALLOC_CCODE_INVAL = 0,
366 ALLOC_CCODE_VAL_NULL = 2,
367 } npa_batch_alloc_ccode_e;
373 ALLOC_STYPE_STSTP = 3,
374 } npa_batch_alloc_stype_e;
376 #endif /* __NPA_HW_H__ */