1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
9 #define TIM_AF_CONST (0x90)
10 #define TIM_PRIV_LFX_CFG(a) (0x20000 | (a) << 3)
11 #define TIM_PRIV_LFX_INT_CFG(a) (0x24000 | (a) << 3)
12 #define TIM_AF_RVU_LF_CFG_DEBUG (0x30000)
13 #define TIM_AF_BLK_RST (0x10)
14 #define TIM_AF_LF_RST (0x20)
15 #define TIM_AF_BLK_RST (0x10)
16 #define TIM_AF_RINGX_GMCTL(a) (0x2000 | (a) << 3)
17 #define TIM_AF_RINGX_CTL0(a) (0x4000 | (a) << 3)
18 #define TIM_AF_RINGX_CTL1(a) (0x6000 | (a) << 3)
19 #define TIM_AF_RINGX_CTL2(a) (0x8000 | (a) << 3)
20 #define TIM_AF_FLAGS_REG (0x80)
21 #define TIM_AF_FLAGS_REG_ENA_TIM BIT_ULL(0)
22 #define TIM_AF_RINGX_CTL1_ENA BIT_ULL(47)
23 #define TIM_AF_RINGX_CTL1_RCF_BUSY BIT_ULL(50)
24 #define TIM_AF_RINGX_CLT1_CLK_10NS (0)
25 #define TIM_AF_RINGX_CLT1_CLK_GPIO (1)
26 #define TIM_AF_RINGX_CLT1_CLK_GTI (2)
27 #define TIM_AF_RINGX_CLT1_CLK_PTP (3)
31 #define TIM_LF_INT_VEC_NRSPERR_INT (0x0ull)
32 #define TIM_LF_INT_VEC_RAS_INT (0x1ull)
33 #define TIM_LF_RING_AURA (0x0)
34 #define TIM_LF_RING_BASE (0x130)
35 #define TIM_LF_NRSPERR_INT (0x200)
36 #define TIM_LF_NRSPERR_INT_W1S (0x208)
37 #define TIM_LF_NRSPERR_INT_ENA_W1S (0x210)
38 #define TIM_LF_NRSPERR_INT_ENA_W1C (0x218)
39 #define TIM_LF_RAS_INT (0x300)
40 #define TIM_LF_RAS_INT_W1S (0x308)
41 #define TIM_LF_RAS_INT_ENA_W1S (0x310)
42 #define TIM_LF_RAS_INT_ENA_W1C (0x318)
43 #define TIM_LF_RING_REL (0x400)
45 #define TIM_MAX_INTERVAL_TICKS ((1ULL << 32) - 1)
46 #define TIM_MAX_BUCKET_SIZE ((1ULL << 20) - 1)
47 #define TIM_MIN_BUCKET_SIZE 3
49 #endif /* __TIM_HW_H__ */