1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
15 /* Bits manipulation */
18 /* Bitfields manipulation */
19 #include "roc_bitfield.h"
22 #define PLT_ETHER_ADDR_LEN 6
24 /* Platform definition */
25 #include "roc_platform.h"
27 #define ROC_LMT_LINES_PER_CORE_LOG2 5
28 #define ROC_LMT_LINE_SIZE_LOG2 7
29 #define ROC_LMT_BASE_PER_CORE_LOG2 \
30 (ROC_LMT_LINES_PER_CORE_LOG2 + ROC_LMT_LINE_SIZE_LOG2)
33 #if defined(__aarch64__)
36 #include "roc_io_generic.h"
40 #define PCI_VENDOR_ID_CAVIUM 0x177D
41 #define PCI_DEVID_CNXK_RVU_PF 0xA063
42 #define PCI_DEVID_CNXK_RVU_VF 0xA064
43 #define PCI_DEVID_CNXK_RVU_AF 0xA065
44 #define PCI_DEVID_CNXK_RVU_SSO_TIM_PF 0xA0F9
45 #define PCI_DEVID_CNXK_RVU_SSO_TIM_VF 0xA0FA
46 #define PCI_DEVID_CNXK_RVU_NPA_PF 0xA0FB
47 #define PCI_DEVID_CNXK_RVU_NPA_VF 0xA0FC
48 #define PCI_DEVID_CNXK_RVU_AF_VF 0xA0f8
49 #define PCI_DEVID_CNXK_DPI_VF 0xA081
50 #define PCI_DEVID_CNXK_EP_VF 0xB203
51 #define PCI_DEVID_CNXK_RVU_SDP_PF 0xA0f6
52 #define PCI_DEVID_CNXK_RVU_SDP_VF 0xA0f7
54 #define PCI_DEVID_CN9K_CGX 0xA059
55 #define PCI_DEVID_CN10K_RPM 0xA060
57 #define PCI_SUBSYSTEM_DEVID_CN10KA 0xB900
58 #define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900
60 #define PCI_SUBSYSTEM_DEVID_CN9KA 0x0000
61 #define PCI_SUBSYSTEM_DEVID_CN9KB 0xb400
62 #define PCI_SUBSYSTEM_DEVID_CN9KC 0x0200
63 #define PCI_SUBSYSTEM_DEVID_CN9KD 0xB200
64 #define PCI_SUBSYSTEM_DEVID_CN9KE 0xB100
66 /* HW structure definition */
77 #include "roc_model.h"
98 #include "roc_utils.h"
101 #include "roc_idev.h"
103 #endif /* _ROC_API_H_ */