1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
10 #define CGX_CMRX_INT 0x40
11 #define CGX_CMRX_INT_OVERFLW BIT_ULL(1)
13 * CN10K stores number of lmacs in 4 bit filed
14 * in contraty to CN9K which uses only 3 bits.
16 * In theory masks should differ yet on CN9K
17 * bits beyond specified range contain zeros.
19 * Hence common longer mask may be used.
21 #define CGX_CMRX_RX_LMACS 0x128
22 #define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
23 #define CGX_CMRX_SCRATCH0 0x1050
24 #define CGX_CMRX_SCRATCH1 0x1058
27 roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
29 int shift = roc_model_is_cn10k() ? 20 : 18;
30 uint64_t base = (uint64_t)roc_cgx->bar0_va;
32 return plt_read64(base + (lmac << shift) + offset);
36 roc_bphy_cgx_write(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset,
39 int shift = roc_model_is_cn10k() ? 20 : 18;
40 uint64_t base = (uint64_t)roc_cgx->bar0_va;
42 plt_write64(value, base + (lmac << shift) + offset);
46 roc_bphy_cgx_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
52 val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_INT);
53 val |= FIELD_PREP(CGX_CMRX_INT_OVERFLW, 1);
54 roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_INT, val);
57 *scr0 &= ~SCR0_ETH_EVT_STS_S_ACK;
58 roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH0, *scr0);
62 roc_bphy_cgx_wait_for_ownership(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
69 *scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
70 scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
72 if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
73 FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0) == 0)
76 /* clear async events if any */
77 if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) ==
79 FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))
80 roc_bphy_cgx_ack(roc_cgx, lmac, scr0);
85 return tries ? 0 : -ETIMEDOUT;
89 roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
96 *scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
97 scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
99 if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
100 FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))
106 return tries ? 0 : -ETIMEDOUT;
110 roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
111 uint64_t scr1, uint64_t *scr0)
113 uint8_t cmd_id = FIELD_GET(SCR1_ETH_CMD_ID, scr1);
116 pthread_mutex_lock(&roc_cgx->lock);
118 /* wait for ownership */
119 ret = roc_bphy_cgx_wait_for_ownership(roc_cgx, lmac, scr0);
121 plt_err("timed out waiting for ownership");
126 scr1 |= FIELD_PREP(SCR1_OWN_STATUS, ETH_OWN_FIRMWARE);
127 roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH1, scr1);
129 /* wait for command ack */
130 ret = roc_bphy_cgx_wait_for_ack(roc_cgx, lmac, scr0);
132 plt_err("timed out waiting for response");
136 if (cmd_id == ETH_CMD_INTF_SHUTDOWN)
139 if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) != ETH_EVT_CMD_RESP) {
140 plt_err("received async event instead of cmd resp event");
145 if (FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0) != cmd_id) {
146 plt_err("received resp for cmd %d expected for cmd %d",
147 (int)FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0), cmd_id);
152 if (FIELD_GET(SCR0_ETH_EVT_STS_S_STAT, *scr0) != ETH_STAT_SUCCESS) {
153 plt_err("cmd %d failed on cgx%u lmac%u with errcode %d", cmd_id,
155 (int)FIELD_GET(SCR0_ETH_LNK_STS_S_ERR_TYPE, *scr0));
160 roc_bphy_cgx_ack(roc_cgx, lmac, scr0);
162 pthread_mutex_unlock(&roc_cgx->lock);
168 roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)
170 uint64_t cgx_id = roc_model_is_cn10k() ? GENMASK_ULL(26, 24) :
173 return FIELD_GET(cgx_id, roc_cgx->bar0_pa);
177 roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)
182 if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)
185 ret = pthread_mutex_init(&roc_cgx->lock, NULL);
189 val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);
190 val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);
191 if (roc_model_is_cn9k())
192 val = GENMASK_ULL(val - 1, 0);
193 roc_cgx->lmac_bmap = val;
194 roc_cgx->id = roc_bphy_cgx_dev_id(roc_cgx);
200 roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
205 pthread_mutex_destroy(&roc_cgx->lock);
211 roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
213 return (lmac < MAX_LMACS_PER_CGX) &&
214 (roc_cgx->lmac_bmap & BIT_ULL(lmac));
218 roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
226 if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
229 scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_INTERNAL_LBK) |
230 FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
232 return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
236 roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
241 if (roc_model_is_cn10k())
247 if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
250 scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_SET_PTP_MODE) |
251 FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
253 return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
257 roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
258 struct roc_bphy_cgx_link_info *info)
266 if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
272 scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_LINK_STS);
273 ret = roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
277 info->link_up = FIELD_GET(SCR0_ETH_LNK_STS_S_LINK_UP, scr0);
278 info->full_duplex = FIELD_GET(SCR0_ETH_LNK_STS_S_FULL_DUPLEX, scr0);
279 info->speed = FIELD_GET(SCR0_ETH_LNK_STS_S_SPEED, scr0);
280 info->an = FIELD_GET(SCR0_ETH_LNK_STS_S_AN, scr0);
281 info->fec = FIELD_GET(SCR0_ETH_LNK_STS_S_FEC, scr0);
282 info->mode = FIELD_GET(SCR0_ETH_LNK_STS_S_MODE, scr0);
288 roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
289 struct roc_bphy_cgx_link_mode *mode)
293 if (roc_model_is_cn10k())
299 if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
305 scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_MODE_CHANGE) |
306 FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) |
307 FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) |
308 FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) |
309 FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) |
310 FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode));
312 return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
316 roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
318 return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, true);
322 roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
324 return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, false);
328 roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
330 return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, true);
334 roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
336 return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, false);