1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
10 #define CGX_CMRX_CONFIG 0x00
11 #define CGX_CMRX_CONFIG_DATA_PKT_RX_EN BIT_ULL(54)
12 #define CGX_CMRX_CONFIG_DATA_PKT_TX_EN BIT_ULL(53)
13 #define CGX_CMRX_INT 0x40
14 #define CGX_CMRX_INT_OVERFLW BIT_ULL(1)
16 * CN10K stores number of lmacs in 4 bit filed
17 * in contraty to CN9K which uses only 3 bits.
19 * In theory masks should differ yet on CN9K
20 * bits beyond specified range contain zeros.
22 * Hence common longer mask may be used.
24 #define CGX_CMRX_RX_LMACS 0x128
25 #define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
26 #define CGX_CMRX_SCRATCH0 0x1050
27 #define CGX_CMRX_SCRATCH1 0x1058
30 roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
32 int shift = roc_model_is_cn10k() ? 20 : 18;
33 uint64_t base = (uint64_t)roc_cgx->bar0_va;
35 return plt_read64(base + (lmac << shift) + offset);
39 roc_bphy_cgx_write(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset,
42 int shift = roc_model_is_cn10k() ? 20 : 18;
43 uint64_t base = (uint64_t)roc_cgx->bar0_va;
45 plt_write64(value, base + (lmac << shift) + offset);
49 roc_bphy_cgx_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
55 val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_INT);
56 val |= FIELD_PREP(CGX_CMRX_INT_OVERFLW, 1);
57 roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_INT, val);
60 *scr0 &= ~SCR0_ETH_EVT_STS_S_ACK;
61 roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH0, *scr0);
65 roc_bphy_cgx_wait_for_ownership(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
72 *scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
73 scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
75 if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
76 FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0) == 0)
79 /* clear async events if any */
80 if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) ==
82 FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))
83 roc_bphy_cgx_ack(roc_cgx, lmac, scr0);
88 return tries ? 0 : -ETIMEDOUT;
92 roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
99 *scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
100 scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
102 if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
103 FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))
109 return tries ? 0 : -ETIMEDOUT;
113 roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
114 uint64_t scr1, uint64_t *scr0)
116 uint8_t cmd_id = FIELD_GET(SCR1_ETH_CMD_ID, scr1);
119 pthread_mutex_lock(&roc_cgx->lock);
121 /* wait for ownership */
122 ret = roc_bphy_cgx_wait_for_ownership(roc_cgx, lmac, scr0);
124 plt_err("timed out waiting for ownership");
129 scr1 |= FIELD_PREP(SCR1_OWN_STATUS, ETH_OWN_FIRMWARE);
130 roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH1, scr1);
132 /* wait for command ack */
133 ret = roc_bphy_cgx_wait_for_ack(roc_cgx, lmac, scr0);
135 plt_err("timed out waiting for response");
139 if (cmd_id == ETH_CMD_INTF_SHUTDOWN)
142 if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) != ETH_EVT_CMD_RESP) {
143 plt_err("received async event instead of cmd resp event");
148 if (FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0) != cmd_id) {
149 plt_err("received resp for cmd %d expected for cmd %d",
150 (int)FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0), cmd_id);
155 if (FIELD_GET(SCR0_ETH_EVT_STS_S_STAT, *scr0) != ETH_STAT_SUCCESS) {
156 plt_err("cmd %d failed on cgx%u lmac%u with errcode %d", cmd_id,
158 (int)FIELD_GET(SCR0_ETH_LNK_STS_S_ERR_TYPE, *scr0));
163 roc_bphy_cgx_ack(roc_cgx, lmac, scr0);
165 pthread_mutex_unlock(&roc_cgx->lock);
171 roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)
173 uint64_t cgx_id = roc_model_is_cn10k() ? GENMASK_ULL(26, 24) :
176 return FIELD_GET(cgx_id, roc_cgx->bar0_pa);
180 roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)
185 if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)
188 ret = pthread_mutex_init(&roc_cgx->lock, NULL);
192 val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);
193 val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);
194 if (roc_model_is_cn9k())
195 val = GENMASK_ULL(val - 1, 0);
196 roc_cgx->lmac_bmap = val;
197 roc_cgx->id = roc_bphy_cgx_dev_id(roc_cgx);
203 roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
208 pthread_mutex_destroy(&roc_cgx->lock);
214 roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
216 return (lmac < MAX_LMACS_PER_CGX) &&
217 (roc_cgx->lmac_bmap & BIT_ULL(lmac));
221 roc_bphy_cgx_start_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
229 if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
232 pthread_mutex_lock(&roc_cgx->lock);
233 val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_CONFIG);
234 val &= ~(CGX_CMRX_CONFIG_DATA_PKT_RX_EN |
235 CGX_CMRX_CONFIG_DATA_PKT_TX_EN);
238 val |= FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_RX_EN, 1) |
239 FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_TX_EN, 1);
241 roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_CONFIG, val);
242 pthread_mutex_unlock(&roc_cgx->lock);
248 roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
256 if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
259 scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_INTERNAL_LBK) |
260 FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
262 return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
266 roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
271 if (roc_model_is_cn10k())
277 if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
280 scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_SET_PTP_MODE) |
281 FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
283 return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
287 roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
289 return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, true);
293 roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
295 return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, false);
299 roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
307 if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
310 scr1 = state ? FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_UP) :
311 FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_DOWN);
313 return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
317 roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
318 struct roc_bphy_cgx_link_info *info)
326 if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
332 scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_LINK_STS);
333 ret = roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
337 info->link_up = FIELD_GET(SCR0_ETH_LNK_STS_S_LINK_UP, scr0);
338 info->full_duplex = FIELD_GET(SCR0_ETH_LNK_STS_S_FULL_DUPLEX, scr0);
339 info->speed = FIELD_GET(SCR0_ETH_LNK_STS_S_SPEED, scr0);
340 info->an = FIELD_GET(SCR0_ETH_LNK_STS_S_AN, scr0);
341 info->fec = FIELD_GET(SCR0_ETH_LNK_STS_S_FEC, scr0);
342 info->mode = FIELD_GET(SCR0_ETH_LNK_STS_S_MODE, scr0);
348 roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
349 struct roc_bphy_cgx_link_mode *mode)
353 if (roc_model_is_cn10k())
359 if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
365 scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_MODE_CHANGE) |
366 FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) |
367 FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) |
368 FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) |
369 FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) |
370 FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode));
372 return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
376 roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
378 return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, true);
382 roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
384 return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, false);
388 roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
390 return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, true);
394 roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
396 return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, false);
400 roc_bphy_cgx_fec_set(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
401 enum roc_bphy_cgx_eth_link_fec fec)
408 if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
411 scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_SET_FEC) |
412 FIELD_PREP(SCR1_ETH_SET_FEC_ARGS, fec);
414 return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
418 roc_bphy_cgx_fec_supported_get(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
419 enum roc_bphy_cgx_eth_link_fec *fec)
424 if (!roc_cgx || !fec)
427 if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
430 scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_SUPPORTED_FEC);
432 ret = roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
436 scr0 = FIELD_GET(SCR0_ETH_FEC_TYPES_S_FEC, scr0);
437 *fec = (enum roc_bphy_cgx_eth_link_fec)scr0;