1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef _ROC_BPHY_CGX_H_
6 #define _ROC_BPHY_CGX_H_
12 #define MAX_LMACS_PER_CGX 4
19 /* serialize access to the whole structure */
21 } __plt_cache_aligned;
23 enum roc_bphy_cgx_eth_link_speed {
24 ROC_BPHY_CGX_ETH_LINK_SPEED_NONE,
25 ROC_BPHY_CGX_ETH_LINK_SPEED_10M,
26 ROC_BPHY_CGX_ETH_LINK_SPEED_100M,
27 ROC_BPHY_CGX_ETH_LINK_SPEED_1G,
28 ROC_BPHY_CGX_ETH_LINK_SPEED_2HG,
29 ROC_BPHY_CGX_ETH_LINK_SPEED_5G,
30 ROC_BPHY_CGX_ETH_LINK_SPEED_10G,
31 ROC_BPHY_CGX_ETH_LINK_SPEED_20G,
32 ROC_BPHY_CGX_ETH_LINK_SPEED_25G,
33 ROC_BPHY_CGX_ETH_LINK_SPEED_40G,
34 ROC_BPHY_CGX_ETH_LINK_SPEED_50G,
35 ROC_BPHY_CGX_ETH_LINK_SPEED_80G,
36 ROC_BPHY_CGX_ETH_LINK_SPEED_100G,
37 __ROC_BPHY_CGX_ETH_LINK_SPEED_MAX
40 enum roc_bphy_cgx_eth_link_fec {
41 ROC_BPHY_CGX_ETH_LINK_FEC_NONE,
42 ROC_BPHY_CGX_ETH_LINK_FEC_BASE_R,
43 ROC_BPHY_CGX_ETH_LINK_FEC_RS,
44 __ROC_BPHY_CGX_ETH_LINK_FEC_MAX
47 enum roc_bphy_cgx_eth_link_mode {
48 ROC_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
49 ROC_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
50 ROC_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
51 ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
52 ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
53 ROC_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
54 ROC_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
55 ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
56 ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
57 ROC_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
58 ROC_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
59 ROC_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
60 ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
61 ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
62 ROC_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
63 ROC_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
64 ROC_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
65 ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
66 ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
67 ROC_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
68 ROC_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
69 ROC_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
70 ROC_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
71 ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
72 ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
73 ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
74 ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
75 __ROC_BPHY_CGX_ETH_LINK_MODE_MAX
78 struct roc_bphy_cgx_link_mode {
82 enum roc_bphy_cgx_eth_link_speed speed;
83 enum roc_bphy_cgx_eth_link_mode mode;
86 struct roc_bphy_cgx_link_info {
89 enum roc_bphy_cgx_eth_link_speed speed;
91 enum roc_bphy_cgx_eth_link_fec fec;
92 enum roc_bphy_cgx_eth_link_mode mode;
95 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
96 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
98 __roc_api int roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx,
100 __roc_api int roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx,
102 __roc_api int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx,
103 unsigned int lmac, bool state);
104 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
106 struct roc_bphy_cgx_link_info *info);
107 __roc_api int roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx,
109 struct roc_bphy_cgx_link_mode *mode);
110 __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
112 __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
114 __roc_api int roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx,
116 __roc_api int roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx,
118 __roc_api int roc_bphy_cgx_fec_set(struct roc_bphy_cgx *roc_cgx,
120 enum roc_bphy_cgx_eth_link_fec fec);
121 __roc_api int roc_bphy_cgx_fec_supported_get(struct roc_bphy_cgx *roc_cgx,
123 enum roc_bphy_cgx_eth_link_fec *fec);
126 #endif /* _ROC_BPHY_CGX_H_ */