1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef _ROC_BPHY_CGX_PRIV_H_
6 #define _ROC_BPHY_CGX_PRIV_H_
14 ETH_LINK_2HG, /* 2.5 Gbps */
26 /* Supported LINK MODE enums
27 * Each link mode is a bit mask of these
28 * enums which are represented as bits
31 ETH_MODE_SGMII_BIT = 0,
32 ETH_MODE_1000_BASEX_BIT,
36 ETH_MODE_10G_KR_BIT, /* = 5 */
40 ETH_MODE_25G_2_C2C_BIT,
41 ETH_MODE_25G_CR_BIT, /* = 10 */
46 ETH_MODE_40G_KR4_BIT, /* = 15 */
47 ETH_MODE_40GAUI_C2C_BIT,
50 ETH_MODE_50G_4_C2C_BIT,
51 ETH_MODE_50G_CR_BIT, /* = 20 */
53 ETH_MODE_80GAUI_C2C_BIT,
54 ETH_MODE_100G_C2C_BIT,
55 ETH_MODE_100G_C2M_BIT,
56 ETH_MODE_100G_CR4_BIT, /* = 25 */
57 ETH_MODE_100G_KR4_BIT,
58 ETH_MODE_MAX_BIT /* = 27 */
61 /* REQUEST ID types. Input to firmware */
63 ETH_CMD_GET_LINK_STS = 4,
64 ETH_CMD_LINK_BRING_UP = 5,
65 ETH_CMD_LINK_BRING_DOWN = 6,
66 ETH_CMD_INTERNAL_LBK = 7,
67 ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
68 ETH_CMD_INTF_SHUTDOWN = 12,
69 ETH_CMD_GET_SUPPORTED_FEC = 18,
71 ETH_CMD_SET_PTP_MODE = 34,
74 /* event types - cause of interrupt */
86 /* default ownership with kernel/uefi/u-boot */
87 ETH_OWN_NON_SECURE_SW,
88 /* set by kernel/uefi/u-boot after posting a new request to ATF */
92 /* scratchx(0) CSR used for ATF->non-secure SW communication.
93 * This acts as the status register
94 * Provides details on command ack/status, link status, error details
97 /* struct eth_evt_sts_s */
98 #define SCR0_ETH_EVT_STS_S_ACK BIT_ULL(0)
99 #define SCR0_ETH_EVT_STS_S_EVT_TYPE BIT_ULL(1)
100 #define SCR0_ETH_EVT_STS_S_STAT BIT_ULL(2)
101 #define SCR0_ETH_EVT_STS_S_ID GENMASK_ULL(8, 3)
103 /* struct eth_lnk_sts_s */
104 #define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15)
105 #define SCR0_ETH_LNK_STS_S_LINK_UP BIT_ULL(9)
106 #define SCR0_ETH_LNK_STS_S_FULL_DUPLEX BIT_ULL(10)
107 #define SCR0_ETH_LNK_STS_S_SPEED GENMASK_ULL(14, 11)
108 #define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15)
109 #define SCR0_ETH_LNK_STS_S_AN BIT_ULL(25)
110 #define SCR0_ETH_LNK_STS_S_FEC GENMASK_ULL(27, 26)
111 #define SCR0_ETH_LNK_STS_S_LMAC_TYPE GENMASK_ULL(35, 28)
112 #define SCR0_ETH_LNK_STS_S_MODE GENMASK_ULL(43, 36)
114 /* struct eth_fec_types_s */
115 #define SCR0_ETH_FEC_TYPES_S_FEC GENMASK_ULL(10, 9)
117 /* scratchx(1) CSR used for non-secure SW->ATF communication
118 * This CSR acts as a command register
122 #define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2)
124 /* struct eth_ctl_args */
125 #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)
127 /* struct eth_mode_change_args */
128 #define SCR1_ETH_MODE_CHANGE_ARGS_SPEED GENMASK_ULL(11, 8)
129 #define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12)
130 #define SCR1_ETH_MODE_CHANGE_ARGS_AN BIT_ULL(13)
131 #define SCR1_ETH_MODE_CHANGE_ARGS_PORT GENMASK_ULL(21, 14)
132 #define SCR1_ETH_MODE_CHANGE_ARGS_MODE GENMASK_ULL(63, 22)
134 /* struct eth_set_fec_args */
135 #define SCR1_ETH_SET_FEC_ARGS GENMASK_ULL(9, 8)
137 #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
139 #endif /* _ROC_BPHY_CGX_PRIV_H_ */