1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef _ROC_BPHY_CGX_PRIV_H_
6 #define _ROC_BPHY_CGX_PRIV_H_
8 /* REQUEST ID types. Input to firmware */
10 ETH_CMD_GET_LINK_STS = 4,
11 ETH_CMD_LINK_BRING_UP = 5,
12 ETH_CMD_LINK_BRING_DOWN = 6,
13 ETH_CMD_INTERNAL_LBK = 7,
14 ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
15 ETH_CMD_INTF_SHUTDOWN = 12,
16 ETH_CMD_GET_SUPPORTED_FEC = 18,
18 ETH_CMD_SET_PTP_MODE = 34,
19 ETH_CMD_CPRI_MODE_CHANGE = 35,
20 ETH_CMD_CPRI_TX_CONTROL = 36,
21 ETH_CMD_CPRI_MISC = 42,
24 /* event types - cause of interrupt */
36 /* default ownership with kernel/uefi/u-boot */
37 ETH_OWN_NON_SECURE_SW,
38 /* set by kernel/uefi/u-boot after posting a new request to ATF */
42 /* scratchx(0) CSR used for ATF->non-secure SW communication.
43 * This acts as the status register
44 * Provides details on command ack/status, link status, error details
47 /* struct eth_evt_sts_s */
48 #define SCR0_ETH_EVT_STS_S_ACK BIT_ULL(0)
49 #define SCR0_ETH_EVT_STS_S_EVT_TYPE BIT_ULL(1)
50 #define SCR0_ETH_EVT_STS_S_STAT BIT_ULL(2)
51 #define SCR0_ETH_EVT_STS_S_ID GENMASK_ULL(8, 3)
53 /* struct eth_lnk_sts_s */
54 #define SCR0_ETH_LNK_STS_S_LINK_UP BIT_ULL(9)
55 #define SCR0_ETH_LNK_STS_S_FULL_DUPLEX BIT_ULL(10)
56 #define SCR0_ETH_LNK_STS_S_SPEED GENMASK_ULL(14, 11)
57 #define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15)
58 #define SCR0_ETH_LNK_STS_S_AN BIT_ULL(25)
59 #define SCR0_ETH_LNK_STS_S_FEC GENMASK_ULL(27, 26)
60 #define SCR0_ETH_LNK_STS_S_LMAC_TYPE GENMASK_ULL(35, 28)
61 #define SCR0_ETH_LNK_STS_S_MODE GENMASK_ULL(43, 36)
63 /* struct eth_fec_types_s */
64 #define SCR0_ETH_FEC_TYPES_S_FEC GENMASK_ULL(10, 9)
66 /* scratchx(1) CSR used for non-secure SW->ATF communication
67 * This CSR acts as a command register
71 #define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2)
73 /* struct eth_ctl_args */
74 #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)
76 /* struct eth_mode_change_args */
77 #define SCR1_ETH_MODE_CHANGE_ARGS_SPEED GENMASK_ULL(11, 8)
78 #define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12)
79 #define SCR1_ETH_MODE_CHANGE_ARGS_AN BIT_ULL(13)
80 #define SCR1_ETH_MODE_CHANGE_ARGS_USE_PORTM_IDX BIT_ULL(14)
81 #define SCR1_ETH_MODE_CHANGE_ARGS_PORTM_IDX GENMASK_ULL(19, 15)
82 #define SCR1_ETH_MODE_CHANGE_ARGS_MODE_GROUP_IDX GENMASK_ULL(21, 20)
83 #define SCR1_ETH_MODE_CHANGE_ARGS_MODE GENMASK_ULL(63, 22)
85 /* struct eth_set_fec_args */
86 #define SCR1_ETH_SET_FEC_ARGS GENMASK_ULL(9, 8)
88 /* struct eth_cpri_mode_change_args */
89 #define SCR1_CPRI_MODE_CHANGE_ARGS_GSERC_IDX GENMASK_ULL(11, 8)
90 #define SCR1_CPRI_MODE_CHANGE_ARGS_LANE_IDX GENMASK_ULL(15, 12)
91 #define SCR1_CPRI_MODE_CHANGE_ARGS_RATE GENMASK_ULL(31, 16)
92 #define SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_LEQ BIT_ULL(32)
93 #define SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_DFE BIT_ULL(33)
95 /* struct cpri_mode_tx_ctrl_args */
96 #define SCR1_CPRI_MODE_TX_CTRL_ARGS_GSERC_IDX GENMASK_ULL(11, 8)
97 #define SCR1_CPRI_MODE_TX_CTRL_ARGS_LANE_IDX GENMASK_ULL(15, 12)
98 #define SCR1_CPRI_MODE_TX_CTRL_ARGS_ENABLE BIT_ULL(16)
100 /* struct cpri_mode_misc_args */
101 #define SCR1_CPRI_MODE_MISC_ARGS_GSERC_IDX GENMASK_ULL(11, 8)
102 #define SCR1_CPRI_MODE_MISC_ARGS_LANE_IDX GENMASK_ULL(15, 12)
103 #define SCR1_CPRI_MODE_MISC_ARGS_FLAGS GENMASK_ULL(17, 16)
105 #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
107 #endif /* _ROC_BPHY_CGX_PRIV_H_ */