1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
12 #include "roc_bphy_irq.h"
14 struct roc_bphy_irq_usr_data {
21 struct roc_bphy_irq_stack {
22 STAILQ_ENTRY(roc_bphy_irq_stack) entries;
28 #define ROC_BPHY_MEMZONE_NAME "roc_bphy_mz"
29 #define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
31 #define ROC_BPHY_IOC_MAGIC 0xF3
32 #define ROC_BPHY_IOC_SET_BPHY_HANDLER \
33 _IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data)
34 #define ROC_BPHY_IOC_CLR_BPHY_HANDLER _IO(ROC_BPHY_IOC_MAGIC, 2)
35 #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
36 #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
38 static STAILQ_HEAD(slisthead, roc_bphy_irq_stack)
39 irq_stacks = STAILQ_HEAD_INITIALIZER(irq_stacks);
41 /* Note: it is assumed that as for now there is no multiprocess support */
42 static pthread_mutex_t stacks_mutex = PTHREAD_MUTEX_INITIALIZER;
44 struct roc_bphy_irq_chip *
45 roc_bphy_intr_init(void)
47 struct roc_bphy_irq_chip *irq_chip;
48 uint64_t max_irq, i, avail_irqs;
51 fd = open(ROC_BPHY_CTR_DEV_PATH, O_RDWR | O_SYNC);
53 plt_err("Failed to open %s", ROC_BPHY_CTR_DEV_PATH);
57 ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_MAX_IRQ, &max_irq);
59 plt_err("Failed to get max irq number via ioctl");
63 ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ, &avail_irqs);
65 plt_err("Failed to get available irqs bitmask via ioctl");
69 irq_chip = plt_zmalloc(sizeof(*irq_chip), 0);
70 if (irq_chip == NULL) {
71 plt_err("Failed to alloc irq_chip");
76 irq_chip->max_irq = max_irq;
77 irq_chip->avail_irq_bmask = avail_irqs;
79 plt_zmalloc(irq_chip->max_irq * sizeof(*irq_chip->irq_vecs), 0);
80 if (irq_chip->irq_vecs == NULL) {
81 plt_err("Failed to alloc irq_chip irq_vecs");
85 irq_chip->mz_name = plt_zmalloc(strlen(ROC_BPHY_MEMZONE_NAME) + 1, 0);
86 if (irq_chip->mz_name == NULL) {
87 plt_err("Failed to alloc irq_chip name");
90 plt_strlcpy(irq_chip->mz_name, ROC_BPHY_MEMZONE_NAME,
91 strlen(ROC_BPHY_MEMZONE_NAME) + 1);
93 for (i = 0; i < irq_chip->max_irq; i++) {
94 irq_chip->irq_vecs[i].fd = -1;
95 irq_chip->irq_vecs[i].handler_cpu = -1;
101 plt_free(irq_chip->irq_vecs);
113 roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
115 if (irq_chip == NULL)
118 close(irq_chip->intfd);
119 plt_free(irq_chip->mz_name);
120 plt_free(irq_chip->irq_vecs);
125 roc_bphy_irq_stack_remove(int cpu)
127 struct roc_bphy_irq_stack *curr_stack;
129 if (pthread_mutex_lock(&stacks_mutex))
132 STAILQ_FOREACH(curr_stack, &irq_stacks, entries) {
133 if (curr_stack->cpu == cpu)
137 if (curr_stack == NULL)
140 if (curr_stack->inuse > 0)
143 if (curr_stack->inuse == 0) {
144 STAILQ_REMOVE(&irq_stacks, curr_stack, roc_bphy_irq_stack,
146 plt_free(curr_stack->sp_buffer);
147 plt_free(curr_stack);
151 pthread_mutex_unlock(&stacks_mutex);
155 roc_bphy_irq_stack_get(int cpu)
157 #define ARM_STACK_ALIGNMENT (2 * sizeof(void *))
158 #define IRQ_ISR_STACK_SIZE 0x200000
160 struct roc_bphy_irq_stack *curr_stack;
163 if (pthread_mutex_lock(&stacks_mutex))
166 STAILQ_FOREACH(curr_stack, &irq_stacks, entries) {
167 if (curr_stack->cpu == cpu) {
169 retval = ((char *)curr_stack->sp_buffer) +
175 curr_stack = plt_zmalloc(sizeof(struct roc_bphy_irq_stack), 0);
176 if (curr_stack == NULL)
179 curr_stack->sp_buffer =
180 plt_zmalloc(IRQ_ISR_STACK_SIZE * 2, ARM_STACK_ALIGNMENT);
181 if (curr_stack->sp_buffer == NULL)
184 curr_stack->cpu = cpu;
185 curr_stack->inuse = 0;
186 STAILQ_INSERT_TAIL(&irq_stacks, curr_stack, entries);
187 retval = ((char *)curr_stack->sp_buffer) + IRQ_ISR_STACK_SIZE;
190 pthread_mutex_unlock(&stacks_mutex);
194 plt_free(curr_stack);
197 pthread_mutex_unlock(&stacks_mutex);
202 roc_bphy_intr_handler(unsigned int irq_num)
204 struct roc_bphy_irq_chip *irq_chip;
205 const struct plt_memzone *mz;
207 mz = plt_memzone_lookup(ROC_BPHY_MEMZONE_NAME);
211 irq_chip = *(struct roc_bphy_irq_chip **)mz->addr;
212 if (irq_chip == NULL)
215 if (irq_chip->irq_vecs[irq_num].handler != NULL)
216 irq_chip->irq_vecs[irq_num].handler(
217 (int)irq_num, irq_chip->irq_vecs[irq_num].isr_data);
223 roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int cpu, int irq_num,
224 void (*isr)(int irq_num, void *isr_data),
227 struct roc_bphy_irq_usr_data irq_usr;
228 const struct plt_memzone *mz;
232 mz = plt_memzone_lookup(chip->mz_name);
234 /* what we want is just a pointer to chip, not object itself */
235 mz = plt_memzone_reserve_cache_align(chip->mz_name,
241 if (chip->irq_vecs[irq_num].handler != NULL)
244 irq_usr.isr_base = (uint64_t)roc_bphy_intr_handler;
245 irq_usr.sp = (uint64_t)roc_bphy_irq_stack_get(cpu);
250 /* On simulator memory locking operation takes much time. We want
251 * to skip this when running in such an environment.
253 env = getenv("BPHY_INTR_MLOCK_DISABLE");
255 rc = mlockall(MCL_CURRENT | MCL_FUTURE);
257 plt_warn("Failed to lock memory into RAM");
260 *((struct roc_bphy_irq_chip **)(mz->addr)) = chip;
261 irq_usr.irq_num = irq_num;
262 chip->irq_vecs[irq_num].handler_cpu = cpu;
263 chip->irq_vecs[irq_num].handler = isr;
264 chip->irq_vecs[irq_num].isr_data = isr_data;
265 retval = ioctl(chip->intfd, ROC_BPHY_IOC_SET_BPHY_HANDLER, &irq_usr);
267 roc_bphy_irq_stack_remove(cpu);
268 chip->irq_vecs[irq_num].handler = NULL;
269 chip->irq_vecs[irq_num].handler_cpu = -1;
278 roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
280 if (irq_num < 0 || (uint64_t)irq_num >= irq_chip->max_irq)
283 return irq_chip->avail_irq_bmask & BIT(irq_num);
287 roc_bphy_intr_max_get(struct roc_bphy_irq_chip *irq_chip)
289 return irq_chip->max_irq;
293 roc_bphy_intr_clear(struct roc_bphy_irq_chip *chip, int irq_num)
295 const struct plt_memzone *mz;
300 if ((uint64_t)irq_num >= chip->max_irq || irq_num < 0)
302 if (!roc_bphy_intr_available(chip, irq_num))
304 if (chip->irq_vecs[irq_num].handler == NULL)
306 mz = plt_memzone_lookup(chip->mz_name);
310 retval = ioctl(chip->intfd, ROC_BPHY_IOC_CLR_BPHY_HANDLER, irq_num);
312 roc_bphy_irq_stack_remove(chip->irq_vecs[irq_num].handler_cpu);
314 chip->irq_vecs[irq_num].isr_data = NULL;
315 chip->irq_vecs[irq_num].handler = NULL;
316 chip->irq_vecs[irq_num].handler_cpu = -1;
317 if (chip->n_handlers == 0) {
318 retval = plt_memzone_free(mz);
320 plt_err("Failed to free memzone: irq %d",
324 plt_err("Failed to clear bphy interrupt handler");
331 roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip,
332 struct roc_bphy_intr *intr)
336 if (!roc_bphy_intr_available(irq_chip, intr->irq_num))
339 ret = roc_bphy_irq_handler_set(irq_chip, intr->cpu, intr->irq_num,
340 intr->intr_handler, intr->isr_data);