1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
12 #include "roc_bphy_irq.h"
14 #define roc_cpuset_t cpu_set_t
16 struct roc_bphy_irq_usr_data {
23 struct roc_bphy_irq_stack {
24 STAILQ_ENTRY(roc_bphy_irq_stack) entries;
30 #define ROC_BPHY_MEMZONE_NAME "roc_bphy_mz"
31 #define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
33 #define ROC_BPHY_IOC_MAGIC 0xF3
34 #define ROC_BPHY_IOC_SET_BPHY_HANDLER \
35 _IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data)
36 #define ROC_BPHY_IOC_CLR_BPHY_HANDLER _IO(ROC_BPHY_IOC_MAGIC, 2)
37 #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
38 #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
40 static STAILQ_HEAD(slisthead, roc_bphy_irq_stack)
41 irq_stacks = STAILQ_HEAD_INITIALIZER(irq_stacks);
43 /* Note: it is assumed that as for now there is no multiprocess support */
44 static pthread_mutex_t stacks_mutex = PTHREAD_MUTEX_INITIALIZER;
46 struct roc_bphy_irq_chip *
47 roc_bphy_intr_init(void)
49 struct roc_bphy_irq_chip *irq_chip;
50 uint64_t max_irq, i, avail_irqs;
53 fd = open(ROC_BPHY_CTR_DEV_PATH, O_RDWR | O_SYNC);
55 plt_err("Failed to open %s", ROC_BPHY_CTR_DEV_PATH);
59 ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_MAX_IRQ, &max_irq);
61 plt_err("Failed to get max irq number via ioctl");
65 ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ, &avail_irqs);
67 plt_err("Failed to get available irqs bitmask via ioctl");
71 irq_chip = plt_zmalloc(sizeof(*irq_chip), 0);
72 if (irq_chip == NULL) {
73 plt_err("Failed to alloc irq_chip");
78 irq_chip->max_irq = max_irq;
79 irq_chip->avail_irq_bmask = avail_irqs;
81 plt_zmalloc(irq_chip->max_irq * sizeof(*irq_chip->irq_vecs), 0);
82 if (irq_chip->irq_vecs == NULL) {
83 plt_err("Failed to alloc irq_chip irq_vecs");
87 irq_chip->mz_name = plt_zmalloc(strlen(ROC_BPHY_MEMZONE_NAME) + 1, 0);
88 if (irq_chip->mz_name == NULL) {
89 plt_err("Failed to alloc irq_chip name");
92 plt_strlcpy(irq_chip->mz_name, ROC_BPHY_MEMZONE_NAME,
93 strlen(ROC_BPHY_MEMZONE_NAME) + 1);
95 for (i = 0; i < irq_chip->max_irq; i++) {
96 irq_chip->irq_vecs[i].fd = -1;
97 irq_chip->irq_vecs[i].handler_cpu = -1;
103 plt_free(irq_chip->irq_vecs);
115 roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
117 if (irq_chip == NULL)
120 close(irq_chip->intfd);
121 plt_free(irq_chip->mz_name);
122 plt_free(irq_chip->irq_vecs);
127 roc_bphy_irq_stack_remove(int cpu)
129 struct roc_bphy_irq_stack *curr_stack;
131 if (pthread_mutex_lock(&stacks_mutex))
134 STAILQ_FOREACH(curr_stack, &irq_stacks, entries) {
135 if (curr_stack->cpu == cpu)
139 if (curr_stack == NULL)
142 if (curr_stack->inuse > 0)
145 if (curr_stack->inuse == 0) {
146 STAILQ_REMOVE(&irq_stacks, curr_stack, roc_bphy_irq_stack,
148 plt_free(curr_stack->sp_buffer);
149 plt_free(curr_stack);
153 pthread_mutex_unlock(&stacks_mutex);
157 roc_bphy_irq_stack_get(int cpu)
159 #define ARM_STACK_ALIGNMENT (2 * sizeof(void *))
160 #define IRQ_ISR_STACK_SIZE 0x200000
162 struct roc_bphy_irq_stack *curr_stack;
165 if (pthread_mutex_lock(&stacks_mutex))
168 STAILQ_FOREACH(curr_stack, &irq_stacks, entries) {
169 if (curr_stack->cpu == cpu) {
171 retval = ((char *)curr_stack->sp_buffer) +
177 curr_stack = plt_zmalloc(sizeof(struct roc_bphy_irq_stack), 0);
178 if (curr_stack == NULL)
181 curr_stack->sp_buffer =
182 plt_zmalloc(IRQ_ISR_STACK_SIZE * 2, ARM_STACK_ALIGNMENT);
183 if (curr_stack->sp_buffer == NULL)
186 curr_stack->cpu = cpu;
187 curr_stack->inuse = 0;
188 STAILQ_INSERT_TAIL(&irq_stacks, curr_stack, entries);
189 retval = ((char *)curr_stack->sp_buffer) + IRQ_ISR_STACK_SIZE;
192 pthread_mutex_unlock(&stacks_mutex);
196 plt_free(curr_stack);
199 pthread_mutex_unlock(&stacks_mutex);
204 roc_bphy_intr_handler(unsigned int irq_num)
206 struct roc_bphy_irq_chip *irq_chip;
207 const struct plt_memzone *mz;
209 mz = plt_memzone_lookup(ROC_BPHY_MEMZONE_NAME);
213 irq_chip = *(struct roc_bphy_irq_chip **)mz->addr;
214 if (irq_chip == NULL)
217 if (irq_chip->irq_vecs[irq_num].handler != NULL)
218 irq_chip->irq_vecs[irq_num].handler(
219 (int)irq_num, irq_chip->irq_vecs[irq_num].isr_data);
225 roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num,
226 void (*isr)(int irq_num, void *isr_data),
229 roc_cpuset_t orig_cpuset, intr_cpuset;
230 struct roc_bphy_irq_usr_data irq_usr;
231 const struct plt_memzone *mz;
232 int i, retval, curr_cpu, rc;
235 mz = plt_memzone_lookup(chip->mz_name);
237 /* what we want is just a pointer to chip, not object itself */
238 mz = plt_memzone_reserve_cache_align(chip->mz_name,
244 if (chip->irq_vecs[irq_num].handler != NULL)
247 rc = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
250 plt_err("Failed to get affinity mask");
254 for (curr_cpu = -1, i = 0; i < CPU_SETSIZE; i++)
255 if (CPU_ISSET(i, &orig_cpuset))
260 CPU_ZERO(&intr_cpuset);
261 CPU_SET(curr_cpu, &intr_cpuset);
262 retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
265 plt_err("Failed to set affinity mask");
269 irq_usr.isr_base = (uint64_t)roc_bphy_intr_handler;
270 irq_usr.sp = (uint64_t)roc_bphy_irq_stack_get(curr_cpu);
271 irq_usr.cpu = curr_cpu;
272 if (irq_usr.sp == 0) {
273 rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
276 plt_err("Failed to restore affinity mask");
280 /* On simulator memory locking operation takes much time. We want
281 * to skip this when running in such an environment.
283 env = getenv("BPHY_INTR_MLOCK_DISABLE");
285 rc = mlockall(MCL_CURRENT | MCL_FUTURE);
287 plt_warn("Failed to lock memory into RAM");
290 *((struct roc_bphy_irq_chip **)(mz->addr)) = chip;
291 irq_usr.irq_num = irq_num;
292 chip->irq_vecs[irq_num].handler_cpu = curr_cpu;
293 chip->irq_vecs[irq_num].handler = isr;
294 chip->irq_vecs[irq_num].isr_data = isr_data;
295 retval = ioctl(chip->intfd, ROC_BPHY_IOC_SET_BPHY_HANDLER, &irq_usr);
297 roc_bphy_irq_stack_remove(curr_cpu);
298 chip->irq_vecs[irq_num].handler = NULL;
299 chip->irq_vecs[irq_num].handler_cpu = -1;
304 rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
307 plt_warn("Failed to restore affinity mask");
313 roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
315 if (irq_num < 0 || (uint64_t)irq_num >= irq_chip->max_irq)
318 return irq_chip->avail_irq_bmask & BIT(irq_num);
322 roc_bphy_intr_max_get(struct roc_bphy_irq_chip *irq_chip)
324 return irq_chip->max_irq;
328 roc_bphy_intr_clear(struct roc_bphy_irq_chip *chip, int irq_num)
330 roc_cpuset_t orig_cpuset, intr_cpuset;
331 const struct plt_memzone *mz;
336 if ((uint64_t)irq_num >= chip->max_irq || irq_num < 0)
338 if (!roc_bphy_intr_available(chip, irq_num))
340 if (chip->irq_vecs[irq_num].handler == NULL)
342 mz = plt_memzone_lookup(chip->mz_name);
346 retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
349 plt_warn("Failed to get affinity mask");
350 CPU_ZERO(&orig_cpuset);
351 CPU_SET(0, &orig_cpuset);
354 CPU_ZERO(&intr_cpuset);
355 CPU_SET(chip->irq_vecs[irq_num].handler_cpu, &intr_cpuset);
356 retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
359 plt_warn("Failed to set affinity mask");
360 CPU_ZERO(&orig_cpuset);
361 CPU_SET(0, &orig_cpuset);
364 retval = ioctl(chip->intfd, ROC_BPHY_IOC_CLR_BPHY_HANDLER, irq_num);
366 roc_bphy_irq_stack_remove(chip->irq_vecs[irq_num].handler_cpu);
368 chip->irq_vecs[irq_num].isr_data = NULL;
369 chip->irq_vecs[irq_num].handler = NULL;
370 chip->irq_vecs[irq_num].handler_cpu = -1;
371 if (chip->n_handlers == 0) {
372 retval = plt_memzone_free(mz);
374 plt_err("Failed to free memzone: irq %d",
378 plt_err("Failed to clear bphy interrupt handler");
381 retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
384 plt_warn("Failed to restore affinity mask");
385 CPU_ZERO(&orig_cpuset);
386 CPU_SET(0, &orig_cpuset);
393 roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip,
394 struct roc_bphy_intr *intr)
396 roc_cpuset_t orig_cpuset, intr_cpuset;
400 if (!roc_bphy_intr_available(irq_chip, intr->irq_num))
403 retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
406 plt_err("Failed to get affinity mask");
410 CPU_ZERO(&intr_cpuset);
411 CPU_SET(intr->cpu, &intr_cpuset);
412 retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
415 plt_err("Failed to set affinity mask");
419 ret = roc_bphy_irq_handler_set(irq_chip, intr->irq_num,
420 intr->intr_handler, intr->isr_data);
422 retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
425 plt_warn("Failed to restore affinity mask");