1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
8 #define CPT_IQ_FC_LEN 128
9 #define CPT_IQ_GRP_LEN 16
11 #define CPT_IQ_NB_DESC_MULTIPLIER 40
13 /* The effective queue size to software is (CPT_LF_Q_SIZE[SIZE_DIV40] - 1 - 8).
15 * CPT requires 320 free entries (+8). And 40 entries are required for
16 * allowing CPT to discard packet when the queues are full (+1).
18 #define CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) \
19 (PLT_DIV_CEIL(nb_desc, CPT_IQ_NB_DESC_MULTIPLIER) + 1 + 8)
21 #define CPT_IQ_GRP_SIZE(nb_desc) \
22 (CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * CPT_IQ_GRP_LEN)
24 #define CPT_LF_MAX_NB_DESC 128000
25 #define CPT_LF_DEFAULT_NB_DESC 1024
28 cpt_lf_misc_intr_enb_dis(struct roc_cpt_lf *lf, bool enb)
30 /* Enable all cpt lf error irqs except RQ_DISABLED and CQ_DISABLED */
32 plt_write64((BIT_ULL(6) | BIT_ULL(5) | BIT_ULL(3) | BIT_ULL(2) |
34 lf->rbase + CPT_LF_MISC_INT_ENA_W1S);
36 plt_write64((BIT_ULL(6) | BIT_ULL(5) | BIT_ULL(3) | BIT_ULL(2) |
38 lf->rbase + CPT_LF_MISC_INT_ENA_W1C);
42 cpt_lf_misc_irq(void *param)
44 struct roc_cpt_lf *lf = (struct roc_cpt_lf *)param;
45 struct dev *dev = lf->dev;
48 intr = plt_read64(lf->rbase + CPT_LF_MISC_INT);
52 plt_err("Err_irq=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
55 plt_write64(intr, lf->rbase + CPT_LF_MISC_INT);
59 cpt_lf_register_misc_irq(struct roc_cpt_lf *lf)
61 struct plt_pci_device *pci_dev = lf->pci_dev;
62 struct plt_intr_handle *handle;
65 handle = &pci_dev->intr_handle;
67 vec = lf->msixoff + CPT_LF_INT_VEC_MISC;
68 /* Clear err interrupt */
69 cpt_lf_misc_intr_enb_dis(lf, false);
70 /* Set used interrupt vectors */
71 rc = dev_irq_register(handle, cpt_lf_misc_irq, lf, vec);
72 /* Enable all dev interrupt except for RQ_DISABLED */
73 cpt_lf_misc_intr_enb_dis(lf, true);
79 cpt_lf_unregister_misc_irq(struct roc_cpt_lf *lf)
81 struct plt_pci_device *pci_dev = lf->pci_dev;
82 struct plt_intr_handle *handle;
85 handle = &pci_dev->intr_handle;
87 vec = lf->msixoff + CPT_LF_INT_VEC_MISC;
88 /* Clear err interrupt */
89 cpt_lf_misc_intr_enb_dis(lf, false);
90 dev_irq_unregister(handle, cpt_lf_misc_irq, lf, vec);
94 cpt_lf_done_intr_enb_dis(struct roc_cpt_lf *lf, bool enb)
97 plt_write64(0x1, lf->rbase + CPT_LF_DONE_INT_ENA_W1S);
99 plt_write64(0x1, lf->rbase + CPT_LF_DONE_INT_ENA_W1C);
103 cpt_lf_done_irq(void *param)
105 struct roc_cpt_lf *lf = param;
109 /* Read the number of completed requests */
110 intr = plt_read64(lf->rbase + CPT_LF_DONE);
114 done_wait = plt_read64(lf->rbase + CPT_LF_DONE_WAIT);
116 /* Acknowledge the number of completed requests */
117 plt_write64(intr, lf->rbase + CPT_LF_DONE_ACK);
119 plt_write64(done_wait, lf->rbase + CPT_LF_DONE_WAIT);
123 cpt_lf_register_done_irq(struct roc_cpt_lf *lf)
125 struct plt_pci_device *pci_dev = lf->pci_dev;
126 struct plt_intr_handle *handle;
129 handle = &pci_dev->intr_handle;
131 vec = lf->msixoff + CPT_LF_INT_VEC_DONE;
133 /* Clear done interrupt */
134 cpt_lf_done_intr_enb_dis(lf, false);
136 /* Set used interrupt vectors */
137 rc = dev_irq_register(handle, cpt_lf_done_irq, lf, vec);
139 /* Enable done interrupt */
140 cpt_lf_done_intr_enb_dis(lf, true);
146 cpt_lf_unregister_done_irq(struct roc_cpt_lf *lf)
148 struct plt_pci_device *pci_dev = lf->pci_dev;
149 struct plt_intr_handle *handle;
152 handle = &pci_dev->intr_handle;
154 vec = lf->msixoff + CPT_LF_INT_VEC_DONE;
156 /* Clear done interrupt */
157 cpt_lf_done_intr_enb_dis(lf, false);
158 dev_irq_unregister(handle, cpt_lf_done_irq, lf, vec);
162 cpt_lf_register_irqs(struct roc_cpt_lf *lf)
166 if (lf->msixoff == MSIX_VECTOR_INVALID) {
167 plt_err("Invalid CPTLF MSIX vector offset vector: 0x%x",
172 /* Register lf err interrupt */
173 rc = cpt_lf_register_misc_irq(lf);
175 plt_err("Error registering IRQs");
177 rc = cpt_lf_register_done_irq(lf);
179 plt_err("Error registering IRQs");
185 cpt_lf_unregister_irqs(struct roc_cpt_lf *lf)
187 cpt_lf_unregister_misc_irq(lf);
188 cpt_lf_unregister_done_irq(lf);
192 cpt_lf_dump(struct roc_cpt_lf *lf)
194 plt_cpt_dbg("CPT LF");
195 plt_cpt_dbg("RBASE: 0x%016" PRIx64, lf->rbase);
196 plt_cpt_dbg("LMT_BASE: 0x%016" PRIx64, lf->lmt_base);
197 plt_cpt_dbg("MSIXOFF: 0x%x", lf->msixoff);
198 plt_cpt_dbg("LF_ID: 0x%x", lf->lf_id);
199 plt_cpt_dbg("NB DESC: %d", lf->nb_desc);
200 plt_cpt_dbg("FC_ADDR: 0x%016" PRIx64, (uintptr_t)lf->fc_addr);
201 plt_cpt_dbg("CQ.VADDR: 0x%016" PRIx64, (uintptr_t)lf->iq_vaddr);
203 plt_cpt_dbg("CPT LF REG:");
204 plt_cpt_dbg("LF_CTL[0x%016llx]: 0x%016" PRIx64, CPT_LF_CTL,
205 plt_read64(lf->rbase + CPT_LF_CTL));
206 plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016" PRIx64, CPT_LF_INPROG,
207 plt_read64(lf->rbase + CPT_LF_INPROG));
209 plt_cpt_dbg("Q_BASE[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_BASE,
210 plt_read64(lf->rbase + CPT_LF_Q_BASE));
211 plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_SIZE,
212 plt_read64(lf->rbase + CPT_LF_Q_SIZE));
213 plt_cpt_dbg("Q_INST_PTR[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_INST_PTR,
214 plt_read64(lf->rbase + CPT_LF_Q_INST_PTR));
215 plt_cpt_dbg("Q_GRP_PTR[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_GRP_PTR,
216 plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR));
220 roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)
222 struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
223 struct cpt_rxc_time_cfg_req *req;
224 struct dev *dev = &cpt->dev;
226 req = mbox_alloc_msg_cpt_rxc_time_cfg(dev->mbox);
232 /* The step value is in microseconds. */
233 req->step = cfg->step;
235 /* The timeout will be: limit * step microseconds */
236 req->zombie_limit = cfg->zombie_limit;
237 req->zombie_thres = cfg->zombie_thres;
239 /* The timeout will be: limit * step microseconds */
240 req->active_limit = cfg->active_limit;
241 req->active_thres = cfg->active_thres;
243 return mbox_process(dev->mbox);
247 cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp)
249 struct mbox *mbox = dev->mbox;
252 /* Get MSIX vector offsets */
253 mbox_alloc_msg_msix_offset(mbox);
254 rc = mbox_process_msg(mbox, (void *)msix_rsp);
260 cpt_lfs_attach(struct dev *dev, uint8_t blkaddr, bool modify, uint16_t nb_lf)
262 struct mbox *mbox = dev->mbox;
263 struct rsrc_attach_req *req;
265 if (blkaddr != RVU_BLOCK_ADDR_CPT0 && blkaddr != RVU_BLOCK_ADDR_CPT1)
269 req = mbox_alloc_msg_attach_resources(mbox);
274 req->modify = modify;
275 req->cpt_blkaddr = blkaddr;
277 return mbox_process(mbox);
281 cpt_lfs_detach(struct dev *dev)
283 struct mbox *mbox = dev->mbox;
284 struct rsrc_detach_req *req;
286 req = mbox_alloc_msg_detach_resources(mbox);
293 return mbox_process(mbox);
297 cpt_available_lfs_get(struct dev *dev, uint16_t *nb_lf)
299 struct mbox *mbox = dev->mbox;
300 struct free_rsrcs_rsp *rsp;
303 mbox_alloc_msg_free_rsrc_cnt(mbox);
305 rc = mbox_process_msg(mbox, (void *)&rsp);
314 cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr,
317 struct cpt_lf_alloc_req_msg *req;
318 struct mbox *mbox = dev->mbox;
320 if (blkaddr != RVU_BLOCK_ADDR_CPT0 && blkaddr != RVU_BLOCK_ADDR_CPT1)
323 PLT_SET_USED(inl_dev_sso);
325 req = mbox_alloc_msg_cpt_lf_alloc(mbox);
326 req->nix_pf_func = 0;
327 req->sso_pf_func = idev_sso_pffunc_get();
328 req->eng_grpmsk = eng_grpmsk;
329 req->blkaddr = blkaddr;
331 return mbox_process(mbox);
335 cpt_lfs_free(struct dev *dev)
337 mbox_alloc_msg_cpt_lf_free(dev->mbox);
339 return mbox_process(dev->mbox);
343 cpt_hardware_caps_get(struct dev *dev, union cpt_eng_caps *hw_caps)
345 struct cpt_caps_rsp_msg *rsp;
348 mbox_alloc_msg_cpt_caps_get(dev->mbox);
350 ret = mbox_process_msg(dev->mbox, (void *)&rsp);
354 mbox_memcpy(hw_caps, rsp->eng_caps,
355 sizeof(union cpt_eng_caps) * CPT_MAX_ENG_TYPES);
361 cpt_lf_iq_mem_calc(uint32_t nb_desc)
365 /* Space for instruction group memory */
366 len = CPT_IQ_GRP_SIZE(nb_desc);
369 len = PLT_ALIGN(len, ROC_ALIGN);
372 len += CPT_IQ_FC_LEN;
374 /* For instruction queues */
375 len += CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * CPT_IQ_NB_DESC_MULTIPLIER *
376 sizeof(struct cpt_inst_s);
382 cpt_iq_init(struct roc_cpt_lf *lf)
384 union cpt_lf_q_size lf_q_size = {.u = 0x0};
385 union cpt_lf_q_base lf_q_base = {.u = 0x0};
386 union cpt_lf_inprog lf_inprog;
387 union cpt_lf_ctl lf_ctl;
390 lf->io_addr = lf->rbase + CPT_LF_NQX(0);
392 /* Disable command queue */
393 roc_cpt_iq_disable(lf);
395 /* Set command queue base address */
396 addr = (uintptr_t)lf->iq_vaddr +
397 PLT_ALIGN(CPT_IQ_GRP_SIZE(lf->nb_desc), ROC_ALIGN);
401 plt_write64(lf_q_base.u, lf->rbase + CPT_LF_Q_BASE);
403 /* Set command queue size */
404 lf_q_size.s.size_div40 = CPT_IQ_NB_DESC_SIZE_DIV40(lf->nb_desc);
405 plt_write64(lf_q_size.u, lf->rbase + CPT_LF_Q_SIZE);
407 /* Enable command queue execution */
408 lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);
409 lf_inprog.s.eena = 1;
410 plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);
412 /* Enable instruction queue enqueuing */
413 lf_ctl.u = plt_read64(lf->rbase + CPT_LF_CTL);
416 lf_ctl.s.fc_up_crossing = 1;
417 lf_ctl.s.fc_hyst_bits = CPT_FC_NUM_HYST_BITS;
418 plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);
420 lf->fc_addr = (uint64_t *)addr;
424 roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf)
426 struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
427 uint8_t blkaddr = RVU_BLOCK_ADDR_CPT0;
428 struct msix_offset_rsp *rsp;
432 /* Request LF resources */
433 rc = cpt_lfs_attach(&cpt->dev, blkaddr, false, nb_lf);
437 eng_grpmsk = (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_AE]) |
438 (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]) |
439 (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_IE]);
441 rc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr, false);
445 rc = cpt_get_msix_offset(&cpt->dev, &rsp);
449 for (i = 0; i < nb_lf; i++)
450 cpt->lf_msix_off[i] =
451 (cpt->lf_blkaddr[i] == RVU_BLOCK_ADDR_CPT1) ?
452 rsp->cpt1_lf_msixoff[i] :
453 rsp->cptlf_msixoff[i];
455 roc_cpt->nb_lf = nb_lf;
460 cpt_lfs_free(&cpt->dev);
462 cpt_lfs_detach(&cpt->dev);
467 cpt_get_blkaddr(struct dev *dev)
472 /* Reading the discovery register to know which CPT is the LF
473 * attached to. Assume CPT LF's of only one block are attached
477 off = RVU_VF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);
479 off = RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);
481 reg = plt_read64(dev->bar2 + off);
483 return reg & 0x1FFULL ? RVU_BLOCK_ADDR_CPT1 : RVU_BLOCK_ADDR_CPT0;
487 cpt_lf_init(struct roc_cpt_lf *lf)
489 struct dev *dev = lf->dev;
494 if (lf->nb_desc == 0 || lf->nb_desc > CPT_LF_MAX_NB_DESC)
495 lf->nb_desc = CPT_LF_DEFAULT_NB_DESC;
497 /* Allocate memory for instruction queue for CPT LF. */
498 iq_mem = plt_zmalloc(cpt_lf_iq_mem_calc(lf->nb_desc), ROC_ALIGN);
502 blkaddr = cpt_get_blkaddr(dev);
503 lf->rbase = dev->bar2 + ((blkaddr << 20) | (lf->lf_id << 12));
504 lf->iq_vaddr = iq_mem;
505 lf->lmt_base = dev->lmt_base;
506 lf->pf_func = dev->pf_func;
508 /* Initialize instruction queue */
511 rc = cpt_lf_register_irqs(lf);
519 roc_cpt_iq_disable(lf);
525 roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf)
527 struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
531 lf->roc_cpt = roc_cpt;
532 lf->msixoff = cpt->lf_msix_off[lf->lf_id];
533 lf->pci_dev = cpt->pci_dev;
535 rc = cpt_lf_init(lf);
539 /* LF init successful */
540 roc_cpt->lf[lf->lf_id] = lf;
545 roc_cpt_dev_init(struct roc_cpt *roc_cpt)
547 struct plt_pci_device *pci_dev;
548 uint16_t nb_lf_avail;
553 if (roc_cpt == NULL || roc_cpt->pci_dev == NULL)
556 PLT_STATIC_ASSERT(sizeof(struct cpt) <= ROC_CPT_MEM_SZ);
558 cpt = roc_cpt_to_cpt_priv(roc_cpt);
559 memset(cpt, 0, sizeof(*cpt));
560 pci_dev = roc_cpt->pci_dev;
563 /* Initialize device */
564 rc = dev_init(dev, pci_dev);
566 plt_err("Failed to init roc device");
570 cpt->pci_dev = pci_dev;
571 roc_cpt->lmt_base = dev->lmt_base;
573 rc = cpt_hardware_caps_get(dev, roc_cpt->hw_caps);
575 plt_err("Could not determine hardware capabilities");
579 rc = cpt_available_lfs_get(&cpt->dev, &nb_lf_avail);
581 plt_err("Could not get available lfs");
585 /* Reserve 1 CPT LF for inline inbound */
586 nb_lf_avail = PLT_MIN(nb_lf_avail, ROC_CPT_MAX_LFS - 1);
588 roc_cpt->nb_lf_avail = nb_lf_avail;
590 dev->roc_cpt = roc_cpt;
592 /* Set it to idev if not already present */
593 if (!roc_idev_cpt_get())
594 roc_idev_cpt_set(roc_cpt);
603 roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr)
605 union cpt_lf_ctx_flush reg;
611 reg.s.pf_func = lf->pf_func;
615 plt_write64(reg.u, lf->rbase + CPT_LF_CTX_FLUSH);
621 cpt_lf_fini(struct roc_cpt_lf *lf)
623 /* Unregister IRQ's */
624 cpt_lf_unregister_irqs(lf);
627 roc_cpt_iq_disable(lf);
630 plt_free(lf->iq_vaddr);
635 roc_cpt_lf_fini(struct roc_cpt_lf *lf)
639 lf->roc_cpt->lf[lf->lf_id] = NULL;
644 roc_cpt_dev_fini(struct roc_cpt *roc_cpt)
646 struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
651 /* Remove idev references */
652 if (roc_idev_cpt_get() == roc_cpt)
653 roc_idev_cpt_set(NULL);
655 roc_cpt->nb_lf_avail = 0;
657 roc_cpt->lmt_base = 0;
659 return dev_fini(&cpt->dev, cpt->pci_dev);
663 roc_cpt_dev_clear(struct roc_cpt *roc_cpt)
665 struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
671 for (i = 0; i < roc_cpt->nb_lf; i++)
672 cpt->lf_msix_off[i] = 0;
676 cpt_lfs_free(&cpt->dev);
678 cpt_lfs_detach(&cpt->dev);
682 roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type)
684 struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
685 struct dev *dev = &cpt->dev;
686 struct cpt_eng_grp_req *req;
687 struct cpt_eng_grp_rsp *rsp;
690 req = mbox_alloc_msg_cpt_eng_grp_get(dev->mbox);
695 case CPT_ENG_TYPE_AE:
696 case CPT_ENG_TYPE_SE:
697 case CPT_ENG_TYPE_IE:
703 req->eng_type = eng_type;
704 ret = mbox_process_msg(dev->mbox, (void *)&rsp);
708 if (rsp->eng_grp_num > 8) {
709 plt_err("Invalid CPT engine group");
713 roc_cpt->eng_grp[eng_type] = rsp->eng_grp_num;
715 return rsp->eng_grp_num;
719 roc_cpt_iq_disable(struct roc_cpt_lf *lf)
721 union cpt_lf_ctl lf_ctl = {.u = 0x0};
722 union cpt_lf_inprog lf_inprog;
725 /* Disable instructions enqueuing */
726 plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);
728 /* Wait for instruction queue to become empty */
730 lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);
731 if (!lf_inprog.s.inflight)
736 plt_err("CPT LF %d is still busy", lf->lf_id);
742 /* Disable executions in the LF's queue.
743 * The queue should be empty at this point
745 lf_inprog.s.eena = 0x0;
746 plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);