1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
8 #define CPT_IQ_FC_LEN 128
9 #define CPT_IQ_GRP_LEN 16
11 #define CPT_IQ_NB_DESC_MULTIPLIER 40
13 /* The effective queue size to software is (CPT_LF_Q_SIZE[SIZE_DIV40] - 1 - 8).
15 * CPT requires 320 free entries (+8). And 40 entries are required for
16 * allowing CPT to discard packet when the queues are full (+1).
18 #define CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) \
19 (PLT_DIV_CEIL(nb_desc, CPT_IQ_NB_DESC_MULTIPLIER) + 1 + 8)
21 #define CPT_IQ_GRP_SIZE(nb_desc) \
22 (CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * CPT_IQ_GRP_LEN)
24 #define CPT_LF_MAX_NB_DESC 128000
25 #define CPT_LF_DEFAULT_NB_DESC 1024
28 cpt_lf_misc_intr_enb_dis(struct roc_cpt_lf *lf, bool enb)
30 /* Enable all cpt lf error irqs except RQ_DISABLED and CQ_DISABLED */
32 plt_write64((BIT_ULL(6) | BIT_ULL(5) | BIT_ULL(3) | BIT_ULL(2) |
34 lf->rbase + CPT_LF_MISC_INT_ENA_W1S);
36 plt_write64((BIT_ULL(6) | BIT_ULL(5) | BIT_ULL(3) | BIT_ULL(2) |
38 lf->rbase + CPT_LF_MISC_INT_ENA_W1C);
42 cpt_lf_misc_irq(void *param)
44 struct roc_cpt_lf *lf = (struct roc_cpt_lf *)param;
45 struct dev *dev = lf->dev;
48 intr = plt_read64(lf->rbase + CPT_LF_MISC_INT);
52 plt_err("Err_irq=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
54 /* Dump lf registers */
58 plt_write64(intr, lf->rbase + CPT_LF_MISC_INT);
62 cpt_lf_register_misc_irq(struct roc_cpt_lf *lf)
64 struct plt_pci_device *pci_dev = lf->pci_dev;
65 struct plt_intr_handle *handle;
68 handle = pci_dev->intr_handle;
70 vec = lf->msixoff + CPT_LF_INT_VEC_MISC;
71 /* Clear err interrupt */
72 cpt_lf_misc_intr_enb_dis(lf, false);
73 /* Set used interrupt vectors */
74 rc = dev_irq_register(handle, cpt_lf_misc_irq, lf, vec);
75 /* Enable all dev interrupt except for RQ_DISABLED */
76 cpt_lf_misc_intr_enb_dis(lf, true);
82 cpt_lf_unregister_misc_irq(struct roc_cpt_lf *lf)
84 struct plt_pci_device *pci_dev = lf->pci_dev;
85 struct plt_intr_handle *handle;
88 handle = pci_dev->intr_handle;
90 vec = lf->msixoff + CPT_LF_INT_VEC_MISC;
91 /* Clear err interrupt */
92 cpt_lf_misc_intr_enb_dis(lf, false);
93 dev_irq_unregister(handle, cpt_lf_misc_irq, lf, vec);
97 cpt_lf_done_intr_enb_dis(struct roc_cpt_lf *lf, bool enb)
100 plt_write64(0x1, lf->rbase + CPT_LF_DONE_INT_ENA_W1S);
102 plt_write64(0x1, lf->rbase + CPT_LF_DONE_INT_ENA_W1C);
106 cpt_lf_done_irq(void *param)
108 struct roc_cpt_lf *lf = param;
112 /* Read the number of completed requests */
113 intr = plt_read64(lf->rbase + CPT_LF_DONE);
117 done_wait = plt_read64(lf->rbase + CPT_LF_DONE_WAIT);
119 /* Acknowledge the number of completed requests */
120 plt_write64(intr, lf->rbase + CPT_LF_DONE_ACK);
122 plt_write64(done_wait, lf->rbase + CPT_LF_DONE_WAIT);
126 cpt_lf_register_done_irq(struct roc_cpt_lf *lf)
128 struct plt_pci_device *pci_dev = lf->pci_dev;
129 struct plt_intr_handle *handle;
132 handle = pci_dev->intr_handle;
134 vec = lf->msixoff + CPT_LF_INT_VEC_DONE;
136 /* Clear done interrupt */
137 cpt_lf_done_intr_enb_dis(lf, false);
139 /* Set used interrupt vectors */
140 rc = dev_irq_register(handle, cpt_lf_done_irq, lf, vec);
142 /* Enable done interrupt */
143 cpt_lf_done_intr_enb_dis(lf, true);
149 cpt_lf_unregister_done_irq(struct roc_cpt_lf *lf)
151 struct plt_pci_device *pci_dev = lf->pci_dev;
152 struct plt_intr_handle *handle;
155 handle = pci_dev->intr_handle;
157 vec = lf->msixoff + CPT_LF_INT_VEC_DONE;
159 /* Clear done interrupt */
160 cpt_lf_done_intr_enb_dis(lf, false);
161 dev_irq_unregister(handle, cpt_lf_done_irq, lf, vec);
165 cpt_lf_register_irqs(struct roc_cpt_lf *lf)
169 if (lf->msixoff == MSIX_VECTOR_INVALID) {
170 plt_err("Invalid CPTLF MSIX vector offset vector: 0x%x",
175 /* Register lf err interrupt */
176 rc = cpt_lf_register_misc_irq(lf);
178 plt_err("Error registering IRQs");
180 rc = cpt_lf_register_done_irq(lf);
182 plt_err("Error registering IRQs");
188 cpt_lf_unregister_irqs(struct roc_cpt_lf *lf)
190 cpt_lf_unregister_misc_irq(lf);
191 cpt_lf_unregister_done_irq(lf);
195 cpt_lf_dump(struct roc_cpt_lf *lf)
197 plt_cpt_dbg("CPT LF");
198 plt_cpt_dbg("RBASE: 0x%016" PRIx64, lf->rbase);
199 plt_cpt_dbg("LMT_BASE: 0x%016" PRIx64, lf->lmt_base);
200 plt_cpt_dbg("MSIXOFF: 0x%x", lf->msixoff);
201 plt_cpt_dbg("LF_ID: 0x%x", lf->lf_id);
202 plt_cpt_dbg("NB DESC: %d", lf->nb_desc);
203 plt_cpt_dbg("FC_ADDR: 0x%016" PRIx64, (uintptr_t)lf->fc_addr);
204 plt_cpt_dbg("CQ.VADDR: 0x%016" PRIx64, (uintptr_t)lf->iq_vaddr);
206 plt_cpt_dbg("CPT LF REG:");
207 plt_cpt_dbg("LF_CTL[0x%016llx]: 0x%016" PRIx64, CPT_LF_CTL,
208 plt_read64(lf->rbase + CPT_LF_CTL));
209 plt_cpt_dbg("LF_INPROG[0x%016llx]: 0x%016" PRIx64, CPT_LF_INPROG,
210 plt_read64(lf->rbase + CPT_LF_INPROG));
212 plt_cpt_dbg("Q_BASE[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_BASE,
213 plt_read64(lf->rbase + CPT_LF_Q_BASE));
214 plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_SIZE,
215 plt_read64(lf->rbase + CPT_LF_Q_SIZE));
216 plt_cpt_dbg("Q_INST_PTR[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_INST_PTR,
217 plt_read64(lf->rbase + CPT_LF_Q_INST_PTR));
218 plt_cpt_dbg("Q_GRP_PTR[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_GRP_PTR,
219 plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR));
223 cpt_lf_outb_cfg(struct dev *dev, uint16_t sso_pf_func, uint16_t nix_pf_func,
224 uint8_t lf_id, bool ena)
226 struct cpt_inline_ipsec_cfg_msg *req;
227 struct mbox *mbox = dev->mbox;
229 req = mbox_alloc_msg_cpt_inline_ipsec_cfg(mbox);
233 req->dir = CPT_INLINE_OUTBOUND;
237 req->sso_pf_func = sso_pf_func;
238 req->nix_pf_func = nix_pf_func;
243 return mbox_process(mbox);
247 roc_cpt_inline_ipsec_cfg(struct dev *cpt_dev, uint8_t lf_id,
248 struct roc_nix *roc_nix)
250 bool ena = roc_nix ? true : false;
251 uint16_t nix_pf_func = 0;
252 uint16_t sso_pf_func = 0;
255 nix_pf_func = roc_nix_get_pf_func(roc_nix);
256 sso_pf_func = idev_sso_pffunc_get();
259 return cpt_lf_outb_cfg(cpt_dev, sso_pf_func, nix_pf_func, lf_id, ena);
263 roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, uint16_t param1,
266 struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
267 struct cpt_rx_inline_lf_cfg_msg *req;
270 mbox = cpt->dev.mbox;
272 req = mbox_alloc_msg_cpt_rx_inline_lf_cfg(mbox);
276 req->sso_pf_func = idev_sso_pffunc_get();
277 req->param1 = param1;
278 req->param2 = param2;
280 return mbox_process(mbox);
284 roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)
286 struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
287 struct cpt_rxc_time_cfg_req *req;
288 struct dev *dev = &cpt->dev;
290 req = mbox_alloc_msg_cpt_rxc_time_cfg(dev->mbox);
296 /* The step value is in microseconds. */
297 req->step = cfg->step;
299 /* The timeout will be: limit * step microseconds */
300 req->zombie_limit = cfg->zombie_limit;
301 req->zombie_thres = cfg->zombie_thres;
303 /* The timeout will be: limit * step microseconds */
304 req->active_limit = cfg->active_limit;
305 req->active_thres = cfg->active_thres;
307 return mbox_process(dev->mbox);
311 cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp)
313 struct mbox *mbox = dev->mbox;
316 /* Get MSIX vector offsets */
317 mbox_alloc_msg_msix_offset(mbox);
318 rc = mbox_process_msg(mbox, (void *)msix_rsp);
324 cpt_lfs_attach(struct dev *dev, uint8_t blkaddr, bool modify, uint16_t nb_lf)
326 struct mbox *mbox = dev->mbox;
327 struct rsrc_attach_req *req;
329 if (blkaddr != RVU_BLOCK_ADDR_CPT0 && blkaddr != RVU_BLOCK_ADDR_CPT1)
333 req = mbox_alloc_msg_attach_resources(mbox);
338 req->modify = modify;
339 req->cpt_blkaddr = blkaddr;
341 return mbox_process(mbox);
345 cpt_lfs_detach(struct dev *dev)
347 struct mbox *mbox = dev->mbox;
348 struct rsrc_detach_req *req;
350 req = mbox_alloc_msg_detach_resources(mbox);
357 return mbox_process(mbox);
361 cpt_available_lfs_get(struct dev *dev, uint16_t *nb_lf)
363 struct mbox *mbox = dev->mbox;
364 struct free_rsrcs_rsp *rsp;
367 mbox_alloc_msg_free_rsrc_cnt(mbox);
369 rc = mbox_process_msg(mbox, (void *)&rsp);
373 *nb_lf = PLT_MAX((uint16_t)rsp->cpt, (uint16_t)rsp->cpt1);
378 cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr,
381 struct cpt_lf_alloc_req_msg *req;
382 struct mbox *mbox = dev->mbox;
384 if (blkaddr != RVU_BLOCK_ADDR_CPT0 && blkaddr != RVU_BLOCK_ADDR_CPT1)
387 req = mbox_alloc_msg_cpt_lf_alloc(mbox);
391 req->nix_pf_func = 0;
392 if (inl_dev_sso && nix_inl_dev_pffunc_get())
393 req->sso_pf_func = nix_inl_dev_pffunc_get();
395 req->sso_pf_func = idev_sso_pffunc_get();
396 req->eng_grpmsk = eng_grpmsk;
397 req->blkaddr = blkaddr;
399 return mbox_process(mbox);
403 cpt_lfs_free(struct dev *dev)
405 mbox_alloc_msg_cpt_lf_free(dev->mbox);
407 return mbox_process(dev->mbox);
411 cpt_hardware_caps_get(struct dev *dev, struct roc_cpt *roc_cpt)
413 struct cpt_caps_rsp_msg *rsp;
416 mbox_alloc_msg_cpt_caps_get(dev->mbox);
418 ret = mbox_process_msg(dev->mbox, (void *)&rsp);
422 roc_cpt->cpt_revision = rsp->cpt_revision;
423 mbox_memcpy(roc_cpt->hw_caps, rsp->eng_caps,
424 sizeof(union cpt_eng_caps) * CPT_MAX_ENG_TYPES);
430 cpt_lf_iq_mem_calc(uint32_t nb_desc)
434 /* Space for instruction group memory */
435 len = CPT_IQ_GRP_SIZE(nb_desc);
438 len = PLT_ALIGN(len, ROC_ALIGN);
441 len += CPT_IQ_FC_LEN;
443 /* For instruction queues */
444 len += PLT_ALIGN(CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) *
445 CPT_IQ_NB_DESC_MULTIPLIER *
446 sizeof(struct cpt_inst_s),
453 cpt_iq_init(struct roc_cpt_lf *lf)
455 union cpt_lf_q_size lf_q_size = {.u = 0x0};
456 union cpt_lf_q_base lf_q_base = {.u = 0x0};
459 lf->io_addr = lf->rbase + CPT_LF_NQX(0);
461 /* Disable command queue */
462 roc_cpt_iq_disable(lf);
464 /* Set command queue base address */
465 addr = (uintptr_t)lf->iq_vaddr +
466 PLT_ALIGN(CPT_IQ_GRP_SIZE(lf->nb_desc), ROC_ALIGN);
470 plt_write64(lf_q_base.u, lf->rbase + CPT_LF_Q_BASE);
472 /* Set command queue size */
473 lf_q_size.s.size_div40 = CPT_IQ_NB_DESC_SIZE_DIV40(lf->nb_desc);
474 plt_write64(lf_q_size.u, lf->rbase + CPT_LF_Q_SIZE);
476 lf->fc_addr = (uint64_t *)addr;
477 lf->fc_hyst_bits = plt_log2_u32(lf->nb_desc) / 2;
478 lf->fc_thresh = lf->nb_desc - (lf->nb_desc % (1 << lf->fc_hyst_bits));
482 roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf)
484 struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
485 uint8_t blkaddr[ROC_CPT_MAX_BLKS];
486 struct msix_offset_rsp *rsp;
491 blkaddr[0] = RVU_BLOCK_ADDR_CPT0;
492 blkaddr[1] = RVU_BLOCK_ADDR_CPT1;
494 if ((roc_cpt->cpt_revision == ROC_CPT_REVISION_ID_98XX) &&
495 (cpt->dev.pf_func & 0x1))
496 blknum = (blknum + 1) % ROC_CPT_MAX_BLKS;
498 /* Request LF resources */
499 rc = cpt_lfs_attach(&cpt->dev, blkaddr[blknum], true, nb_lf);
501 /* Request LFs from another block if current block has less LFs */
502 if (roc_cpt->cpt_revision == ROC_CPT_REVISION_ID_98XX && rc == ENOSPC) {
503 blknum = (blknum + 1) % ROC_CPT_MAX_BLKS;
504 rc = cpt_lfs_attach(&cpt->dev, blkaddr[blknum], true, nb_lf);
507 plt_err("Could not attach LFs");
511 for (i = 0; i < nb_lf; i++)
512 cpt->lf_blkaddr[i] = blkaddr[blknum];
514 eng_grpmsk = (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_AE]) |
515 (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]) |
516 (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_IE]);
518 rc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr[blknum], false);
522 rc = cpt_get_msix_offset(&cpt->dev, &rsp);
526 for (i = 0; i < nb_lf; i++)
527 cpt->lf_msix_off[i] =
528 (cpt->lf_blkaddr[i] == RVU_BLOCK_ADDR_CPT1) ?
529 rsp->cpt1_lf_msixoff[i] :
530 rsp->cptlf_msixoff[i];
532 roc_cpt->nb_lf = nb_lf;
537 cpt_lfs_free(&cpt->dev);
539 cpt_lfs_detach(&cpt->dev);
544 cpt_get_blkaddr(struct dev *dev)
549 /* Reading the discovery register to know which CPT is the LF
550 * attached to. Assume CPT LF's of only one block are attached
554 off = RVU_VF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);
556 off = RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);
558 reg = plt_read64(dev->bar2 + off);
560 return reg & 0x1FFULL ? RVU_BLOCK_ADDR_CPT1 : RVU_BLOCK_ADDR_CPT0;
564 cpt_lf_init(struct roc_cpt_lf *lf)
566 struct dev *dev = lf->dev;
571 if (lf->nb_desc == 0 || lf->nb_desc > CPT_LF_MAX_NB_DESC)
572 lf->nb_desc = CPT_LF_DEFAULT_NB_DESC;
574 /* Update nb_desc to next power of 2 to aid in pending queue checks */
575 lf->nb_desc = plt_align32pow2(lf->nb_desc);
577 /* Allocate memory for instruction queue for CPT LF. */
578 iq_mem = plt_zmalloc(cpt_lf_iq_mem_calc(lf->nb_desc), ROC_ALIGN);
581 plt_atomic_thread_fence(__ATOMIC_ACQ_REL);
583 blkaddr = cpt_get_blkaddr(dev);
584 lf->rbase = dev->bar2 + ((blkaddr << 20) | (lf->lf_id << 12));
585 lf->iq_vaddr = iq_mem;
586 lf->lmt_base = dev->lmt_base;
587 lf->pf_func = dev->pf_func;
589 /* Initialize instruction queue */
592 rc = cpt_lf_register_irqs(lf);
599 roc_cpt_iq_disable(lf);
605 roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf)
607 struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
611 lf->roc_cpt = roc_cpt;
612 lf->msixoff = cpt->lf_msix_off[lf->lf_id];
613 lf->pci_dev = cpt->pci_dev;
615 rc = cpt_lf_init(lf);
619 /* LF init successful */
620 roc_cpt->lf[lf->lf_id] = lf;
625 roc_cpt_dev_init(struct roc_cpt *roc_cpt)
627 struct plt_pci_device *pci_dev;
628 uint16_t nb_lf_avail;
633 if (roc_cpt == NULL || roc_cpt->pci_dev == NULL)
636 PLT_STATIC_ASSERT(sizeof(struct cpt) <= ROC_CPT_MEM_SZ);
638 cpt = roc_cpt_to_cpt_priv(roc_cpt);
639 memset(cpt, 0, sizeof(*cpt));
640 pci_dev = roc_cpt->pci_dev;
643 /* Initialize device */
644 rc = dev_init(dev, pci_dev);
646 plt_err("Failed to init roc device");
650 cpt->pci_dev = pci_dev;
651 roc_cpt->lmt_base = dev->lmt_base;
653 rc = cpt_hardware_caps_get(dev, roc_cpt);
655 plt_err("Could not determine hardware capabilities");
659 rc = cpt_available_lfs_get(&cpt->dev, &nb_lf_avail);
661 plt_err("Could not get available lfs");
665 /* Reserve 1 CPT LF for inline inbound */
666 nb_lf_avail = PLT_MIN(nb_lf_avail, (uint16_t)(ROC_CPT_MAX_LFS - 1));
668 roc_cpt->nb_lf_avail = nb_lf_avail;
670 dev->roc_cpt = roc_cpt;
672 /* Set it to idev if not already present */
673 if (!roc_idev_cpt_get())
674 roc_idev_cpt_set(roc_cpt);
683 roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, void *cptr, bool inval)
685 union cpt_lf_ctx_flush reg;
688 plt_err("Could not trigger CTX flush");
694 reg.s.cptr = (uintptr_t)cptr >> 7;
696 plt_write64(reg.u, lf->rbase + CPT_LF_CTX_FLUSH);
702 roc_cpt_lf_ctx_reload(struct roc_cpt_lf *lf, void *cptr)
704 union cpt_lf_ctx_reload reg;
707 plt_err("Could not trigger CTX reload");
712 reg.s.cptr = (uintptr_t)cptr >> 7;
714 plt_write64(reg.u, lf->rbase + CPT_LF_CTX_RELOAD);
720 cpt_lf_fini(struct roc_cpt_lf *lf)
722 /* Unregister IRQ's */
723 cpt_lf_unregister_irqs(lf);
726 roc_cpt_iq_disable(lf);
729 plt_free(lf->iq_vaddr);
734 roc_cpt_lf_fini(struct roc_cpt_lf *lf)
738 lf->roc_cpt->lf[lf->lf_id] = NULL;
743 roc_cpt_dev_fini(struct roc_cpt *roc_cpt)
745 struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
750 /* Remove idev references */
751 if (roc_idev_cpt_get() == roc_cpt)
752 roc_idev_cpt_set(NULL);
754 roc_cpt->nb_lf_avail = 0;
756 roc_cpt->lmt_base = 0;
758 return dev_fini(&cpt->dev, cpt->pci_dev);
762 roc_cpt_dev_clear(struct roc_cpt *roc_cpt)
764 struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
770 for (i = 0; i < roc_cpt->nb_lf; i++)
771 cpt->lf_msix_off[i] = 0;
775 cpt_lfs_free(&cpt->dev);
777 cpt_lfs_detach(&cpt->dev);
781 roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type)
783 struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
784 struct dev *dev = &cpt->dev;
785 struct cpt_eng_grp_req *req;
786 struct cpt_eng_grp_rsp *rsp;
789 req = mbox_alloc_msg_cpt_eng_grp_get(dev->mbox);
794 case CPT_ENG_TYPE_AE:
795 case CPT_ENG_TYPE_SE:
796 case CPT_ENG_TYPE_IE:
802 req->eng_type = eng_type;
803 ret = mbox_process_msg(dev->mbox, (void *)&rsp);
807 if (rsp->eng_grp_num > 8) {
808 plt_err("Invalid CPT engine group");
812 roc_cpt->eng_grp[eng_type] = rsp->eng_grp_num;
814 return rsp->eng_grp_num;
818 roc_cpt_iq_disable(struct roc_cpt_lf *lf)
820 union cpt_lf_ctl lf_ctl = {.u = 0x0};
821 union cpt_lf_q_grp_ptr grp_ptr;
822 union cpt_lf_inprog lf_inprog;
826 /* Disable instructions enqueuing */
827 plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);
829 /* Wait for instruction queue to become empty */
831 lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);
832 if (!lf_inprog.s.inflight)
837 plt_err("CPT LF %d is still busy", lf->lf_id);
843 /* Disable executions in the LF's queue.
844 * The queue should be empty at this point
846 lf_inprog.s.eena = 0x0;
847 plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);
849 /* Wait for instruction queue to become empty */
852 lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);
853 if (lf_inprog.s.grb_partial)
857 grp_ptr.u = plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR);
858 } while ((cnt < 10) && (grp_ptr.s.nq_ptr != grp_ptr.s.dq_ptr));
862 lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);
863 if ((lf_inprog.s.inflight == 0) && (lf_inprog.s.gwb_cnt < 40) &&
864 ((lf_inprog.s.grb_cnt == 0) || (lf_inprog.s.grb_cnt == 40)))
872 roc_cpt_iq_enable(struct roc_cpt_lf *lf)
874 union cpt_lf_inprog lf_inprog;
875 union cpt_lf_ctl lf_ctl;
877 /* Disable command queue */
878 roc_cpt_iq_disable(lf);
880 /* Enable instruction queue enqueuing */
881 lf_ctl.u = plt_read64(lf->rbase + CPT_LF_CTL);
884 lf_ctl.s.fc_up_crossing = 0;
885 lf_ctl.s.fc_hyst_bits = lf->fc_hyst_bits;
886 plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);
888 /* Enable command queue execution */
889 lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);
890 lf_inprog.s.eena = 1;
891 plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);
897 roc_cpt_lmtline_init(struct roc_cpt *roc_cpt, struct roc_cpt_lmtline *lmtline,
900 struct roc_cpt_lf *lf;
902 lf = roc_cpt->lf[lf_id];
906 lmtline->io_addr = lf->io_addr;
907 if (roc_model_is_cn10k())
908 lmtline->io_addr |= ROC_CN10K_CPT_INST_DW_M1 << 4;
910 lmtline->fc_addr = lf->fc_addr;
911 lmtline->lmt_base = lf->lmt_base;
917 roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr,
920 uintptr_t lmt_base = lf->lmt_base;
921 uint64_t lmt_arg, io_addr;
922 struct cpt_inst_s *inst;
923 union cpt_res_s *res;
928 ROC_LMT_CPT_BASE_ID_GET(lmt_base, lmt_id);
929 inst = (struct cpt_inst_s *)lmt_base;
931 memset(inst, 0, sizeof(struct cpt_inst_s));
933 res = plt_zmalloc(sizeof(*res), ROC_CPT_RES_ALIGN);
935 plt_err("Couldn't allocate memory for result address");
939 dptr = plt_zmalloc(sa_len, 8);
941 plt_err("Couldn't allocate memory for SA dptr");
946 for (i = 0; i < (sa_len / 8); i++)
947 dptr[i] = plt_cpu_to_be_64(((uint64_t *)sa_dptr)[i]);
949 /* Fill CPT_INST_S for WRITE_SA microcode op */
950 res->cn10k.compcode = CPT_COMP_NOT_DONE;
951 inst->res_addr = (uint64_t)res;
952 inst->dptr = (uint64_t)dptr;
953 inst->w4.s.param2 = sa_len >> 3;
954 inst->w4.s.dlen = sa_len;
955 inst->w4.s.opcode_major = ROC_IE_OT_MAJOR_OP_WRITE_SA;
956 inst->w4.s.opcode_minor = ROC_IE_OT_MINOR_OP_WRITE_SA;
957 inst->w7.s.cptr = (uint64_t)sa_cptr;
958 inst->w7.s.ctx_val = 1;
959 inst->w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE_IE;
961 lmt_arg = ROC_CN10K_CPT_LMT_ARG | (uint64_t)lmt_id;
962 io_addr = lf->io_addr | ROC_CN10K_CPT_INST_DW_M1 << 4;
964 roc_lmt_submit_steorl(lmt_arg, io_addr);
967 /* Wait until CPT instruction completes */
968 while (res->cn10k.compcode == CPT_COMP_NOT_DONE)