1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
14 /* PCI Extended capability ID */
15 #define ROC_PCI_EXT_CAP_ID_SRIOV 0x10 /* SRIOV cap */
17 /* Single Root I/O Virtualization */
18 #define ROC_PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
21 mbox_mem_map(off_t off, size_t size)
23 void *va = MAP_FAILED;
26 if (size <= 0 || !off) {
27 plt_err("Invalid mbox area off 0x%lx size %lu", off, size);
31 mem_fd = open("/dev/mem", O_RDWR);
35 va = plt_mmap(NULL, size, PLT_PROT_READ | PLT_PROT_WRITE,
36 PLT_MAP_SHARED, mem_fd, off);
40 plt_err("Failed to mmap sz=0x%zx, fd=%d, off=%jd", size, mem_fd,
47 mbox_mem_unmap(void *va, size_t size)
54 pf_af_sync_msg(struct dev *dev, struct mbox_msghdr **rsp)
56 uint32_t timeout = 0, sleep = 1;
57 struct mbox *mbox = dev->mbox;
58 struct mbox_dev *mdev = &mbox->dev[0];
60 volatile uint64_t int_status = 0;
61 struct mbox_msghdr *msghdr;
65 /* We need to disable PF interrupts. We are in timer interrupt */
66 plt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
69 mbox_msg_send(mbox, 0);
74 if (timeout >= mbox->rsp_tmo) {
75 plt_err("Message timeout: %dms", mbox->rsp_tmo);
79 int_status = plt_read64(dev->bar2 + RVU_PF_INT);
80 } while ((int_status & 0x1) != 0x1);
83 plt_write64(int_status, dev->bar2 + RVU_PF_INT);
85 /* Enable interrupts */
86 plt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
90 off = mbox->rx_start +
91 PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
92 msghdr = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + off);
102 af_pf_wait_msg(struct dev *dev, uint16_t vf, int num_msg)
104 uint32_t timeout = 0, sleep = 1;
105 struct mbox *mbox = dev->mbox;
106 struct mbox_dev *mdev = &mbox->dev[0];
107 volatile uint64_t int_status;
108 struct mbox_hdr *req_hdr;
109 struct mbox_msghdr *msg;
110 struct mbox_msghdr *rsp;
115 /* We need to disable PF interrupts. We are in timer interrupt */
116 plt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
119 mbox_msg_send(mbox, 0);
124 if (timeout >= mbox->rsp_tmo) {
125 plt_err("Routed messages %d timeout: %dms", num_msg,
129 int_status = plt_read64(dev->bar2 + RVU_PF_INT);
130 } while ((int_status & 0x1) != 0x1);
133 plt_write64(~0ull, dev->bar2 + RVU_PF_INT);
135 /* Enable interrupts */
136 plt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
138 plt_spinlock_lock(&mdev->mbox_lock);
140 req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
141 if (req_hdr->num_msgs != num_msg)
142 plt_err("Routed messages: %d received: %d", num_msg,
145 /* Get messages from mbox */
146 offset = mbox->rx_start +
147 PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
148 for (i = 0; i < req_hdr->num_msgs; i++) {
149 msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
150 size = mbox->rx_start + msg->next_msgoff - offset;
152 /* Reserve PF/VF mbox message */
153 size = PLT_ALIGN(size, MBOX_MSG_ALIGN);
154 rsp = mbox_alloc_msg(&dev->mbox_vfpf, vf, size);
156 plt_err("Failed to reserve VF%d message", vf);
160 mbox_rsp_init(msg->id, rsp);
162 /* Copy message from AF<->PF mbox to PF<->VF mbox */
163 mbox_memcpy((uint8_t *)rsp + sizeof(struct mbox_msghdr),
164 (uint8_t *)msg + sizeof(struct mbox_msghdr),
165 size - sizeof(struct mbox_msghdr));
167 /* Set status and sender pf_func data */
169 rsp->pcifunc = msg->pcifunc;
171 /* Whenever a PF comes up, AF sends the link status to it but
172 * when VF comes up no such event is sent to respective VF.
173 * Using MBOX_MSG_NIX_LF_START_RX response from AF for the
174 * purpose and send the link status of PF to VF.
176 if (msg->id == MBOX_MSG_NIX_LF_START_RX) {
177 /* Send link status to VF */
178 struct cgx_link_user_info linfo;
179 struct mbox_msghdr *vf_msg;
182 /* Get the link status */
183 memset(&linfo, 0, sizeof(struct cgx_link_user_info));
184 if (dev->ops && dev->ops->link_status_get)
185 dev->ops->link_status_get(dev->roc_nix, &linfo);
187 sz = PLT_ALIGN(mbox_id2size(MBOX_MSG_CGX_LINK_EVENT),
189 /* Prepare the message to be sent */
190 vf_msg = mbox_alloc_msg(&dev->mbox_vfpf_up, vf, sz);
192 mbox_req_init(MBOX_MSG_CGX_LINK_EVENT, vf_msg);
193 memcpy((uint8_t *)vf_msg +
194 sizeof(struct mbox_msghdr), &linfo,
195 sizeof(struct cgx_link_user_info));
197 vf_msg->rc = msg->rc;
198 vf_msg->pcifunc = msg->pcifunc;
200 mbox_msg_send(&dev->mbox_vfpf_up, vf);
204 offset = mbox->rx_start + msg->next_msgoff;
206 plt_spinlock_unlock(&mdev->mbox_lock);
208 return req_hdr->num_msgs;
212 vf_pf_process_msgs(struct dev *dev, uint16_t vf)
214 struct mbox *mbox = &dev->mbox_vfpf;
215 struct mbox_dev *mdev = &mbox->dev[vf];
216 struct mbox_hdr *req_hdr;
217 struct mbox_msghdr *msg;
218 int offset, routed = 0;
222 req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
223 if (!req_hdr->num_msgs)
226 offset = mbox->rx_start + PLT_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
228 for (i = 0; i < req_hdr->num_msgs; i++) {
229 msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
230 size = mbox->rx_start + msg->next_msgoff - offset;
233 msg->pcifunc = dev_pf_func(dev->pf, vf);
235 if (msg->id == MBOX_MSG_READY) {
236 struct ready_msg_rsp *rsp;
237 uint16_t max_bits = sizeof(dev->active_vfs[0]) * 8;
239 /* Handle READY message in PF */
240 dev->active_vfs[vf / max_bits] |=
241 BIT_ULL(vf % max_bits);
242 rsp = (struct ready_msg_rsp *)mbox_alloc_msg(
243 mbox, vf, sizeof(*rsp));
245 plt_err("Failed to alloc VF%d READY message",
250 mbox_rsp_init(msg->id, rsp);
252 /* PF/VF function ID */
253 rsp->hdr.pcifunc = msg->pcifunc;
256 struct mbox_msghdr *af_req;
257 /* Reserve AF/PF mbox message */
258 size = PLT_ALIGN(size, MBOX_MSG_ALIGN);
259 af_req = mbox_alloc_msg(dev->mbox, 0, size);
262 mbox_req_init(msg->id, af_req);
264 /* Copy message from VF<->PF mbox to PF<->AF mbox */
265 mbox_memcpy((uint8_t *)af_req +
266 sizeof(struct mbox_msghdr),
267 (uint8_t *)msg + sizeof(struct mbox_msghdr),
268 size - sizeof(struct mbox_msghdr));
269 af_req->pcifunc = msg->pcifunc;
272 offset = mbox->rx_start + msg->next_msgoff;
276 plt_base_dbg("pf:%d routed %d messages from vf:%d to AF",
277 dev->pf, routed, vf);
278 af_pf_wait_msg(dev, vf, routed);
279 mbox_reset(dev->mbox, 0);
282 /* Send mbox responses to VF */
283 if (mdev->num_msgs) {
284 plt_base_dbg("pf:%d reply %d messages to vf:%d", dev->pf,
286 mbox_msg_send(mbox, vf);
293 vf_pf_process_up_msgs(struct dev *dev, uint16_t vf)
295 struct mbox *mbox = &dev->mbox_vfpf_up;
296 struct mbox_dev *mdev = &mbox->dev[vf];
297 struct mbox_hdr *req_hdr;
298 struct mbox_msghdr *msg;
303 req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
304 if (req_hdr->num_msgs == 0)
307 offset = mbox->rx_start + PLT_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
309 for (i = 0; i < req_hdr->num_msgs; i++) {
310 msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
314 msg->pcifunc = dev_pf_func(dev->pf, vf);
317 case MBOX_MSG_CGX_LINK_EVENT:
318 plt_base_dbg("PF: Msg 0x%x (%s) fn:0x%x (pf:%d,vf:%d)",
319 msg->id, mbox_id2name(msg->id),
320 msg->pcifunc, dev_get_pf(msg->pcifunc),
321 dev_get_vf(msg->pcifunc));
323 case MBOX_MSG_CGX_PTP_RX_INFO:
324 plt_base_dbg("PF: Msg 0x%x (%s) fn:0x%x (pf:%d,vf:%d)",
325 msg->id, mbox_id2name(msg->id),
326 msg->pcifunc, dev_get_pf(msg->pcifunc),
327 dev_get_vf(msg->pcifunc));
330 plt_err("Not handled UP msg 0x%x (%s) func:0x%x",
331 msg->id, mbox_id2name(msg->id), msg->pcifunc);
333 offset = mbox->rx_start + msg->next_msgoff;
335 mbox_reset(mbox, vf);
336 mdev->msgs_acked = msgs_acked;
343 roc_vf_pf_mbox_handle_msg(void *param)
345 uint16_t vf, max_vf, max_bits;
346 struct dev *dev = param;
348 max_bits = sizeof(dev->intr.bits[0]) * sizeof(uint64_t);
349 max_vf = max_bits * MAX_VFPF_DWORD_BITS;
351 for (vf = 0; vf < max_vf; vf++) {
352 if (dev->intr.bits[vf / max_bits] & BIT_ULL(vf % max_bits)) {
353 plt_base_dbg("Process vf:%d request (pf:%d, vf:%d)", vf,
355 vf_pf_process_msgs(dev, vf);
357 vf_pf_process_up_msgs(dev, vf);
358 dev->intr.bits[vf / max_bits] &=
359 ~(BIT_ULL(vf % max_bits));
366 roc_vf_pf_mbox_irq(void *param)
368 struct dev *dev = param;
369 bool alarm_set = false;
373 for (vfpf = 0; vfpf < MAX_VFPF_DWORD_BITS; ++vfpf) {
374 intr = plt_read64(dev->bar2 + RVU_PF_VFPF_MBOX_INTX(vfpf));
378 plt_base_dbg("vfpf: %d intr: 0x%" PRIx64 " (pf:%d, vf:%d)",
379 vfpf, intr, dev->pf, dev->vf);
381 /* Save and clear intr bits */
382 dev->intr.bits[vfpf] |= intr;
383 plt_write64(intr, dev->bar2 + RVU_PF_VFPF_MBOX_INTX(vfpf));
387 if (!dev->timer_set && alarm_set) {
389 /* Start timer to handle messages */
390 plt_alarm_set(VF_PF_MBOX_TIMER_MS, roc_vf_pf_mbox_handle_msg,
396 process_msgs(struct dev *dev, struct mbox *mbox)
398 struct mbox_dev *mdev = &mbox->dev[0];
399 struct mbox_hdr *req_hdr;
400 struct mbox_msghdr *msg;
405 req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
406 if (req_hdr->num_msgs == 0)
409 offset = mbox->rx_start + PLT_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
410 for (i = 0; i < req_hdr->num_msgs; i++) {
411 msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
414 plt_base_dbg("Message 0x%x (%s) pf:%d/vf:%d", msg->id,
415 mbox_id2name(msg->id), dev_get_pf(msg->pcifunc),
416 dev_get_vf(msg->pcifunc));
419 /* Add message id's that are handled here */
421 /* Get our identity */
422 dev->pf_func = msg->pcifunc;
427 plt_err("Message (%s) response has err=%d",
428 mbox_id2name(msg->id), msg->rc);
431 offset = mbox->rx_start + msg->next_msgoff;
435 /* Update acked if someone is waiting a message */
436 mdev->msgs_acked = msgs_acked;
440 /* Copies the message received from AF and sends it to VF */
442 pf_vf_mbox_send_up_msg(struct dev *dev, void *rec_msg)
444 uint16_t max_bits = sizeof(dev->active_vfs[0]) * sizeof(uint64_t);
445 struct mbox *vf_mbox = &dev->mbox_vfpf_up;
446 struct msg_req *msg = rec_msg;
447 struct mbox_msghdr *vf_msg;
451 size = PLT_ALIGN(mbox_id2size(msg->hdr.id), MBOX_MSG_ALIGN);
452 /* Send UP message to all VF's */
453 for (vf = 0; vf < vf_mbox->ndevs; vf++) {
455 if (!(dev->active_vfs[vf / max_bits] & (BIT_ULL(vf))))
458 plt_base_dbg("(%s) size: %zx to VF: %d",
459 mbox_id2name(msg->hdr.id), size, vf);
461 /* Reserve PF/VF mbox message */
462 vf_msg = mbox_alloc_msg(vf_mbox, vf, size);
464 plt_err("Failed to alloc VF%d UP message", vf);
467 mbox_req_init(msg->hdr.id, vf_msg);
470 * Copy message from AF<->PF UP mbox
473 mbox_memcpy((uint8_t *)vf_msg + sizeof(struct mbox_msghdr),
474 (uint8_t *)msg + sizeof(struct mbox_msghdr),
475 size - sizeof(struct mbox_msghdr));
477 vf_msg->rc = msg->hdr.rc;
478 /* Set PF to be a sender */
479 vf_msg->pcifunc = dev->pf_func;
482 mbox_msg_send(vf_mbox, vf);
487 mbox_up_handler_cgx_link_event(struct dev *dev, struct cgx_link_info_msg *msg,
490 struct cgx_link_user_info *linfo = &msg->link_info;
491 void *roc_nix = dev->roc_nix;
493 plt_base_dbg("pf:%d/vf:%d NIC Link %s --> 0x%x (%s) from: pf:%d/vf:%d",
494 dev_get_pf(dev->pf_func), dev_get_vf(dev->pf_func),
495 linfo->link_up ? "UP" : "DOWN", msg->hdr.id,
496 mbox_id2name(msg->hdr.id), dev_get_pf(msg->hdr.pcifunc),
497 dev_get_vf(msg->hdr.pcifunc));
499 /* PF gets link notification from AF */
500 if (dev_get_pf(msg->hdr.pcifunc) == 0) {
501 if (dev->ops && dev->ops->link_status_update)
502 dev->ops->link_status_update(roc_nix, linfo);
504 /* Forward the same message as received from AF to VF */
505 pf_vf_mbox_send_up_msg(dev, msg);
507 /* VF gets link up notification */
508 if (dev->ops && dev->ops->link_status_update)
509 dev->ops->link_status_update(roc_nix, linfo);
517 mbox_up_handler_cgx_ptp_rx_info(struct dev *dev,
518 struct cgx_ptp_rx_info_msg *msg,
521 void *roc_nix = dev->roc_nix;
523 plt_base_dbg("pf:%d/vf:%d PTP mode %s --> 0x%x (%s) from: pf:%d/vf:%d",
524 dev_get_pf(dev->pf_func), dev_get_vf(dev->pf_func),
525 msg->ptp_en ? "ENABLED" : "DISABLED", msg->hdr.id,
526 mbox_id2name(msg->hdr.id), dev_get_pf(msg->hdr.pcifunc),
527 dev_get_vf(msg->hdr.pcifunc));
529 /* PF gets PTP notification from AF */
530 if (dev_get_pf(msg->hdr.pcifunc) == 0) {
531 if (dev->ops && dev->ops->ptp_info_update)
532 dev->ops->ptp_info_update(roc_nix, msg->ptp_en);
534 /* Forward the same message as received from AF to VF */
535 pf_vf_mbox_send_up_msg(dev, msg);
537 /* VF gets PTP notification */
538 if (dev->ops && dev->ops->ptp_info_update)
539 dev->ops->ptp_info_update(roc_nix, msg->ptp_en);
547 mbox_process_msgs_up(struct dev *dev, struct mbox_msghdr *req)
549 /* Check if valid, if not reply with a invalid msg */
550 if (req->sig != MBOX_REQ_SIG)
555 reply_invalid_msg(&dev->mbox_up, 0, 0, req->id);
557 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
559 struct _rsp_type *rsp; \
561 rsp = (struct _rsp_type *)mbox_alloc_msg( \
562 &dev->mbox_up, 0, sizeof(struct _rsp_type)); \
566 rsp->hdr.sig = MBOX_RSP_SIG; \
567 rsp->hdr.pcifunc = dev->pf_func; \
569 err = mbox_up_handler_##_fn_name(dev, (struct _req_type *)req, \
581 process_msgs_up(struct dev *dev, struct mbox *mbox)
583 struct mbox_dev *mdev = &mbox->dev[0];
584 struct mbox_hdr *req_hdr;
585 struct mbox_msghdr *msg;
588 req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
589 if (req_hdr->num_msgs == 0)
592 offset = mbox->rx_start + PLT_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
593 for (i = 0; i < req_hdr->num_msgs; i++) {
594 msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
596 plt_base_dbg("Message 0x%x (%s) pf:%d/vf:%d", msg->id,
597 mbox_id2name(msg->id), dev_get_pf(msg->pcifunc),
598 dev_get_vf(msg->pcifunc));
599 err = mbox_process_msgs_up(dev, msg);
601 plt_err("Error %d handling 0x%x (%s)", err, msg->id,
602 mbox_id2name(msg->id));
603 offset = mbox->rx_start + msg->next_msgoff;
605 /* Send mbox responses */
606 if (mdev->num_msgs) {
607 plt_base_dbg("Reply num_msgs:%d", mdev->num_msgs);
608 mbox_msg_send(mbox, 0);
613 roc_pf_vf_mbox_irq(void *param)
615 struct dev *dev = param;
618 intr = plt_read64(dev->bar2 + RVU_VF_INT);
620 plt_base_dbg("Proceeding to check mbox UP messages if any");
622 plt_write64(intr, dev->bar2 + RVU_VF_INT);
623 plt_base_dbg("Irq 0x%" PRIx64 "(pf:%d,vf:%d)", intr, dev->pf, dev->vf);
625 /* First process all configuration messages */
626 process_msgs(dev, dev->mbox);
628 /* Process Uplink messages */
629 process_msgs_up(dev, &dev->mbox_up);
633 roc_af_pf_mbox_irq(void *param)
635 struct dev *dev = param;
638 intr = plt_read64(dev->bar2 + RVU_PF_INT);
640 plt_base_dbg("Proceeding to check mbox UP messages if any");
642 plt_write64(intr, dev->bar2 + RVU_PF_INT);
643 plt_base_dbg("Irq 0x%" PRIx64 "(pf:%d,vf:%d)", intr, dev->pf, dev->vf);
645 /* First process all configuration messages */
646 process_msgs(dev, dev->mbox);
648 /* Process Uplink messages */
649 process_msgs_up(dev, &dev->mbox_up);
653 mbox_register_pf_irq(struct plt_pci_device *pci_dev, struct dev *dev)
655 struct plt_intr_handle *intr_handle = pci_dev->intr_handle;
659 for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)
661 dev->bar2 + RVU_PF_VFPF_MBOX_INT_ENA_W1CX(i));
663 plt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
667 /* MBOX interrupt for VF(0...63) <-> PF */
668 rc = dev_irq_register(intr_handle, roc_vf_pf_mbox_irq, dev,
669 RVU_PF_INT_VEC_VFPF_MBOX0);
672 plt_err("Fail to register PF(VF0-63) mbox irq");
675 /* MBOX interrupt for VF(64...128) <-> PF */
676 rc = dev_irq_register(intr_handle, roc_vf_pf_mbox_irq, dev,
677 RVU_PF_INT_VEC_VFPF_MBOX1);
680 plt_err("Fail to register PF(VF64-128) mbox irq");
683 /* MBOX interrupt AF <-> PF */
684 rc = dev_irq_register(intr_handle, roc_af_pf_mbox_irq, dev,
685 RVU_PF_INT_VEC_AFPF_MBOX);
687 plt_err("Fail to register AF<->PF mbox irq");
692 for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)
694 dev->bar2 + RVU_PF_VFPF_MBOX_INT_ENA_W1SX(i));
696 plt_write64(~0ull, dev->bar2 + RVU_PF_INT);
697 plt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
703 mbox_register_vf_irq(struct plt_pci_device *pci_dev, struct dev *dev)
705 struct plt_intr_handle *intr_handle = pci_dev->intr_handle;
709 plt_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1C);
711 /* MBOX interrupt PF <-> VF */
712 rc = dev_irq_register(intr_handle, roc_pf_vf_mbox_irq, dev,
713 RVU_VF_INT_VEC_MBOX);
715 plt_err("Fail to register PF<->VF mbox irq");
720 plt_write64(~0ull, dev->bar2 + RVU_VF_INT);
721 plt_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1S);
727 mbox_register_irq(struct plt_pci_device *pci_dev, struct dev *dev)
730 return mbox_register_vf_irq(pci_dev, dev);
732 return mbox_register_pf_irq(pci_dev, dev);
736 mbox_unregister_pf_irq(struct plt_pci_device *pci_dev, struct dev *dev)
738 struct plt_intr_handle *intr_handle = pci_dev->intr_handle;
742 for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)
744 dev->bar2 + RVU_PF_VFPF_MBOX_INT_ENA_W1CX(i));
746 plt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
750 plt_alarm_cancel(roc_vf_pf_mbox_handle_msg, dev);
752 /* Unregister the interrupt handler for each vectors */
753 /* MBOX interrupt for VF(0...63) <-> PF */
754 dev_irq_unregister(intr_handle, roc_vf_pf_mbox_irq, dev,
755 RVU_PF_INT_VEC_VFPF_MBOX0);
757 /* MBOX interrupt for VF(64...128) <-> PF */
758 dev_irq_unregister(intr_handle, roc_vf_pf_mbox_irq, dev,
759 RVU_PF_INT_VEC_VFPF_MBOX1);
761 /* MBOX interrupt AF <-> PF */
762 dev_irq_unregister(intr_handle, roc_af_pf_mbox_irq, dev,
763 RVU_PF_INT_VEC_AFPF_MBOX);
767 mbox_unregister_vf_irq(struct plt_pci_device *pci_dev, struct dev *dev)
769 struct plt_intr_handle *intr_handle = pci_dev->intr_handle;
772 plt_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1C);
774 /* Unregister the interrupt handler */
775 dev_irq_unregister(intr_handle, roc_pf_vf_mbox_irq, dev,
776 RVU_VF_INT_VEC_MBOX);
780 mbox_unregister_irq(struct plt_pci_device *pci_dev, struct dev *dev)
783 mbox_unregister_vf_irq(pci_dev, dev);
785 mbox_unregister_pf_irq(pci_dev, dev);
789 vf_flr_send_msg(struct dev *dev, uint16_t vf)
791 struct mbox *mbox = dev->mbox;
795 req = mbox_alloc_msg_vf_flr(mbox);
798 /* Overwrite pcifunc to indicate VF */
799 req->hdr.pcifunc = dev_pf_func(dev->pf, vf);
801 /* Sync message in interrupt context */
802 rc = pf_af_sync_msg(dev, NULL);
804 plt_err("Failed to send VF FLR mbox msg, rc=%d", rc);
810 roc_pf_vf_flr_irq(void *param)
812 struct dev *dev = (struct dev *)param;
813 uint16_t max_vf = 64, vf;
818 max_vf = (dev->maxvf > 0) ? dev->maxvf : 64;
821 plt_base_dbg("FLR VF interrupt: max_vf: %d", max_vf);
823 for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i) {
824 intr = plt_read64(bar2 + RVU_PF_VFFLR_INTX(i));
828 for (vf = 0; vf < max_vf; vf++) {
829 if (!(intr & (1ULL << vf)))
832 plt_base_dbg("FLR: i :%d intr: 0x%" PRIx64 ", vf-%d", i,
833 intr, (64 * i + vf));
834 /* Clear interrupt */
835 plt_write64(BIT_ULL(vf), bar2 + RVU_PF_VFFLR_INTX(i));
836 /* Disable the interrupt */
837 plt_write64(BIT_ULL(vf),
838 bar2 + RVU_PF_VFFLR_INT_ENA_W1CX(i));
839 /* Inform AF about VF reset */
840 vf_flr_send_msg(dev, vf);
842 /* Signal FLR finish */
843 plt_write64(BIT_ULL(vf), bar2 + RVU_PF_VFTRPENDX(i));
844 /* Enable interrupt */
845 plt_write64(~0ull, bar2 + RVU_PF_VFFLR_INT_ENA_W1SX(i));
851 vf_flr_unregister_irqs(struct plt_pci_device *pci_dev, struct dev *dev)
853 struct plt_intr_handle *intr_handle = pci_dev->intr_handle;
856 plt_base_dbg("Unregister VF FLR interrupts for %s", pci_dev->name);
859 for (i = 0; i < MAX_VFPF_DWORD_BITS; i++)
860 plt_write64(~0ull, dev->bar2 + RVU_PF_VFFLR_INT_ENA_W1CX(i));
862 dev_irq_unregister(intr_handle, roc_pf_vf_flr_irq, dev,
863 RVU_PF_INT_VEC_VFFLR0);
865 dev_irq_unregister(intr_handle, roc_pf_vf_flr_irq, dev,
866 RVU_PF_INT_VEC_VFFLR1);
872 vf_flr_register_irqs(struct plt_pci_device *pci_dev, struct dev *dev)
874 struct plt_intr_handle *handle = pci_dev->intr_handle;
877 plt_base_dbg("Register VF FLR interrupts for %s", pci_dev->name);
879 rc = dev_irq_register(handle, roc_pf_vf_flr_irq, dev,
880 RVU_PF_INT_VEC_VFFLR0);
882 plt_err("Failed to init RVU_PF_INT_VEC_VFFLR0 rc=%d", rc);
884 rc = dev_irq_register(handle, roc_pf_vf_flr_irq, dev,
885 RVU_PF_INT_VEC_VFFLR1);
887 plt_err("Failed to init RVU_PF_INT_VEC_VFFLR1 rc=%d", rc);
889 /* Enable HW interrupt */
890 for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i) {
891 plt_write64(~0ull, dev->bar2 + RVU_PF_VFFLR_INTX(i));
892 plt_write64(~0ull, dev->bar2 + RVU_PF_VFTRPENDX(i));
893 plt_write64(~0ull, dev->bar2 + RVU_PF_VFFLR_INT_ENA_W1SX(i));
899 clear_rvum_interrupts(struct dev *dev)
904 if (dev_is_vf(dev)) {
905 /* Clear VF mbox interrupt */
906 intr = plt_read64(dev->bar2 + RVU_VF_INT);
908 plt_write64(intr, dev->bar2 + RVU_VF_INT);
910 /* Clear AF PF interrupt line */
911 intr = plt_read64(dev->bar2 + RVU_PF_INT);
913 plt_write64(intr, dev->bar2 + RVU_PF_INT);
914 for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i) {
915 /* Clear MBOX interrupts */
916 intr = plt_read64(dev->bar2 + RVU_PF_VFPF_MBOX_INTX(i));
920 RVU_PF_VFPF_MBOX_INTX(i));
921 /* Clear VF FLR interrupts */
922 intr = plt_read64(dev->bar2 + RVU_PF_VFFLR_INTX(i));
925 dev->bar2 + RVU_PF_VFFLR_INTX(i));
931 dev_active_vfs(struct dev *dev)
935 for (i = 0; i < MAX_VFPF_DWORD_BITS; i++)
936 count += __builtin_popcount(dev->active_vfs[i]);
942 dev_vf_hwcap_update(struct plt_pci_device *pci_dev, struct dev *dev)
944 switch (pci_dev->id.device_id) {
945 case PCI_DEVID_CNXK_RVU_PF:
947 case PCI_DEVID_CNXK_RVU_SSO_TIM_VF:
948 case PCI_DEVID_CNXK_RVU_NPA_VF:
949 case PCI_DEVID_CN10K_RVU_CPT_VF:
950 case PCI_DEVID_CN9K_RVU_CPT_VF:
951 case PCI_DEVID_CNXK_RVU_AF_VF:
952 case PCI_DEVID_CNXK_RVU_VF:
953 case PCI_DEVID_CNXK_RVU_SDP_VF:
954 dev->hwcap |= DEV_HWCAP_F_VF;
960 dev_vf_mbase_get(struct plt_pci_device *pci_dev, struct dev *dev)
962 void *vf_mbase = NULL;
968 /* For CN10K onwards, it is just after PF MBOX */
969 if (!roc_model_is_cn9k())
970 return dev->bar4 + MBOX_SIZE;
972 pa = plt_read64(dev->bar2 + RVU_PF_VF_BAR4_ADDR);
974 plt_err("Invalid VF mbox base pa");
978 vf_mbase = mbox_mem_map(pa, MBOX_SIZE * pci_dev->max_vfs);
979 if (vf_mbase == MAP_FAILED) {
980 plt_err("Failed to mmap vf mbase at pa 0x%lx, rc=%d", pa,
984 return (uintptr_t)vf_mbase;
988 dev_vf_mbase_put(struct plt_pci_device *pci_dev, uintptr_t vf_mbase)
990 if (!vf_mbase || !pci_dev->max_vfs || !roc_model_is_cn9k())
993 mbox_mem_unmap((void *)vf_mbase, MBOX_SIZE * pci_dev->max_vfs);
997 dev_setup_shared_lmt_region(struct mbox *mbox, bool valid_iova, uint64_t iova)
999 struct lmtst_tbl_setup_req *req;
1001 req = mbox_alloc_msg_lmtst_tbl_setup(mbox);
1005 /* This pcifunc is defined with primary pcifunc whose LMT address
1006 * will be shared. If call contains valid IOVA, following pcifunc
1007 * field is of no use.
1009 req->pcifunc = valid_iova ? 0 : idev_lmt_pffunc_get();
1010 req->use_local_lmt_region = valid_iova;
1011 req->lmt_iova = iova;
1013 return mbox_process(mbox);
1016 /* Total no of lines * size of each lmtline */
1017 #define LMT_REGION_SIZE (ROC_NUM_LMT_LINES * ROC_LMT_LINE_SZ)
1019 dev_lmt_setup(struct dev *dev)
1021 char name[PLT_MEMZONE_NAMESIZE];
1022 const struct plt_memzone *mz;
1023 struct idev_cfg *idev;
1026 if (roc_model_is_cn9k()) {
1027 dev->lmt_base = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
1033 /* Set common lmt region from second pf_func onwards. */
1034 if (!dev->disable_shared_lmt && idev_lmt_pffunc_get() &&
1035 dev->pf_func != idev_lmt_pffunc_get()) {
1036 rc = dev_setup_shared_lmt_region(dev->mbox, false, 0);
1038 /* On success, updating lmt base of secondary pf_funcs
1039 * with primary pf_func's lmt base.
1041 dev->lmt_base = roc_idev_lmt_base_addr_get();
1044 plt_err("Failed to setup shared lmt region, pf_func %d err %d "
1045 "Using respective LMT region per pf func",
1049 /* Allocating memory for LMT region */
1050 sprintf(name, "LMT_MAP%x", dev->pf_func);
1052 /* Setting alignment to ensure correct masking for resetting to lmt base
1053 * of a core after all lmt lines under that core are used.
1054 * Alignment value LMT_REGION_SIZE to handle the case where all lines
1055 * are used by 1 core.
1057 mz = plt_lmt_region_reserve_aligned(name, LMT_REGION_SIZE,
1060 plt_err("Memory alloc failed: %s", strerror(errno));
1064 /* Share the IOVA address with Kernel */
1065 rc = dev_setup_shared_lmt_region(dev->mbox, true, mz->iova);
1071 dev->lmt_base = mz->iova;
1073 /* Base LMT address should be chosen from only those pci funcs which
1074 * participate in LMT shared mode.
1076 if (!dev->disable_shared_lmt) {
1077 idev = idev_get_cfg();
1083 if (!__atomic_load_n(&idev->lmt_pf_func, __ATOMIC_ACQUIRE)) {
1084 idev->lmt_base_addr = dev->lmt_base;
1085 idev->lmt_pf_func = dev->pf_func;
1086 idev->num_lmtlines = RVU_LMT_LINE_MAX;
1092 plt_memzone_free(mz);
1098 dev_init(struct dev *dev, struct plt_pci_device *pci_dev)
1100 int direction, up_direction, rc;
1101 uintptr_t bar2, bar4, mbox;
1102 uintptr_t vf_mbase = 0;
1103 uint64_t intr_offset;
1105 bar2 = (uintptr_t)pci_dev->mem_resource[2].addr;
1106 bar4 = (uintptr_t)pci_dev->mem_resource[4].addr;
1107 if (bar2 == 0 || bar4 == 0) {
1108 plt_err("Failed to get PCI bars");
1113 /* Trigger fault on bar2 and bar4 regions
1114 * to avoid BUG_ON in remap_pfn_range()
1117 *(volatile uint64_t *)bar2;
1118 *(volatile uint64_t *)bar4;
1120 /* Check ROC model supported */
1121 if (roc_model->flag == 0) {
1122 rc = UTIL_ERR_INVALID_MODEL;
1126 dev->maxvf = pci_dev->max_vfs;
1129 dev_vf_hwcap_update(pci_dev, dev);
1131 if (dev_is_vf(dev)) {
1132 mbox = (roc_model_is_cn9k() ?
1133 bar4 : (bar2 + RVU_VF_MBOX_REGION));
1134 direction = MBOX_DIR_VFPF;
1135 up_direction = MBOX_DIR_VFPF_UP;
1136 intr_offset = RVU_VF_INT;
1139 direction = MBOX_DIR_PFAF;
1140 up_direction = MBOX_DIR_PFAF_UP;
1141 intr_offset = RVU_PF_INT;
1144 /* Clear all RVUM interrupts */
1145 clear_rvum_interrupts(dev);
1147 /* Initialize the local mbox */
1148 rc = mbox_init(&dev->mbox_local, mbox, bar2, direction, 1, intr_offset);
1151 dev->mbox = &dev->mbox_local;
1153 rc = mbox_init(&dev->mbox_up, mbox, bar2, up_direction, 1, intr_offset);
1157 /* Register mbox interrupts */
1158 rc = mbox_register_irq(pci_dev, dev);
1162 /* Check the readiness of PF/VF */
1163 rc = send_ready_msg(dev->mbox, &dev->pf_func);
1165 goto mbox_unregister;
1167 dev->pf = dev_get_pf(dev->pf_func);
1168 dev->vf = dev_get_vf(dev->pf_func);
1169 memset(&dev->active_vfs, 0, sizeof(dev->active_vfs));
1171 /* Allocate memory for device ops */
1172 dev->ops = plt_zmalloc(sizeof(struct dev_ops), 0);
1173 if (dev->ops == NULL) {
1175 goto mbox_unregister;
1178 /* Found VF devices in a PF device */
1179 if (pci_dev->max_vfs > 0) {
1180 /* Remap mbox area for all vf's */
1181 vf_mbase = dev_vf_mbase_get(pci_dev, dev);
1184 goto mbox_unregister;
1186 /* Init mbox object */
1187 rc = mbox_init(&dev->mbox_vfpf, vf_mbase, bar2, MBOX_DIR_PFVF,
1188 pci_dev->max_vfs, intr_offset);
1192 /* PF -> VF UP messages */
1193 rc = mbox_init(&dev->mbox_vfpf_up, vf_mbase, bar2,
1194 MBOX_DIR_PFVF_UP, pci_dev->max_vfs, intr_offset);
1199 /* Register VF-FLR irq handlers */
1200 if (!dev_is_vf(dev)) {
1201 rc = vf_flr_register_irqs(pci_dev, dev);
1205 dev->mbox_active = 1;
1207 rc = npa_lf_init(dev, pci_dev);
1211 /* Setup LMT line base */
1212 rc = dev_lmt_setup(dev);
1218 dev_vf_mbase_put(pci_dev, vf_mbase);
1220 mbox_unregister_irq(pci_dev, dev);
1224 mbox_fini(dev->mbox);
1225 mbox_fini(&dev->mbox_up);
1231 dev_fini(struct dev *dev, struct plt_pci_device *pci_dev)
1233 struct plt_intr_handle *intr_handle = pci_dev->intr_handle;
1236 /* Check if this dev hosts npalf and has 1+ refs */
1237 if (idev_npa_lf_active(dev) > 1)
1240 /* Clear references to this pci dev */
1243 /* Releasing memory allocated for lmt region */
1245 plt_memzone_free(dev->lmt_mz);
1247 mbox_unregister_irq(pci_dev, dev);
1249 if (!dev_is_vf(dev))
1250 vf_flr_unregister_irqs(pci_dev, dev);
1251 /* Release PF - VF */
1252 mbox = &dev->mbox_vfpf;
1253 if (mbox->hwbase && mbox->dev)
1254 dev_vf_mbase_put(pci_dev, mbox->hwbase);
1260 mbox = &dev->mbox_vfpf_up;
1263 /* Release PF - AF */
1266 mbox = &dev->mbox_up;
1268 dev->mbox_active = 0;
1270 /* Disable MSIX vectors */
1271 dev_irqs_disable(intr_handle);