1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
12 #define DPI_PF_MBOX_SYSFS_ENTRY "dpi_device_config"
15 send_msg_to_pf(struct plt_pci_addr *pci_addr, const char *value, int size)
21 buf, sizeof(buf), "/sys/bus/pci/devices/" PCI_PRI_FMT "/%s",
22 pci_addr->domain, pci_addr->bus, DPI_PF_DBDF_DEVICE & 0x7,
23 DPI_PF_DBDF_FUNCTION & 0x7, DPI_PF_MBOX_SYSFS_ENTRY);
25 if ((res < 0) || ((size_t)res > sizeof(buf)))
28 fd = open(buf, O_WRONLY);
32 res = write(fd, value, size);
41 roc_dpi_enable(struct roc_dpi *dpi)
43 plt_write64(0x1, dpi->rbase + DPI_VDMA_EN);
48 roc_dpi_disable(struct roc_dpi *dpi)
50 plt_write64(0x0, dpi->rbase + DPI_VDMA_EN);
55 roc_dpi_configure(struct roc_dpi *roc_dpi)
57 struct plt_pci_device *pci_dev;
58 const struct plt_memzone *dpi_mz;
59 dpi_mbox_msg_t mbox_msg;
60 struct npa_pool_s pool;
61 struct npa_aura_s aura;
62 int rc, count, buflen;
68 plt_err("roc_dpi is NULL");
72 pci_dev = roc_dpi->pci_dev;
73 memset(&pool, 0, sizeof(struct npa_pool_s));
76 memset(&aura, 0, sizeof(aura));
77 rc = roc_npa_pool_create(&aura_handle, DPI_CMD_QUEUE_SIZE,
78 DPI_CMD_QUEUE_BUFS, &aura, &pool);
80 plt_err("Failed to create NPA pool, err %d\n", rc);
84 snprintf(name, sizeof(name), "dpimem%d", roc_dpi->vfid);
85 buflen = DPI_CMD_QUEUE_SIZE * DPI_CMD_QUEUE_BUFS;
86 dpi_mz = plt_memzone_reserve_aligned(name, buflen, 0,
89 plt_err("dpi memzone reserve failed");
96 for (count = 0; count < DPI_CMD_QUEUE_BUFS; count++) {
97 roc_npa_aura_op_free(aura_handle, 0, iova);
98 iova += DPI_CMD_QUEUE_SIZE;
101 roc_dpi->chunk_base = (void *)roc_npa_aura_op_alloc(aura_handle, 0);
102 if (!roc_dpi->chunk_base) {
103 plt_err("Failed to alloc buffer from NPA aura");
108 roc_dpi->chunk_next = (void *)roc_npa_aura_op_alloc(aura_handle, 0);
109 if (!roc_dpi->chunk_next) {
110 plt_err("Failed to alloc buffer from NPA aura");
115 roc_dpi->aura_handle = aura_handle;
116 /* subtract 2 as they have already been alloc'ed above */
117 roc_dpi->pool_size_m1 = (DPI_CMD_QUEUE_SIZE >> 3) - 2;
119 plt_write64(0x0, roc_dpi->rbase + DPI_VDMA_REQQ_CTL);
120 plt_write64(((uint64_t)(roc_dpi->chunk_base) >> 7) << 7,
121 roc_dpi->rbase + DPI_VDMA_SADDR);
124 /* DPI PF driver expects vfid starts from index 0 */
125 mbox_msg.s.vfid = roc_dpi->vfid;
126 mbox_msg.s.cmd = DPI_QUEUE_OPEN;
127 mbox_msg.s.csize = DPI_CMD_QUEUE_SIZE;
128 mbox_msg.s.aura = roc_npa_aura_handle_to_aura(aura_handle);
129 mbox_msg.s.sso_pf_func = idev_sso_pffunc_get();
130 mbox_msg.s.npa_pf_func = idev_npa_pffunc_get();
132 rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg,
133 sizeof(dpi_mbox_msg_t));
135 plt_err("Failed to send mbox message %d to DPI PF, err %d",
143 plt_memzone_free(dpi_mz);
145 roc_npa_pool_destroy(aura_handle);
150 roc_dpi_dev_init(struct roc_dpi *roc_dpi)
152 struct plt_pci_device *pci_dev = roc_dpi->pci_dev;
155 roc_dpi->rbase = pci_dev->mem_resource[0].addr;
156 vfid = ((pci_dev->addr.devid & 0x1F) << 3) |
157 (pci_dev->addr.function & 0x7);
159 roc_dpi->vfid = vfid;
160 plt_spinlock_init(&roc_dpi->chunk_lock);
166 roc_dpi_dev_fini(struct roc_dpi *roc_dpi)
168 struct plt_pci_device *pci_dev = roc_dpi->pci_dev;
169 dpi_mbox_msg_t mbox_msg;
173 /* Wait for SADDR to become idle */
174 reg = plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR);
175 while (!(reg & BIT_ULL(63)))
176 reg = plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR);
180 mbox_msg.s.vfid = roc_dpi->vfid;
181 mbox_msg.s.cmd = DPI_QUEUE_CLOSE;
183 rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg,
184 sizeof(dpi_mbox_msg_t));
186 plt_err("Failed to send mbox message %d to DPI PF, err %d",
189 roc_npa_pool_destroy(roc_dpi->aura_handle);
190 plt_memzone_free(roc_dpi->mz);