1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
11 static const char name[] = "roc_cn10k_intra_device_conf";
12 const struct plt_memzone *mz;
13 struct idev_cfg *idev;
15 mz = plt_memzone_lookup(name);
19 /* Request for the first time */
20 mz = plt_memzone_reserve_cache_align(name, sizeof(struct idev_cfg));
23 idev_set_defaults(idev);
30 idev_set_defaults(struct idev_cfg *idev)
33 idev->npa_pf_func = 0;
34 idev->max_pools = 128;
35 idev->lmt_pf_func = 0;
36 idev->lmt_base_addr = 0;
37 idev->num_lmtlines = 0;
38 __atomic_store_n(&idev->npa_refcnt, 0, __ATOMIC_RELEASE);
42 idev_npa_pffunc_get(void)
44 struct idev_cfg *idev;
47 idev = idev_get_cfg();
50 npa_pf_func = idev->npa_pf_func;
56 idev_npa_obj_get(void)
58 struct idev_cfg *idev;
60 idev = idev_get_cfg();
61 if (idev && __atomic_load_n(&idev->npa_refcnt, __ATOMIC_ACQUIRE))
68 roc_idev_npa_maxpools_get(void)
70 struct idev_cfg *idev;
73 idev = idev_get_cfg();
76 max_pools = idev->max_pools;
82 roc_idev_npa_maxpools_set(uint32_t max_pools)
84 struct idev_cfg *idev;
86 idev = idev_get_cfg();
88 __atomic_store_n(&idev->max_pools, max_pools, __ATOMIC_RELEASE);
92 idev_npa_lf_active(struct dev *dev)
94 struct idev_cfg *idev;
96 /* Check if npalf is actively used on this dev */
97 idev = idev_get_cfg();
98 if (!idev || !idev->npa || idev->npa->mbox != dev->mbox)
101 return __atomic_load_n(&idev->npa_refcnt, __ATOMIC_ACQUIRE);
105 idev_lmt_pffunc_get(void)
107 struct idev_cfg *idev;
108 uint16_t lmt_pf_func;
110 idev = idev_get_cfg();
113 lmt_pf_func = idev->lmt_pf_func;
119 roc_idev_lmt_base_addr_get(void)
121 uint64_t lmt_base_addr;
122 struct idev_cfg *idev;
124 idev = idev_get_cfg();
127 lmt_base_addr = idev->lmt_base_addr;
129 return lmt_base_addr;
133 roc_idev_num_lmtlines_get(void)
135 struct idev_cfg *idev;
136 uint16_t num_lmtlines;
138 idev = idev_get_cfg();
141 num_lmtlines = idev->num_lmtlines;
147 roc_idev_npa_nix_get(void)
149 struct npa_lf *npa_lf = idev_npa_obj_get();
155 dev = container_of(npa_lf, struct dev, npa);