1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
12 /* Device memory does not support unaligned access, instruct compiler to
13 * not optimize the memory access when working with mailbox memory.
17 /* Header which precedes all mbox messages */
19 uint64_t __io msg_size; /* Total msgs size embedded */
20 uint16_t __io num_msgs; /* No of msgs embedded */
23 /* Header which precedes every msg and is also part of it */
25 uint16_t __io pcifunc; /* Who's sending this msg */
26 uint16_t __io id; /* Mbox message ID */
27 #define MBOX_REQ_SIG (0xdead)
28 #define MBOX_RSP_SIG (0xbeef)
29 /* Signature, for validating corrupted msgs */
31 #define MBOX_VERSION (0x000a)
32 /* Version of msg's structure for this ID */
34 /* Offset of next msg within mailbox region */
35 uint16_t __io next_msgoff;
36 int __io rc; /* Msg processed response code */
39 /* Mailbox message types */
40 #define MBOX_MSG_MASK 0xFFFF
41 #define MBOX_MSG_INVALID 0xFFFE
42 #define MBOX_MSG_MAX 0xFFFF
44 #define MBOX_MESSAGES \
45 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
46 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
47 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach_req, msg_rsp) \
48 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach_req, msg_rsp) \
49 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
50 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
51 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
52 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
53 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
54 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
55 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
57 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
58 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
59 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
60 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
61 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
62 cgx_mac_addr_set_or_get) \
63 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
64 cgx_mac_addr_set_or_get) \
65 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
66 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
67 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
68 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
69 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, \
71 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
72 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
73 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
74 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
75 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
77 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
78 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
79 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
80 cgx_mac_addr_add_rsp) \
81 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
83 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
84 cgx_max_dmac_entries_get_rsp) \
85 M(CGX_SET_LINK_STATE, 0x214, cgx_set_link_state, \
86 cgx_set_link_state_msg, msg_rsp) \
87 M(CGX_GET_PHY_MOD_TYPE, 0x215, cgx_get_phy_mod_type, msg_req, \
89 M(CGX_SET_PHY_MOD_TYPE, 0x216, cgx_set_phy_mod_type, cgx_phy_mod_type, \
91 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
92 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req, \
93 cgx_set_link_mode_rsp) \
94 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, \
96 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \
97 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
98 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
99 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, npa_lf_alloc_req, \
101 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
102 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
103 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, \
105 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
106 M(SSO_LF_ALLOC, 0x600, sso_lf_alloc, sso_lf_alloc_req, \
108 M(SSO_LF_FREE, 0x601, sso_lf_free, sso_lf_free_req, msg_rsp) \
109 M(SSOW_LF_ALLOC, 0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp) \
110 M(SSOW_LF_FREE, 0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp) \
111 M(SSO_HW_SETCONFIG, 0x604, sso_hw_setconfig, sso_hw_setconfig, \
113 M(SSO_GRP_SET_PRIORITY, 0x605, sso_grp_set_priority, sso_grp_priority, \
115 M(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req, \
117 M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp) \
118 M(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg, \
120 M(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req, \
122 M(SSO_HWS_GET_STATS, 0x610, sso_hws_get_stats, sso_info_req, \
124 M(SSO_HW_RELEASE_XAQ, 0x611, sso_hw_release_xaq_aura, \
125 sso_hw_xaq_release, msg_rsp) \
126 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
127 M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \
129 M(TIM_LF_FREE, 0x801, tim_lf_free, tim_ring_req, msg_rsp) \
130 M(TIM_CONFIG_RING, 0x802, tim_config_ring, tim_config_req, msg_rsp) \
131 M(TIM_ENABLE_RING, 0x803, tim_enable_ring, tim_ring_req, \
133 M(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \
134 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
135 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, msg_rsp) \
136 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
137 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
139 M(CPT_SET_CRYPTO_GRP, 0xA03, cpt_set_crypto_grp, \
140 cpt_set_crypto_grp_req_msg, msg_rsp) \
141 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
142 cpt_inline_ipsec_cfg_msg, msg_rsp) \
143 M(CPT_STATS, 0xA05, cpt_sts_get, cpt_sts_req, cpt_sts_rsp) \
144 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
146 M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \
147 cpt_rx_inline_lf_cfg_msg, msg_rsp) \
148 M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg) \
149 M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req, \
151 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
152 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, \
154 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
155 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, \
156 npc_mcam_alloc_entry_req, npc_mcam_alloc_entry_rsp) \
157 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
158 npc_mcam_free_entry_req, msg_rsp) \
159 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
160 npc_mcam_write_entry_req, msg_rsp) \
161 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
162 npc_mcam_ena_dis_entry_req, msg_rsp) \
163 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
164 npc_mcam_ena_dis_entry_req, msg_rsp) \
165 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, \
166 npc_mcam_shift_entry_req, npc_mcam_shift_entry_rsp) \
167 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
168 npc_mcam_alloc_counter_req, npc_mcam_alloc_counter_rsp) \
169 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
170 npc_mcam_oper_counter_req, msg_rsp) \
171 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
172 npc_mcam_unmap_counter_req, msg_rsp) \
173 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
174 npc_mcam_oper_counter_req, msg_rsp) \
175 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
176 npc_mcam_oper_counter_req, npc_mcam_oper_counter_rsp) \
177 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, \
178 npc_mcam_alloc_and_write_entry, npc_mcam_alloc_and_write_entry_req, \
179 npc_mcam_alloc_and_write_entry_rsp) \
180 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, msg_req, \
181 npc_get_kex_cfg_rsp) \
182 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, npc_install_flow_req, \
183 npc_install_flow_rsp) \
184 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, npc_delete_flow_req, \
186 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
187 npc_mcam_read_entry_req, npc_mcam_read_entry_rsp) \
188 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, npc_set_pkind, msg_rsp) \
189 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, msg_req, \
190 npc_mcam_read_base_rule_rsp) \
191 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
192 npc_mcam_get_stats_req, npc_mcam_get_stats_rsp) \
193 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
194 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, nix_lf_alloc_req, \
196 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
197 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
198 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, hwctx_disable_req, \
200 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, nix_txsch_alloc_req, \
201 nix_txsch_alloc_rsp) \
202 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
203 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
205 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
206 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
207 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
208 nix_rss_flowkey_cfg, nix_rss_flowkey_cfg_rsp) \
209 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, \
211 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
212 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
213 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
214 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
215 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
216 nix_mark_format_cfg, nix_mark_format_cfg_rsp) \
217 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
218 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, nix_lso_format_cfg, \
219 nix_lso_format_cfg_rsp) \
220 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, \
222 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, \
224 M(NIX_SET_VLAN_TPID, 0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid, \
226 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
228 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
229 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, \
230 nix_get_mac_addr_rsp) \
231 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
232 nix_inline_ipsec_cfg, msg_rsp) \
233 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \
234 nix_inline_ipsec_lf_cfg, msg_rsp) \
235 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
236 nix_cn10k_aq_enq_rsp) \
237 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info)
239 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
240 #define MBOX_UP_CGX_MESSAGES \
241 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) \
242 M(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, msg_rsp)
245 #define M(_name, _id, _1, _2, _3) MBOX_MSG_##_name = _id,
246 MBOX_MESSAGES MBOX_UP_CGX_MESSAGES
250 /* Mailbox message formats */
252 #define RVU_DEFAULT_PF_FUNC 0xFFFF
254 /* Generic request msg used for those mbox messages which
255 * don't send any data in the request.
258 struct mbox_msghdr hdr;
261 /* Generic response msg used a ack or response for those mbox
262 * messages which does not have a specific rsp msg format.
265 struct mbox_msghdr hdr;
268 /* RVU mailbox error codes
272 RVU_INVALID_VF_ID = -256,
275 struct ready_msg_rsp {
276 struct mbox_msghdr hdr;
277 uint16_t __io sclk_freq; /* SCLK frequency */
278 uint16_t __io rclk_freq; /* RCLK frequency */
281 enum npc_pkind_type {
282 NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
283 NPC_RX_CHLEN24B_PKIND,
284 NPC_RX_CPT_HDR_PKIND,
285 NPC_RX_CHLEN90B_PKIND,
293 /* Struct to set pkind */
294 struct npc_set_pkind {
295 struct mbox_msghdr hdr;
296 #define ROC_PRIV_FLAGS_DEFAULT BIT_ULL(0)
297 #define ROC_PRIV_FLAGS_EDSA BIT_ULL(1)
298 #define ROC_PRIV_FLAGS_HIGIG BIT_ULL(2)
299 #define ROC_PRIV_FLAGS_LEN_90B BIT_ULL(3)
300 #define ROC_PRIV_FLAGS_EXDSA BIT_ULL(4)
301 #define ROC_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5)
302 #define ROC_PRIV_FLAGS_CUSTOM BIT_ULL(63)
304 #define PKIND_TX BIT_ULL(0)
305 #define PKIND_RX BIT_ULL(1)
307 uint8_t __io pkind; /* valid only in case custom flag */
310 /* Structure for requesting resource provisioning.
311 * 'modify' flag to be used when either requesting more
312 * or to detach partial of a certain resource type.
313 * Rest of the fields specify how many of what type to
315 * To request LFs from two blocks of same type this mailbox
316 * can be sent twice as below:
317 * struct rsrc_attach *attach;
318 * .. Allocate memory for message ..
319 * attach->cptlfs = 3; <3 LFs from CPT0>
321 * .. Allocate memory for message ..
322 * attach->modify = 1;
323 * attach->cpt_blkaddr = BLKADDR_CPT1;
324 * attach->cptlfs = 2; <2 LFs from CPT1>
327 struct rsrc_attach_req {
328 struct mbox_msghdr hdr;
329 uint8_t __io modify : 1;
330 uint8_t __io npalf : 1;
331 uint8_t __io nixlf : 1;
334 uint16_t __io timlfs;
335 uint16_t __io cptlfs;
336 uint16_t __io reelfs;
337 /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
338 int __io cpt_blkaddr;
339 /* BLKADDR_REE0/BLKADDR_REE1 or 0 for BLKADDR_REE0 */
340 int __io ree_blkaddr;
343 /* Structure for relinquishing resources.
344 * 'partial' flag to be used when relinquishing all resources
345 * but only of a certain type. If not set, all resources of all
346 * types provisioned to the RVU function will be detached.
348 struct rsrc_detach_req {
349 struct mbox_msghdr hdr;
350 uint8_t __io partial : 1;
351 uint8_t __io npalf : 1;
352 uint8_t __io nixlf : 1;
353 uint8_t __io sso : 1;
354 uint8_t __io ssow : 1;
355 uint8_t __io timlfs : 1;
356 uint8_t __io cptlfs : 1;
357 uint8_t __io reelfs : 1;
360 /* NIX Transmit schedulers */
361 #define NIX_TXSCH_LVL_SMQ 0x0
362 #define NIX_TXSCH_LVL_MDQ 0x0
363 #define NIX_TXSCH_LVL_TL4 0x1
364 #define NIX_TXSCH_LVL_TL3 0x2
365 #define NIX_TXSCH_LVL_TL2 0x3
366 #define NIX_TXSCH_LVL_TL1 0x4
367 #define NIX_TXSCH_LVL_CNT 0x5
370 * Number of resources available to the caller.
371 * In reply to MBOX_MSG_FREE_RSRC_CNT.
373 struct free_rsrcs_rsp {
374 struct mbox_msghdr hdr;
375 uint16_t __io schq[NIX_TXSCH_LVL_CNT];
382 uint16_t __io schq_nix1[NIX_TXSCH_LVL_CNT];
389 #define MSIX_VECTOR_INVALID 0xFFFF
390 #define MAX_RVU_BLKLF_CNT 256
392 struct msix_offset_rsp {
393 struct mbox_msghdr hdr;
394 uint16_t __io npa_msixoff;
395 uint16_t __io nix_msixoff;
398 uint16_t __io timlfs;
399 uint16_t __io cptlfs;
400 uint16_t __io sso_msixoff[MAX_RVU_BLKLF_CNT];
401 uint16_t __io ssow_msixoff[MAX_RVU_BLKLF_CNT];
402 uint16_t __io timlf_msixoff[MAX_RVU_BLKLF_CNT];
403 uint16_t __io cptlf_msixoff[MAX_RVU_BLKLF_CNT];
404 uint16_t __io cpt1_lfs;
405 uint16_t __io ree0_lfs;
406 uint16_t __io ree1_lfs;
407 uint16_t __io cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
408 uint16_t __io ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
409 uint16_t __io ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
412 struct lmtst_tbl_setup_req {
413 struct mbox_msghdr hdr;
415 uint64_t __io dis_sched_early_comp : 1;
416 uint64_t __io sched_ena : 1;
417 uint64_t __io dis_line_pref : 1;
418 uint64_t __io ssow_pf_func : 13;
419 uint16_t __io pcifunc;
420 uint8_t __io use_local_lmt_region;
421 uint64_t __io lmt_iova;
422 uint64_t __io rsvd[2]; /* Future use */
425 /* CGX mbox message formats */
427 struct cgx_stats_rsp {
428 struct mbox_msghdr hdr;
429 #define CGX_RX_STATS_COUNT 13
430 #define CGX_TX_STATS_COUNT 18
431 uint64_t __io rx_stats[CGX_RX_STATS_COUNT];
432 uint64_t __io tx_stats[CGX_TX_STATS_COUNT];
435 struct rpm_stats_rsp {
436 struct mbox_msghdr hdr;
437 #define RPM_RX_STATS_COUNT 43
438 #define RPM_TX_STATS_COUNT 34
439 uint64_t __io rx_stats[RPM_RX_STATS_COUNT];
440 uint64_t __io tx_stats[RPM_TX_STATS_COUNT];
443 struct cgx_fec_stats_rsp {
444 struct mbox_msghdr hdr;
445 uint64_t __io fec_corr_blks;
446 uint64_t __io fec_uncorr_blks;
449 /* Structure for requesting the operation for
450 * setting/getting mac address in the CGX interface
452 struct cgx_mac_addr_set_or_get {
453 struct mbox_msghdr hdr;
454 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
457 /* Structure for requesting the operation to
458 * add DMAC filter entry into CGX interface
460 struct cgx_mac_addr_add_req {
461 struct mbox_msghdr hdr;
462 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
465 /* Structure for response against the operation to
466 * add DMAC filter entry into CGX interface
468 struct cgx_mac_addr_add_rsp {
469 struct mbox_msghdr hdr;
473 /* Structure for requesting the operation to
474 * delete DMAC filter entry from CGX interface
476 struct cgx_mac_addr_del_req {
477 struct mbox_msghdr hdr;
481 /* Structure for response against the operation to
482 * get maximum supported DMAC filter entries
484 struct cgx_max_dmac_entries_get_rsp {
485 struct mbox_msghdr hdr;
486 uint8_t __io max_dmac_filters;
489 struct cgx_link_user_info {
490 uint64_t __io link_up : 1;
491 uint64_t __io full_duplex : 1;
492 uint64_t __io lmac_type_id : 4;
493 uint64_t __io speed : 20; /* speed in Mbps */
494 uint64_t __io an : 1; /* AN supported or not */
495 uint64_t __io fec : 2; /* FEC type if enabled else 0 */
496 uint64_t __io port : 8;
497 #define LMACTYPE_STR_LEN 16
498 char lmac_type[LMACTYPE_STR_LEN];
501 struct cgx_link_info_msg {
502 struct mbox_msghdr hdr;
503 struct cgx_link_user_info link_info;
506 struct cgx_ptp_rx_info_msg {
507 struct mbox_msghdr hdr;
511 struct cgx_pause_frm_cfg {
512 struct mbox_msghdr hdr;
514 /* set = 1 if the request is to config pause frames */
515 /* set = 0 if the request is to fetch pause frames config */
516 uint8_t __io rx_pause;
517 uint8_t __io tx_pause;
520 struct sfp_eeprom_s {
521 #define SFP_EEPROM_SIZE 256
522 uint16_t __io sff_id;
523 uint8_t __io buf[SFP_EEPROM_SIZE];
524 uint64_t __io reserved;
534 uint64_t __io can_change_mod_type : 1;
535 uint64_t __io mod_type : 1;
538 struct cgx_lmac_fwdata_s {
539 uint16_t __io rw_valid;
540 uint64_t __io supported_fec;
541 uint64_t __io supported_an;
542 uint64_t __io supported_link_modes;
543 /* Only applicable if AN is supported */
544 uint64_t __io advertised_fec;
545 uint64_t __io advertised_link_modes;
546 /* Only applicable if SFP/QSFP slot is present */
547 struct sfp_eeprom_s sfp_eeprom;
549 #define LMAC_FWDATA_RESERVED_MEM 1023
550 uint64_t __io reserved[LMAC_FWDATA_RESERVED_MEM];
554 struct mbox_msghdr hdr;
555 struct cgx_lmac_fwdata_s fwdata;
559 struct mbox_msghdr hdr;
563 struct cgx_set_link_state_msg {
564 struct mbox_msghdr hdr;
568 struct cgx_phy_mod_type {
569 struct mbox_msghdr hdr;
573 struct cgx_set_link_mode_args {
581 struct cgx_set_link_mode_req {
582 struct mbox_msghdr hdr;
583 struct cgx_set_link_mode_args args;
586 struct cgx_set_link_mode_rsp {
587 struct mbox_msghdr hdr;
591 /* NPA mbox message formats */
593 /* NPA mailbox error codes
597 NPA_AF_ERR_PARAM = -301,
598 NPA_AF_ERR_AQ_FULL = -302,
599 NPA_AF_ERR_AQ_ENQUEUE = -303,
600 NPA_AF_ERR_AF_LF_INVALID = -304,
601 NPA_AF_ERR_AF_LF_ALLOC = -305,
602 NPA_AF_ERR_LF_RESET = -306,
605 #define NPA_AURA_SZ_0 0
606 #define NPA_AURA_SZ_128 1
607 #define NPA_AURA_SZ_256 2
608 #define NPA_AURA_SZ_512 3
609 #define NPA_AURA_SZ_1K 4
610 #define NPA_AURA_SZ_2K 5
611 #define NPA_AURA_SZ_4K 6
612 #define NPA_AURA_SZ_8K 7
613 #define NPA_AURA_SZ_16K 8
614 #define NPA_AURA_SZ_32K 9
615 #define NPA_AURA_SZ_64K 10
616 #define NPA_AURA_SZ_128K 11
617 #define NPA_AURA_SZ_256K 12
618 #define NPA_AURA_SZ_512K 13
619 #define NPA_AURA_SZ_1M 14
620 #define NPA_AURA_SZ_MAX 15
622 /* For NPA LF context alloc and init */
623 struct npa_lf_alloc_req {
624 struct mbox_msghdr hdr;
626 int __io aura_sz; /* No of auras. See NPA_AURA_SZ_* */
627 uint32_t __io nr_pools; /* No of pools */
628 uint64_t __io way_mask;
631 struct npa_lf_alloc_rsp {
632 struct mbox_msghdr hdr;
633 uint32_t __io stack_pg_ptrs; /* No of ptrs per stack page */
634 uint32_t __io stack_pg_bytes; /* Size of stack page */
635 uint16_t __io qints; /* NPA_AF_CONST::QINTS */
636 uint8_t __io cache_lines; /* Batch Alloc DMA */
639 /* NPA AQ enqueue msg */
640 struct npa_aq_enq_req {
641 struct mbox_msghdr hdr;
642 uint32_t __io aura_id;
646 /* Valid when op == WRITE/INIT and ctype == AURA.
647 * LF fills the pool_id in aura.pool_addr. AF will translate
648 * the pool_id to pool context pointer.
650 __io struct npa_aura_s aura;
651 /* Valid when op == WRITE/INIT and ctype == POOL */
652 __io struct npa_pool_s pool;
654 /* Mask data when op == WRITE (1=write, 0=don't write) */
656 /* Valid when op == WRITE and ctype == AURA */
657 __io struct npa_aura_s aura_mask;
658 /* Valid when op == WRITE and ctype == POOL */
659 __io struct npa_pool_s pool_mask;
663 struct npa_aq_enq_rsp {
664 struct mbox_msghdr hdr;
666 /* Valid when op == READ and ctype == AURA */
667 __io struct npa_aura_s aura;
668 /* Valid when op == READ and ctype == POOL */
669 __io struct npa_pool_s pool;
673 /* Disable all contexts of type 'ctype' */
674 struct hwctx_disable_req {
675 struct mbox_msghdr hdr;
679 /* NIX mbox message formats */
681 /* NIX mailbox error codes
685 NIX_AF_ERR_PARAM = -401,
686 NIX_AF_ERR_AQ_FULL = -402,
687 NIX_AF_ERR_AQ_ENQUEUE = -403,
688 NIX_AF_ERR_AF_LF_INVALID = -404,
689 NIX_AF_ERR_AF_LF_ALLOC = -405,
690 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
691 NIX_AF_ERR_TLX_INVALID = -407,
692 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
693 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
694 NIX_AF_ERR_FRS_INVALID = -410,
695 NIX_AF_ERR_RX_LINK_INVALID = -411,
696 NIX_AF_INVAL_TXSCHQ_CFG = -412,
697 NIX_AF_SMQ_FLUSH_FAILED = -413,
698 NIX_AF_ERR_LF_RESET = -414,
699 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
700 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
701 NIX_AF_ERR_MARK_CFG_FAIL = -417,
702 NIX_AF_ERR_LSO_CFG_FAIL = -418,
703 NIX_AF_INVAL_NPA_PF_FUNC = -419,
704 NIX_AF_INVAL_SSO_PF_FUNC = -420,
705 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
706 NIX_AF_ERR_RX_VTAG_INUSE = -422,
707 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
710 /* For NIX LF context alloc and init */
711 struct nix_lf_alloc_req {
712 struct mbox_msghdr hdr;
714 uint32_t __io rq_cnt; /* No of receive queues */
715 uint32_t __io sq_cnt; /* No of send queues */
716 uint32_t __io cq_cnt; /* No of completion queues */
718 uint16_t __io rss_sz;
719 uint8_t __io rss_grps;
720 uint16_t __io npa_func;
721 /* RVU_DEFAULT_PF_FUNC == default pf_func associated with lf */
722 uint16_t __io sso_func;
723 uint64_t __io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
724 uint64_t __io way_mask;
725 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
729 struct nix_lf_alloc_rsp {
730 struct mbox_msghdr hdr;
731 uint16_t __io sqb_size;
732 uint16_t __io rx_chan_base;
733 uint16_t __io tx_chan_base;
734 uint8_t __io rx_chan_cnt; /* Total number of RX channels */
735 uint8_t __io tx_chan_cnt; /* Total number of TX channels */
736 uint8_t __io lso_tsov4_idx;
737 uint8_t __io lso_tsov6_idx;
738 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
739 uint8_t __io lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
740 uint8_t __io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
741 uint16_t __io cints; /* NIX_AF_CONST2::CINTS */
742 uint16_t __io qints; /* NIX_AF_CONST2::QINTS */
743 uint8_t __io hw_rx_tstamp_en; /*set if rx timestamping enabled */
744 uint8_t __io cgx_links; /* No. of CGX links present in HW */
745 uint8_t __io lbk_links; /* No. of LBK links present in HW */
746 uint8_t __io sdp_links; /* No. of SDP links present in HW */
747 uint8_t tx_link; /* Transmit channel link number */
750 struct nix_lf_free_req {
751 struct mbox_msghdr hdr;
752 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
753 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
757 /* CN10x NIX AQ enqueue msg */
758 struct nix_cn10k_aq_enq_req {
759 struct mbox_msghdr hdr;
764 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
765 __io struct nix_cn10k_rq_ctx_s rq;
766 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
767 __io struct nix_cn10k_sq_ctx_s sq;
768 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
769 __io struct nix_cq_ctx_s cq;
770 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
771 __io struct nix_rsse_s rss;
772 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
773 __io struct nix_rx_mce_s mce;
775 /* Mask data when op == WRITE (1=write, 0=don't write) */
777 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
778 __io struct nix_cn10k_rq_ctx_s rq_mask;
779 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
780 __io struct nix_cn10k_sq_ctx_s sq_mask;
781 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
782 __io struct nix_cq_ctx_s cq_mask;
783 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
784 __io struct nix_rsse_s rss_mask;
785 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
786 __io struct nix_rx_mce_s mce_mask;
790 struct nix_cn10k_aq_enq_rsp {
791 struct mbox_msghdr hdr;
793 struct nix_cn10k_rq_ctx_s rq;
794 struct nix_cn10k_sq_ctx_s sq;
795 struct nix_cq_ctx_s cq;
796 struct nix_rsse_s rss;
797 struct nix_rx_mce_s mce;
801 /* NIX AQ enqueue msg */
802 struct nix_aq_enq_req {
803 struct mbox_msghdr hdr;
808 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
809 __io struct nix_rq_ctx_s rq;
810 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
811 __io struct nix_sq_ctx_s sq;
812 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
813 __io struct nix_cq_ctx_s cq;
814 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
815 __io struct nix_rsse_s rss;
816 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
817 __io struct nix_rx_mce_s mce;
819 /* Mask data when op == WRITE (1=write, 0=don't write) */
821 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
822 __io struct nix_rq_ctx_s rq_mask;
823 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
824 __io struct nix_sq_ctx_s sq_mask;
825 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
826 __io struct nix_cq_ctx_s cq_mask;
827 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
828 __io struct nix_rsse_s rss_mask;
829 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
830 __io struct nix_rx_mce_s mce_mask;
834 struct nix_aq_enq_rsp {
835 struct mbox_msghdr hdr;
837 __io struct nix_rq_ctx_s rq;
838 __io struct nix_sq_ctx_s sq;
839 __io struct nix_cq_ctx_s cq;
840 __io struct nix_rsse_s rss;
841 __io struct nix_rx_mce_s mce;
845 /* Tx scheduler/shaper mailbox messages */
847 #define MAX_TXSCHQ_PER_FUNC 128
849 struct nix_txsch_alloc_req {
850 struct mbox_msghdr hdr;
851 /* Scheduler queue count request at each level */
852 uint16_t __io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
853 uint16_t __io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
856 struct nix_txsch_alloc_rsp {
857 struct mbox_msghdr hdr;
858 /* Scheduler queue count allocated at each level */
859 uint16_t __io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
860 uint16_t __io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
861 /* Scheduler queue list allocated at each level */
862 uint16_t __io schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
863 uint16_t __io schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
864 /* Traffic aggregation scheduler level */
865 uint8_t __io aggr_level;
866 /* Aggregation lvl's RR_PRIO config */
867 uint8_t __io aggr_lvl_rr_prio;
868 /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
869 uint8_t __io link_cfg_lvl;
872 struct nix_txsch_free_req {
873 struct mbox_msghdr hdr;
874 #define TXSCHQ_FREE_ALL BIT_ULL(0)
876 /* Scheduler queue level to be freed */
877 uint16_t __io schq_lvl;
878 /* List of scheduler queues to be freed */
882 struct nix_txschq_config {
883 struct mbox_msghdr hdr;
884 uint8_t __io lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
886 #define TXSCHQ_IDX_SHIFT 16
887 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
888 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
889 uint8_t __io num_regs;
890 #define MAX_REGS_PER_MBOX_MSG 20
891 uint64_t __io reg[MAX_REGS_PER_MBOX_MSG];
892 uint64_t __io regval[MAX_REGS_PER_MBOX_MSG];
893 /* All 0's => overwrite with new value */
894 uint64_t __io regval_mask[MAX_REGS_PER_MBOX_MSG];
897 struct nix_vtag_config {
898 struct mbox_msghdr hdr;
899 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
900 uint8_t __io vtag_size;
901 /* cfg_type is '0' for tx vlan cfg
902 * cfg_type is '1' for rx vlan cfg
904 uint8_t __io cfg_type;
906 /* Valid when cfg_type is '0' */
911 /* cfg_vtag0 & cfg_vtag1 fields are valid
912 * when free_vtag0 & free_vtag1 are '0's.
914 /* cfg_vtag0 = 1 to configure vtag0 */
915 uint8_t __io cfg_vtag0 : 1;
916 /* cfg_vtag1 = 1 to configure vtag1 */
917 uint8_t __io cfg_vtag1 : 1;
919 /* vtag0_idx & vtag1_idx are only valid when
920 * both cfg_vtag0 & cfg_vtag1 are '0's,
921 * these fields are used along with free_vtag0
922 * & free_vtag1 to free the nix lf's tx_vlan
925 * Denotes the indices of tx_vtag def registers
926 * that needs to be cleared and freed.
931 /* Free_vtag0 & free_vtag1 fields are valid
932 * when cfg_vtag0 & cfg_vtag1 are '0's.
934 /* Free_vtag0 = 1 clears vtag0 configuration
935 * vtag0_idx denotes the index to be cleared.
937 uint8_t __io free_vtag0 : 1;
938 /* Free_vtag1 = 1 clears vtag1 configuration
939 * vtag1_idx denotes the index to be cleared.
941 uint8_t __io free_vtag1 : 1;
944 /* Valid when cfg_type is '1' */
946 /* Rx vtag type index, valid values are in 0..7 range */
947 uint8_t __io vtag_type;
949 uint8_t __io strip_vtag : 1;
950 /* Rx vtag capture */
951 uint8_t __io capture_vtag : 1;
956 struct nix_vtag_config_rsp {
957 struct mbox_msghdr hdr;
958 /* Indices of tx_vtag def registers used to configure
959 * tx vtag0 & vtag1 headers, these indices are valid
960 * when nix_vtag_config mbox requested for vtag0 and/
961 * or vtag1 configuration.
967 struct nix_rss_flowkey_cfg {
968 struct mbox_msghdr hdr;
969 int __io mcam_index; /* MCAM entry index to modify */
970 uint32_t __io flowkey_cfg; /* Flowkey types selected */
971 #define FLOW_KEY_TYPE_PORT BIT(0)
972 #define FLOW_KEY_TYPE_IPV4 BIT(1)
973 #define FLOW_KEY_TYPE_IPV6 BIT(2)
974 #define FLOW_KEY_TYPE_TCP BIT(3)
975 #define FLOW_KEY_TYPE_UDP BIT(4)
976 #define FLOW_KEY_TYPE_SCTP BIT(5)
977 #define FLOW_KEY_TYPE_NVGRE BIT(6)
978 #define FLOW_KEY_TYPE_VXLAN BIT(7)
979 #define FLOW_KEY_TYPE_GENEVE BIT(8)
980 #define FLOW_KEY_TYPE_ETH_DMAC BIT(9)
981 #define FLOW_KEY_TYPE_IPV6_EXT BIT(10)
982 #define FLOW_KEY_TYPE_GTPU BIT(11)
983 #define FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
984 #define FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
985 #define FLOW_KEY_TYPE_INNR_TCP BIT(14)
986 #define FLOW_KEY_TYPE_INNR_UDP BIT(15)
987 #define FLOW_KEY_TYPE_INNR_SCTP BIT(16)
988 #define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
989 #define FLOW_KEY_TYPE_CH_LEN_90B BIT(18)
990 #define FLOW_KEY_TYPE_CUSTOM0 BIT(19)
991 #define FLOW_KEY_TYPE_VLAN BIT(20)
992 #define FLOW_KEY_TYPE_L4_DST BIT(28)
993 #define FLOW_KEY_TYPE_L4_SRC BIT(29)
994 #define FLOW_KEY_TYPE_L3_DST BIT(30)
995 #define FLOW_KEY_TYPE_L3_SRC BIT(31)
996 uint8_t __io group; /* RSS context or group */
999 struct nix_rss_flowkey_cfg_rsp {
1000 struct mbox_msghdr hdr;
1001 uint8_t __io alg_idx; /* Selected algo index */
1004 struct nix_set_mac_addr {
1005 struct mbox_msghdr hdr;
1006 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
1009 struct nix_get_mac_addr_rsp {
1010 struct mbox_msghdr hdr;
1011 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
1014 struct nix_mark_format_cfg {
1015 struct mbox_msghdr hdr;
1016 uint8_t __io offset;
1017 uint8_t __io y_mask;
1019 uint8_t __io r_mask;
1023 struct nix_mark_format_cfg_rsp {
1024 struct mbox_msghdr hdr;
1025 uint8_t __io mark_format_idx;
1028 struct nix_lso_format_cfg {
1029 struct mbox_msghdr hdr;
1030 uint64_t __io field_mask;
1031 uint64_t __io fields[NIX_LSO_FIELD_MAX];
1034 struct nix_lso_format_cfg_rsp {
1035 struct mbox_msghdr hdr;
1036 uint8_t __io lso_format_idx;
1039 struct nix_rx_mode {
1040 struct mbox_msghdr hdr;
1041 #define NIX_RX_MODE_UCAST BIT(0)
1042 #define NIX_RX_MODE_PROMISC BIT(1)
1043 #define NIX_RX_MODE_ALLMULTI BIT(2)
1048 struct mbox_msghdr hdr;
1049 #define NIX_RX_OL3_VERIFY BIT(0)
1050 #define NIX_RX_OL4_VERIFY BIT(1)
1051 uint8_t __io len_verify; /* Outer L3/L4 len check */
1052 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1053 uint8_t __io csum_verify; /* Outer L4 checksum verification */
1056 struct nix_frs_cfg {
1057 struct mbox_msghdr hdr;
1058 uint8_t __io update_smq; /* Update SMQ's min/max lens */
1059 uint8_t __io update_minlen; /* Set minlen also */
1060 uint8_t __io sdp_link; /* Set SDP RX link */
1061 uint16_t __io maxlen;
1062 uint16_t __io minlen;
1065 struct nix_set_vlan_tpid {
1066 struct mbox_msghdr hdr;
1067 #define NIX_VLAN_TYPE_INNER 0
1068 #define NIX_VLAN_TYPE_OUTER 1
1069 uint8_t __io vlan_type;
1073 struct nix_bp_cfg_req {
1074 struct mbox_msghdr hdr;
1075 uint16_t __io chan_base; /* Starting channel number */
1076 uint8_t __io chan_cnt; /* Number of channels */
1077 uint8_t __io bpid_per_chan;
1078 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1079 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1082 /* PF can be mapped to either CGX or LBK interface,
1083 * so maximum 64 channels are possible.
1085 #define NIX_MAX_CHAN 64
1086 struct nix_bp_cfg_rsp {
1087 struct mbox_msghdr hdr;
1088 /* Channel and bpid mapping */
1089 uint16_t __io chan_bpid[NIX_MAX_CHAN];
1090 /* Number of channel for which bpids are assigned */
1091 uint8_t __io chan_cnt;
1094 /* Global NIX inline IPSec configuration */
1095 struct nix_inline_ipsec_cfg {
1096 struct mbox_msghdr hdr;
1097 uint32_t __io cpt_credit;
1100 uint8_t __io opcode;
1103 uint16_t __io cpt_pf_func;
1104 uint8_t __io cpt_slot;
1106 uint8_t __io enable;
1109 /* Per NIX LF inline IPSec configuration */
1110 struct nix_inline_ipsec_lf_cfg {
1111 struct mbox_msghdr hdr;
1112 uint64_t __io sa_base_addr;
1114 uint32_t __io tag_const;
1115 uint16_t __io lenm1_max;
1116 uint8_t __io sa_pow2_size;
1120 uint32_t __io sa_idx_max;
1121 uint8_t __io sa_idx_w;
1123 uint8_t __io enable;
1126 struct nix_hw_info {
1127 struct mbox_msghdr hdr;
1128 uint16_t __io vwqe_delay;
1129 uint16_t __io rsvd[15];
1132 /* SSO mailbox error codes
1135 enum sso_af_status {
1136 SSO_AF_ERR_PARAM = -501,
1137 SSO_AF_ERR_LF_INVALID = -502,
1138 SSO_AF_ERR_AF_LF_ALLOC = -503,
1139 SSO_AF_ERR_GRP_EBUSY = -504,
1140 SSO_AF_INVAL_NPA_PF_FUNC = -505,
1143 struct sso_lf_alloc_req {
1144 struct mbox_msghdr hdr;
1146 uint16_t __io hwgrps;
1149 struct sso_lf_alloc_rsp {
1150 struct mbox_msghdr hdr;
1151 uint32_t __io xaq_buf_size;
1152 uint32_t __io xaq_wq_entries;
1153 uint32_t __io in_unit_entries;
1154 uint16_t __io hwgrps;
1157 struct sso_lf_free_req {
1158 struct mbox_msghdr hdr;
1160 uint16_t __io hwgrps;
1163 /* SSOW mailbox error codes
1166 enum ssow_af_status {
1167 SSOW_AF_ERR_PARAM = -601,
1168 SSOW_AF_ERR_LF_INVALID = -602,
1169 SSOW_AF_ERR_AF_LF_ALLOC = -603,
1172 struct ssow_lf_alloc_req {
1173 struct mbox_msghdr hdr;
1178 struct ssow_lf_free_req {
1179 struct mbox_msghdr hdr;
1184 struct sso_hw_setconfig {
1185 struct mbox_msghdr hdr;
1186 uint32_t __io npa_aura_id;
1187 uint16_t __io npa_pf_func;
1188 uint16_t __io hwgrps;
1191 struct sso_hw_xaq_release {
1192 struct mbox_msghdr hdr;
1193 uint16_t __io hwgrps;
1196 struct sso_info_req {
1197 struct mbox_msghdr hdr;
1204 struct sso_grp_priority {
1205 struct mbox_msghdr hdr;
1207 uint8_t __io priority;
1208 uint8_t __io affinity;
1209 uint8_t __io weight;
1212 struct sso_grp_qos_cfg {
1213 struct mbox_msghdr hdr;
1215 uint32_t __io xaq_limit;
1216 uint16_t __io taq_thr;
1217 uint16_t __io iaq_thr;
1220 struct sso_grp_stats {
1221 struct mbox_msghdr hdr;
1223 uint64_t __io ws_pc;
1224 uint64_t __io ext_pc;
1225 uint64_t __io wa_pc;
1226 uint64_t __io ts_pc;
1227 uint64_t __io ds_pc;
1228 uint64_t __io dq_pc;
1229 uint64_t __io aw_status;
1230 uint64_t __io page_cnt;
1233 struct sso_hws_stats {
1234 struct mbox_msghdr hdr;
1236 uint64_t __io arbitration;
1239 /* CPT mailbox error codes
1242 enum cpt_af_status {
1243 CPT_AF_ERR_PARAM = -901,
1244 CPT_AF_ERR_GRP_INVALID = -902,
1245 CPT_AF_ERR_LF_INVALID = -903,
1246 CPT_AF_ERR_ACCESS_DENIED = -904,
1247 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1248 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1249 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1250 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1253 /* CPT mbox message formats */
1255 struct cpt_rd_wr_reg_msg {
1256 struct mbox_msghdr hdr;
1257 uint64_t __io reg_offset;
1258 uint64_t __io *ret_val;
1260 uint8_t __io is_write;
1263 struct cpt_set_crypto_grp_req_msg {
1264 struct mbox_msghdr hdr;
1265 uint8_t __io crypto_eng_grp;
1268 struct cpt_lf_alloc_req_msg {
1269 struct mbox_msghdr hdr;
1270 uint16_t __io nix_pf_func;
1271 uint16_t __io sso_pf_func;
1272 uint16_t __io eng_grpmsk;
1273 uint8_t __io blkaddr;
1276 #define CPT_INLINE_INBOUND 0
1277 #define CPT_INLINE_OUTBOUND 1
1279 struct cpt_inline_ipsec_cfg_msg {
1280 struct mbox_msghdr hdr;
1281 uint8_t __io enable;
1284 uint8_t __io sso_pf_func_ovrd;
1285 uint16_t __io sso_pf_func; /* Inbound path SSO_PF_FUNC */
1286 uint16_t __io nix_pf_func; /* Outbound path NIX_PF_FUNC */
1289 struct cpt_sts_req {
1290 struct mbox_msghdr hdr;
1291 uint8_t __io blkaddr;
1294 struct cpt_sts_rsp {
1295 struct mbox_msghdr hdr;
1296 uint64_t __io inst_req_pc;
1297 uint64_t __io inst_lat_pc;
1298 uint64_t __io rd_req_pc;
1299 uint64_t __io rd_lat_pc;
1300 uint64_t __io rd_uc_pc;
1301 uint64_t __io active_cycles_pc;
1302 uint64_t __io ctx_mis_pc;
1303 uint64_t __io ctx_hit_pc;
1304 uint64_t __io ctx_aop_pc;
1305 uint64_t __io ctx_aop_lat_pc;
1306 uint64_t __io ctx_ifetch_pc;
1307 uint64_t __io ctx_ifetch_lat_pc;
1308 uint64_t __io ctx_ffetch_pc;
1309 uint64_t __io ctx_ffetch_lat_pc;
1310 uint64_t __io ctx_wback_pc;
1311 uint64_t __io ctx_wback_lat_pc;
1312 uint64_t __io ctx_psh_pc;
1313 uint64_t __io ctx_psh_lat_pc;
1314 uint64_t __io ctx_err;
1315 uint64_t __io ctx_enc_id;
1316 uint64_t __io ctx_flush_timer;
1317 uint64_t __io rxc_time;
1318 uint64_t __io rxc_time_cfg;
1319 uint64_t __io rxc_active_sts;
1320 uint64_t __io rxc_zombie_sts;
1321 uint64_t __io busy_sts_ae;
1322 uint64_t __io free_sts_ae;
1323 uint64_t __io busy_sts_se;
1324 uint64_t __io free_sts_se;
1325 uint64_t __io busy_sts_ie;
1326 uint64_t __io free_sts_ie;
1327 uint64_t __io exe_err_info;
1328 uint64_t __io cptclk_cnt;
1330 uint64_t __io rxc_dfrg;
1331 uint64_t __io x2p_link_cfg0;
1332 uint64_t __io x2p_link_cfg1;
1335 struct cpt_rxc_time_cfg_req {
1336 struct mbox_msghdr hdr;
1339 uint16_t zombie_thres;
1340 uint16_t zombie_limit;
1341 uint16_t active_thres;
1342 uint16_t active_limit;
1345 struct cpt_rx_inline_lf_cfg_msg {
1346 struct mbox_msghdr hdr;
1347 uint16_t __io sso_pf_func;
1348 uint16_t __io param1;
1349 uint16_t __io param2;
1350 uint16_t __io reserved;
1354 CPT_ENG_TYPE_AE = 1,
1355 CPT_ENG_TYPE_SE = 2,
1356 CPT_ENG_TYPE_IE = 3,
1360 /* CPT HW capabilities */
1361 union cpt_eng_caps {
1364 uint64_t __io reserved_0_4 : 5;
1365 uint64_t __io mul : 1;
1366 uint64_t __io sha1_sha2 : 1;
1367 uint64_t __io chacha20 : 1;
1368 uint64_t __io zuc_snow3g : 1;
1369 uint64_t __io sha3 : 1;
1370 uint64_t __io aes : 1;
1371 uint64_t __io kasumi : 1;
1372 uint64_t __io des : 1;
1373 uint64_t __io crc : 1;
1374 uint64_t __io reserved_14_63 : 50;
1378 struct cpt_caps_rsp_msg {
1379 struct mbox_msghdr hdr;
1380 uint16_t __io cpt_pf_drv_version;
1381 uint8_t __io cpt_revision;
1382 union cpt_eng_caps eng_caps[CPT_MAX_ENG_TYPES];
1385 struct cpt_eng_grp_req {
1386 struct mbox_msghdr hdr;
1387 uint8_t __io eng_type;
1390 struct cpt_eng_grp_rsp {
1391 struct mbox_msghdr hdr;
1392 uint8_t __io eng_type;
1393 uint8_t __io eng_grp_num;
1396 /* NPC mbox message structs */
1398 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1399 #define NPC_MCAM_INVALID_MAP 0xFFFF
1401 /* NPC mailbox error codes
1404 enum npc_af_status {
1405 NPC_MCAM_INVALID_REQ = -701,
1406 NPC_MCAM_ALLOC_DENIED = -702,
1407 NPC_MCAM_ALLOC_FAILED = -703,
1408 NPC_MCAM_PERM_DENIED = -704,
1409 NPC_AF_ERR_HIGIG_CONFIG_FAIL = -705,
1412 struct npc_mcam_alloc_entry_req {
1413 struct mbox_msghdr hdr;
1414 #define NPC_MAX_NONCONTIG_ENTRIES 256
1415 uint8_t __io contig; /* Contiguous entries ? */
1416 #define NPC_MCAM_ANY_PRIO 0
1417 #define NPC_MCAM_LOWER_PRIO 1
1418 #define NPC_MCAM_HIGHER_PRIO 2
1419 uint8_t __io priority; /* Lower or higher w.r.t ref_entry */
1420 uint16_t __io ref_entry;
1421 uint16_t __io count; /* Number of entries requested */
1424 struct npc_mcam_alloc_entry_rsp {
1425 struct mbox_msghdr hdr;
1426 /* Entry alloc'ed or start index if contiguous.
1427 * Invalid in case of non-contiguous.
1429 uint16_t __io entry;
1430 uint16_t __io count; /* Number of entries allocated */
1431 uint16_t __io free_count; /* Number of entries available */
1432 uint16_t __io entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1435 struct npc_mcam_free_entry_req {
1436 struct mbox_msghdr hdr;
1437 uint16_t __io entry; /* Entry index to be freed */
1438 uint8_t __io all; /* Free all entries alloc'ed to this PFVF */
1442 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max key width */
1443 uint64_t __io kw[NPC_MAX_KWS_IN_KEY];
1444 uint64_t __io kw_mask[NPC_MAX_KWS_IN_KEY];
1445 uint64_t __io action;
1446 uint64_t __io vtag_action;
1449 struct npc_mcam_write_entry_req {
1450 struct mbox_msghdr hdr;
1451 struct mcam_entry entry_data;
1452 uint16_t __io entry; /* MCAM entry to write this match key */
1453 uint16_t __io cntr; /* Counter for this MCAM entry */
1454 uint8_t __io intf; /* Rx or Tx interface */
1455 uint8_t __io enable_entry; /* Enable this MCAM entry ? */
1456 uint8_t __io set_cntr; /* Set counter for this entry ? */
1459 /* Enable/Disable a given entry */
1460 struct npc_mcam_ena_dis_entry_req {
1461 struct mbox_msghdr hdr;
1462 uint16_t __io entry;
1465 struct npc_mcam_shift_entry_req {
1466 struct mbox_msghdr hdr;
1467 #define NPC_MCAM_MAX_SHIFTS 64
1468 uint16_t __io curr_entry[NPC_MCAM_MAX_SHIFTS];
1469 uint16_t __io new_entry[NPC_MCAM_MAX_SHIFTS];
1470 uint16_t __io shift_count; /* Number of entries to shift */
1473 struct npc_mcam_shift_entry_rsp {
1474 struct mbox_msghdr hdr;
1475 /* Index in 'curr_entry', not entry itself */
1476 uint16_t __io failed_entry_idx;
1479 struct npc_mcam_alloc_counter_req {
1480 struct mbox_msghdr hdr;
1481 uint8_t __io contig; /* Contiguous counters ? */
1482 #define NPC_MAX_NONCONTIG_COUNTERS 64
1483 uint16_t __io count; /* Number of counters requested */
1486 struct npc_mcam_alloc_counter_rsp {
1487 struct mbox_msghdr hdr;
1488 /* Counter alloc'ed or start idx if contiguous.
1489 * Invalid in case of non-contiguous.
1492 uint16_t __io count; /* Number of counters allocated */
1493 uint16_t __io cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1496 struct npc_mcam_oper_counter_req {
1497 struct mbox_msghdr hdr;
1498 uint16_t __io cntr; /* Free a counter or clear/fetch it's stats */
1501 struct npc_mcam_oper_counter_rsp {
1502 struct mbox_msghdr hdr;
1503 /* valid only while fetching counter's stats */
1507 struct npc_mcam_unmap_counter_req {
1508 struct mbox_msghdr hdr;
1510 uint16_t __io entry; /* Entry and counter to be unmapped */
1511 uint8_t __io all; /* Unmap all entries using this counter ? */
1514 struct npc_mcam_alloc_and_write_entry_req {
1515 struct mbox_msghdr hdr;
1516 struct mcam_entry entry_data;
1517 uint16_t __io ref_entry;
1518 uint8_t __io priority; /* Lower or higher w.r.t ref_entry */
1519 uint8_t __io intf; /* Rx or Tx interface */
1520 uint8_t __io enable_entry; /* Enable this MCAM entry ? */
1521 uint8_t __io alloc_cntr; /* Allocate counter and map ? */
1524 struct npc_mcam_alloc_and_write_entry_rsp {
1525 struct mbox_msghdr hdr;
1526 uint16_t __io entry;
1530 struct npc_get_kex_cfg_rsp {
1531 struct mbox_msghdr hdr;
1532 uint64_t __io rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1533 uint64_t __io tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1534 #define NPC_MAX_INTF 2
1535 #define NPC_MAX_LID 8
1536 #define NPC_MAX_LT 16
1537 #define NPC_MAX_LD 2
1538 #define NPC_MAX_LFL 16
1539 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1540 uint64_t __io kex_ld_flags[NPC_MAX_LD];
1541 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1542 uint64_t __io intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT]
1544 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1545 uint64_t __io intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1546 #define MKEX_NAME_LEN 128
1547 uint8_t __io mkex_pfl_name[MKEX_NAME_LEN];
1550 enum header_fields {
1565 NPC_HEADER_FIELDS_MAX,
1569 unsigned char __io dmac[6];
1570 unsigned char __io smac[6];
1571 uint16_t __io etype;
1572 uint16_t __io vlan_etype;
1573 uint16_t __io vlan_tci;
1575 uint32_t __io ip4src;
1576 uint32_t __io ip6src[4];
1579 uint32_t __io ip4dst;
1580 uint32_t __io ip6dst[4];
1583 uint8_t __io ip_ver;
1584 uint8_t __io ip_proto;
1586 uint16_t __io sport;
1587 uint16_t __io dport;
1590 struct npc_install_flow_req {
1591 struct mbox_msghdr hdr;
1592 struct flow_msg packet;
1593 struct flow_msg mask;
1594 uint64_t __io features;
1595 uint16_t __io entry;
1596 uint16_t __io channel;
1598 uint8_t __io set_cntr;
1599 uint8_t __io default_rule;
1600 /* Overwrite(0) or append(1) flow to default rule? */
1601 uint8_t __io append;
1604 uint32_t __io index;
1605 uint16_t __io match_id;
1606 uint8_t __io flow_key_alg;
1609 uint8_t __io vtag0_type;
1610 uint8_t __io vtag0_valid;
1611 uint8_t __io vtag1_type;
1612 uint8_t __io vtag1_valid;
1614 /* vtag tx action */
1615 uint16_t __io vtag0_def;
1616 uint8_t __io vtag0_op;
1617 uint16_t __io vtag1_def;
1618 uint8_t __io vtag1_op;
1621 struct npc_install_flow_rsp {
1622 struct mbox_msghdr hdr;
1623 /* Negative if no counter else counter number */
1627 struct npc_delete_flow_req {
1628 struct mbox_msghdr hdr;
1629 uint16_t __io entry;
1630 uint16_t __io start; /*Disable range of entries */
1632 uint8_t __io all; /* PF + VFs */
1635 struct npc_mcam_read_entry_req {
1636 struct mbox_msghdr hdr;
1637 /* MCAM entry to read */
1638 uint16_t __io entry;
1641 struct npc_mcam_read_entry_rsp {
1642 struct mbox_msghdr hdr;
1643 struct mcam_entry entry_data;
1645 uint8_t __io enable;
1648 struct npc_mcam_read_base_rule_rsp {
1649 struct mbox_msghdr hdr;
1650 struct mcam_entry entry_data;
1653 struct npc_mcam_get_stats_req {
1654 struct mbox_msghdr hdr;
1655 uint16_t __io entry; /* mcam entry */
1658 struct npc_mcam_get_stats_rsp {
1659 struct mbox_msghdr hdr;
1660 uint64_t __io stat; /* counter stats */
1661 uint8_t __io stat_ena; /* enabled */
1664 /* TIM mailbox error codes
1667 enum tim_af_status {
1668 TIM_AF_NO_RINGS_LEFT = -801,
1669 TIM_AF_INVALID_NPA_PF_FUNC = -802,
1670 TIM_AF_INVALID_SSO_PF_FUNC = -803,
1671 TIM_AF_RING_STILL_RUNNING = -804,
1672 TIM_AF_LF_INVALID = -805,
1673 TIM_AF_CSIZE_NOT_ALIGNED = -806,
1674 TIM_AF_CSIZE_TOO_SMALL = -807,
1675 TIM_AF_CSIZE_TOO_BIG = -808,
1676 TIM_AF_INTERVAL_TOO_SMALL = -809,
1677 TIM_AF_INVALID_BIG_ENDIAN_VALUE = -810,
1678 TIM_AF_INVALID_CLOCK_SOURCE = -811,
1679 TIM_AF_GPIO_CLK_SRC_NOT_ENABLED = -812,
1680 TIM_AF_INVALID_BSIZE = -813,
1681 TIM_AF_INVALID_ENABLE_PERIODIC = -814,
1682 TIM_AF_INVALID_ENABLE_DONTFREE = -815,
1683 TIM_AF_ENA_DONTFRE_NSET_PERIODIC = -816,
1684 TIM_AF_RING_ALREADY_DISABLED = -817,
1688 TIM_CLK_SRCS_TENNS = 0,
1689 TIM_CLK_SRCS_GPIO = 1,
1690 TIM_CLK_SRCS_GTI = 2,
1691 TIM_CLK_SRCS_PTP = 3,
1692 TIM_CLK_SRSC_INVALID,
1695 enum tim_gpio_edge {
1696 TIM_GPIO_NO_EDGE = 0,
1697 TIM_GPIO_LTOH_TRANS = 1,
1698 TIM_GPIO_HTOL_TRANS = 2,
1699 TIM_GPIO_BOTH_TRANS = 3,
1704 PTP_OP_ADJFINE = 0, /* adjfine(req.scaled_ppm); */
1705 PTP_OP_GET_CLOCK = 1, /* rsp.clk = get_clock() */
1709 struct mbox_msghdr hdr;
1711 int64_t __io scaled_ppm;
1712 uint8_t __io is_pmu;
1716 struct mbox_msghdr hdr;
1721 struct get_hw_cap_rsp {
1722 struct mbox_msghdr hdr;
1723 /* Schq mapping fixed or flexible */
1724 uint8_t __io nix_fixed_txschq_mapping;
1725 uint8_t __io nix_shaping; /* Is shaping and coloring supported */
1728 struct ndc_sync_op {
1729 struct mbox_msghdr hdr;
1730 uint8_t __io nix_lf_tx_sync;
1731 uint8_t __io nix_lf_rx_sync;
1732 uint8_t __io npa_lf_sync;
1735 struct tim_lf_alloc_req {
1736 struct mbox_msghdr hdr;
1738 uint16_t __io npa_pf_func;
1739 uint16_t __io sso_pf_func;
1742 struct tim_ring_req {
1743 struct mbox_msghdr hdr;
1747 struct tim_config_req {
1748 struct mbox_msghdr hdr;
1750 uint8_t __io bigendian;
1751 uint8_t __io clocksource;
1752 uint8_t __io enableperiodic;
1753 uint8_t __io enabledontfreebuffer;
1754 uint32_t __io bucketsize;
1755 uint32_t __io chunksize;
1756 uint32_t __io interval;
1757 uint8_t __io gpioedge;
1760 struct tim_lf_alloc_rsp {
1761 struct mbox_msghdr hdr;
1762 uint64_t __io tenns_clk;
1765 struct tim_enable_rsp {
1766 struct mbox_msghdr hdr;
1767 uint64_t __io timestarted;
1768 uint32_t __io currentbucket;
1771 struct sdp_node_info {
1772 /* Node to which this PF belons to */
1773 uint8_t __io node_id;
1774 uint8_t __io max_vfs;
1775 uint8_t __io num_pf_rings;
1776 uint8_t __io pf_srn;
1777 #define SDP_MAX_VFS 128
1778 uint8_t __io vf_rings[SDP_MAX_VFS];
1781 struct sdp_chan_info_msg {
1782 struct mbox_msghdr hdr;
1783 struct sdp_node_info info;
1786 #endif /* __ROC_MBOX_H__ */