1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
12 /* Device memory does not support unaligned access, instruct compiler to
13 * not optimize the memory access when working with mailbox memory.
17 /* Header which precedes all mbox messages */
19 uint64_t __io msg_size; /* Total msgs size embedded */
20 uint16_t __io num_msgs; /* No of msgs embedded */
23 /* Header which precedes every msg and is also part of it */
25 uint16_t __io pcifunc; /* Who's sending this msg */
26 uint16_t __io id; /* Mbox message ID */
27 #define MBOX_REQ_SIG (0xdead)
28 #define MBOX_RSP_SIG (0xbeef)
29 /* Signature, for validating corrupted msgs */
31 #define MBOX_VERSION (0x000b)
32 /* Version of msg's structure for this ID */
34 /* Offset of next msg within mailbox region */
35 uint16_t __io next_msgoff;
36 int __io rc; /* Msg processed response code */
39 /* Mailbox message types */
40 #define MBOX_MSG_MASK 0xFFFF
41 #define MBOX_MSG_INVALID 0xFFFE
42 #define MBOX_MSG_MAX 0xFFFF
44 #define MBOX_MESSAGES \
45 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
46 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
47 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach_req, msg_rsp) \
48 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach_req, msg_rsp) \
49 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
50 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
51 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
52 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
53 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
54 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
55 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
57 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
58 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
59 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
60 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
61 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
62 cgx_mac_addr_set_or_get) \
63 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
64 cgx_mac_addr_set_or_get) \
65 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
66 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
67 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
68 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
69 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, \
71 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
72 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
73 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
74 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
75 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
77 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
78 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
79 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
80 cgx_mac_addr_add_rsp) \
81 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
83 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
84 cgx_max_dmac_entries_get_rsp) \
85 M(CGX_SET_LINK_STATE, 0x214, cgx_set_link_state, \
86 cgx_set_link_state_msg, msg_rsp) \
87 M(CGX_GET_PHY_MOD_TYPE, 0x215, cgx_get_phy_mod_type, msg_req, \
89 M(CGX_SET_PHY_MOD_TYPE, 0x216, cgx_set_phy_mod_type, cgx_phy_mod_type, \
91 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
92 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req, \
93 cgx_set_link_mode_rsp) \
94 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, \
96 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \
97 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
98 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
99 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, npa_lf_alloc_req, \
101 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
102 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
103 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, \
105 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
106 M(SSO_LF_ALLOC, 0x600, sso_lf_alloc, sso_lf_alloc_req, \
108 M(SSO_LF_FREE, 0x601, sso_lf_free, sso_lf_free_req, msg_rsp) \
109 M(SSOW_LF_ALLOC, 0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp) \
110 M(SSOW_LF_FREE, 0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp) \
111 M(SSO_HW_SETCONFIG, 0x604, sso_hw_setconfig, sso_hw_setconfig, \
113 M(SSO_GRP_SET_PRIORITY, 0x605, sso_grp_set_priority, sso_grp_priority, \
115 M(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req, \
117 M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp) \
118 M(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg, \
120 M(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req, \
122 M(SSO_HWS_GET_STATS, 0x610, sso_hws_get_stats, sso_info_req, \
124 M(SSO_HW_RELEASE_XAQ, 0x611, sso_hw_release_xaq_aura, \
125 sso_hw_xaq_release, msg_rsp) \
126 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
127 M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \
129 M(TIM_LF_FREE, 0x801, tim_lf_free, tim_ring_req, msg_rsp) \
130 M(TIM_CONFIG_RING, 0x802, tim_config_ring, tim_config_req, msg_rsp) \
131 M(TIM_ENABLE_RING, 0x803, tim_enable_ring, tim_ring_req, \
133 M(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \
134 M(TIM_GET_MIN_INTVL, 0x805, tim_get_min_intvl, tim_intvl_req, \
136 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
137 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, msg_rsp) \
138 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
139 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
141 M(CPT_SET_CRYPTO_GRP, 0xA03, cpt_set_crypto_grp, \
142 cpt_set_crypto_grp_req_msg, msg_rsp) \
143 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
144 cpt_inline_ipsec_cfg_msg, msg_rsp) \
145 M(CPT_STATS, 0xA05, cpt_sts_get, cpt_sts_req, cpt_sts_rsp) \
146 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
148 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \
149 M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \
150 cpt_rx_inline_lf_cfg_msg, msg_rsp) \
151 M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg) \
152 M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req, \
154 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
155 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, \
157 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
158 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, \
159 npc_mcam_alloc_entry_req, npc_mcam_alloc_entry_rsp) \
160 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
161 npc_mcam_free_entry_req, msg_rsp) \
162 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
163 npc_mcam_write_entry_req, msg_rsp) \
164 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
165 npc_mcam_ena_dis_entry_req, msg_rsp) \
166 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
167 npc_mcam_ena_dis_entry_req, msg_rsp) \
168 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, \
169 npc_mcam_shift_entry_req, npc_mcam_shift_entry_rsp) \
170 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
171 npc_mcam_alloc_counter_req, npc_mcam_alloc_counter_rsp) \
172 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
173 npc_mcam_oper_counter_req, msg_rsp) \
174 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
175 npc_mcam_unmap_counter_req, msg_rsp) \
176 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
177 npc_mcam_oper_counter_req, msg_rsp) \
178 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
179 npc_mcam_oper_counter_req, npc_mcam_oper_counter_rsp) \
180 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, \
181 npc_mcam_alloc_and_write_entry, npc_mcam_alloc_and_write_entry_req, \
182 npc_mcam_alloc_and_write_entry_rsp) \
183 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, msg_req, \
184 npc_get_kex_cfg_rsp) \
185 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, npc_install_flow_req, \
186 npc_install_flow_rsp) \
187 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, npc_delete_flow_req, \
189 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
190 npc_mcam_read_entry_req, npc_mcam_read_entry_rsp) \
191 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, npc_set_pkind, msg_rsp) \
192 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, msg_req, \
193 npc_mcam_read_base_rule_rsp) \
194 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
195 npc_mcam_get_stats_req, npc_mcam_get_stats_rsp) \
196 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
197 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, nix_lf_alloc_req, \
199 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
200 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
201 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, hwctx_disable_req, \
203 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, nix_txsch_alloc_req, \
204 nix_txsch_alloc_rsp) \
205 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
206 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
208 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
209 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
210 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
211 nix_rss_flowkey_cfg, nix_rss_flowkey_cfg_rsp) \
212 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, \
214 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
215 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
216 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
217 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
218 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
219 nix_mark_format_cfg, nix_mark_format_cfg_rsp) \
220 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
221 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, nix_lso_format_cfg, \
222 nix_lso_format_cfg_rsp) \
223 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, \
225 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, \
227 M(NIX_SET_VLAN_TPID, 0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid, \
229 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
231 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
232 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, \
233 nix_get_mac_addr_rsp) \
234 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
235 nix_inline_ipsec_cfg, msg_rsp) \
236 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \
237 nix_inline_ipsec_lf_cfg, msg_rsp) \
238 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
239 nix_cn10k_aq_enq_rsp) \
240 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \
241 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, \
242 nix_bandprof_alloc_req, nix_bandprof_alloc_rsp) \
243 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
245 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
246 nix_bandprof_get_hwinfo_rsp) \
247 M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \
249 M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \
252 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
253 #define MBOX_UP_CGX_MESSAGES \
254 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) \
255 M(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, msg_rsp)
258 #define M(_name, _id, _1, _2, _3) MBOX_MSG_##_name = _id,
259 MBOX_MESSAGES MBOX_UP_CGX_MESSAGES
263 /* Mailbox message formats */
265 #define RVU_DEFAULT_PF_FUNC 0xFFFF
267 /* Generic request msg used for those mbox messages which
268 * don't send any data in the request.
271 struct mbox_msghdr hdr;
274 /* Generic response msg used a ack or response for those mbox
275 * messages which does not have a specific rsp msg format.
278 struct mbox_msghdr hdr;
281 /* RVU mailbox error codes
285 RVU_INVALID_VF_ID = -256,
288 struct ready_msg_rsp {
289 struct mbox_msghdr hdr;
290 uint16_t __io sclk_freq; /* SCLK frequency */
291 uint16_t __io rclk_freq; /* RCLK frequency */
294 enum npc_pkind_type {
295 NPC_RX_CUSTOM_PRE_L2_PKIND = 55ULL,
296 NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
297 NPC_RX_CHLEN24B_PKIND,
298 NPC_RX_CPT_HDR_PKIND,
299 NPC_RX_CHLEN90B_PKIND,
307 /* Struct to set pkind */
308 struct npc_set_pkind {
309 struct mbox_msghdr hdr;
310 #define ROC_PRIV_FLAGS_DEFAULT BIT_ULL(0)
311 #define ROC_PRIV_FLAGS_EDSA BIT_ULL(1)
312 #define ROC_PRIV_FLAGS_HIGIG BIT_ULL(2)
313 #define ROC_PRIV_FLAGS_LEN_90B BIT_ULL(3)
314 #define ROC_PRIV_FLAGS_EXDSA BIT_ULL(4)
315 #define ROC_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5)
316 #define ROC_PRIV_FLAGS_CUSTOM BIT_ULL(63)
318 #define PKIND_TX BIT_ULL(0)
319 #define PKIND_RX BIT_ULL(1)
321 uint8_t __io pkind; /* valid only in case custom flag */
322 uint8_t __io var_len_off;
323 /* Offset of custom header length field.
324 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
326 uint8_t __io var_len_off_mask; /* Mask for length with in offset */
327 uint8_t __io shift_dir;
328 /* Shift direction to get length of the
329 * header at var_len_off
333 /* Structure for requesting resource provisioning.
334 * 'modify' flag to be used when either requesting more
335 * or to detach partial of a certain resource type.
336 * Rest of the fields specify how many of what type to
338 * To request LFs from two blocks of same type this mailbox
339 * can be sent twice as below:
340 * struct rsrc_attach *attach;
341 * .. Allocate memory for message ..
342 * attach->cptlfs = 3; <3 LFs from CPT0>
344 * .. Allocate memory for message ..
345 * attach->modify = 1;
346 * attach->cpt_blkaddr = BLKADDR_CPT1;
347 * attach->cptlfs = 2; <2 LFs from CPT1>
350 struct rsrc_attach_req {
351 struct mbox_msghdr hdr;
352 uint8_t __io modify : 1;
353 uint8_t __io npalf : 1;
354 uint8_t __io nixlf : 1;
357 uint16_t __io timlfs;
358 uint16_t __io cptlfs;
359 uint16_t __io reelfs;
360 /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
361 int __io cpt_blkaddr;
362 /* BLKADDR_REE0/BLKADDR_REE1 or 0 for BLKADDR_REE0 */
363 int __io ree_blkaddr;
366 /* Structure for relinquishing resources.
367 * 'partial' flag to be used when relinquishing all resources
368 * but only of a certain type. If not set, all resources of all
369 * types provisioned to the RVU function will be detached.
371 struct rsrc_detach_req {
372 struct mbox_msghdr hdr;
373 uint8_t __io partial : 1;
374 uint8_t __io npalf : 1;
375 uint8_t __io nixlf : 1;
376 uint8_t __io sso : 1;
377 uint8_t __io ssow : 1;
378 uint8_t __io timlfs : 1;
379 uint8_t __io cptlfs : 1;
380 uint8_t __io reelfs : 1;
383 /* NIX Transmit schedulers */
384 #define NIX_TXSCH_LVL_SMQ 0x0
385 #define NIX_TXSCH_LVL_MDQ 0x0
386 #define NIX_TXSCH_LVL_TL4 0x1
387 #define NIX_TXSCH_LVL_TL3 0x2
388 #define NIX_TXSCH_LVL_TL2 0x3
389 #define NIX_TXSCH_LVL_TL1 0x4
390 #define NIX_TXSCH_LVL_CNT 0x5
393 * Number of resources available to the caller.
394 * In reply to MBOX_MSG_FREE_RSRC_CNT.
396 struct free_rsrcs_rsp {
397 struct mbox_msghdr hdr;
398 uint16_t __io schq[NIX_TXSCH_LVL_CNT];
405 uint16_t __io schq_nix1[NIX_TXSCH_LVL_CNT];
412 #define MSIX_VECTOR_INVALID 0xFFFF
413 #define MAX_RVU_BLKLF_CNT 256
415 struct msix_offset_rsp {
416 struct mbox_msghdr hdr;
417 uint16_t __io npa_msixoff;
418 uint16_t __io nix_msixoff;
421 uint16_t __io timlfs;
422 uint16_t __io cptlfs;
423 uint16_t __io sso_msixoff[MAX_RVU_BLKLF_CNT];
424 uint16_t __io ssow_msixoff[MAX_RVU_BLKLF_CNT];
425 uint16_t __io timlf_msixoff[MAX_RVU_BLKLF_CNT];
426 uint16_t __io cptlf_msixoff[MAX_RVU_BLKLF_CNT];
427 uint16_t __io cpt1_lfs;
428 uint16_t __io ree0_lfs;
429 uint16_t __io ree1_lfs;
430 uint16_t __io cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
431 uint16_t __io ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
432 uint16_t __io ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
435 struct lmtst_tbl_setup_req {
436 struct mbox_msghdr hdr;
438 uint64_t __io dis_sched_early_comp : 1;
439 uint64_t __io sched_ena : 1;
440 uint64_t __io dis_line_pref : 1;
441 uint64_t __io ssow_pf_func : 13;
442 uint16_t __io pcifunc;
443 uint8_t __io use_local_lmt_region;
444 uint64_t __io lmt_iova;
445 uint64_t __io rsvd[2]; /* Future use */
448 /* CGX mbox message formats */
450 struct cgx_stats_rsp {
451 struct mbox_msghdr hdr;
452 #define CGX_RX_STATS_COUNT 13
453 #define CGX_TX_STATS_COUNT 18
454 uint64_t __io rx_stats[CGX_RX_STATS_COUNT];
455 uint64_t __io tx_stats[CGX_TX_STATS_COUNT];
458 struct rpm_stats_rsp {
459 struct mbox_msghdr hdr;
460 #define RPM_RX_STATS_COUNT 43
461 #define RPM_TX_STATS_COUNT 34
462 uint64_t __io rx_stats[RPM_RX_STATS_COUNT];
463 uint64_t __io tx_stats[RPM_TX_STATS_COUNT];
466 struct cgx_fec_stats_rsp {
467 struct mbox_msghdr hdr;
468 uint64_t __io fec_corr_blks;
469 uint64_t __io fec_uncorr_blks;
472 /* Structure for requesting the operation for
473 * setting/getting mac address in the CGX interface
475 struct cgx_mac_addr_set_or_get {
476 struct mbox_msghdr hdr;
477 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
480 /* Structure for requesting the operation to
481 * add DMAC filter entry into CGX interface
483 struct cgx_mac_addr_add_req {
484 struct mbox_msghdr hdr;
485 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
488 /* Structure for response against the operation to
489 * add DMAC filter entry into CGX interface
491 struct cgx_mac_addr_add_rsp {
492 struct mbox_msghdr hdr;
496 /* Structure for requesting the operation to
497 * delete DMAC filter entry from CGX interface
499 struct cgx_mac_addr_del_req {
500 struct mbox_msghdr hdr;
504 /* Structure for response against the operation to
505 * get maximum supported DMAC filter entries
507 struct cgx_max_dmac_entries_get_rsp {
508 struct mbox_msghdr hdr;
509 uint8_t __io max_dmac_filters;
512 struct cgx_link_user_info {
513 uint64_t __io link_up : 1;
514 uint64_t __io full_duplex : 1;
515 uint64_t __io lmac_type_id : 4;
516 uint64_t __io speed : 20; /* speed in Mbps */
517 uint64_t __io an : 1; /* AN supported or not */
518 uint64_t __io fec : 2; /* FEC type if enabled else 0 */
519 uint64_t __io port : 8;
520 #define LMACTYPE_STR_LEN 16
521 char lmac_type[LMACTYPE_STR_LEN];
524 struct cgx_link_info_msg {
525 struct mbox_msghdr hdr;
526 struct cgx_link_user_info link_info;
529 struct cgx_ptp_rx_info_msg {
530 struct mbox_msghdr hdr;
534 struct cgx_pause_frm_cfg {
535 struct mbox_msghdr hdr;
537 /* set = 1 if the request is to config pause frames */
538 /* set = 0 if the request is to fetch pause frames config */
539 uint8_t __io rx_pause;
540 uint8_t __io tx_pause;
543 struct sfp_eeprom_s {
544 #define SFP_EEPROM_SIZE 256
545 uint16_t __io sff_id;
546 uint8_t __io buf[SFP_EEPROM_SIZE];
547 uint64_t __io reserved;
557 uint64_t __io can_change_mod_type : 1;
558 uint64_t __io mod_type : 1;
561 struct cgx_lmac_fwdata_s {
562 uint16_t __io rw_valid;
563 uint64_t __io supported_fec;
564 uint64_t __io supported_an;
565 uint64_t __io supported_link_modes;
566 /* Only applicable if AN is supported */
567 uint64_t __io advertised_fec;
568 uint64_t __io advertised_link_modes;
569 /* Only applicable if SFP/QSFP slot is present */
570 struct sfp_eeprom_s sfp_eeprom;
572 #define LMAC_FWDATA_RESERVED_MEM 1023
573 uint64_t __io reserved[LMAC_FWDATA_RESERVED_MEM];
577 struct mbox_msghdr hdr;
578 struct cgx_lmac_fwdata_s fwdata;
582 struct mbox_msghdr hdr;
586 struct cgx_set_link_state_msg {
587 struct mbox_msghdr hdr;
591 struct cgx_phy_mod_type {
592 struct mbox_msghdr hdr;
596 struct cgx_set_link_mode_args {
604 struct cgx_set_link_mode_req {
605 struct mbox_msghdr hdr;
606 struct cgx_set_link_mode_args args;
609 struct cgx_set_link_mode_rsp {
610 struct mbox_msghdr hdr;
614 /* NPA mbox message formats */
616 /* NPA mailbox error codes
620 NPA_AF_ERR_PARAM = -301,
621 NPA_AF_ERR_AQ_FULL = -302,
622 NPA_AF_ERR_AQ_ENQUEUE = -303,
623 NPA_AF_ERR_AF_LF_INVALID = -304,
624 NPA_AF_ERR_AF_LF_ALLOC = -305,
625 NPA_AF_ERR_LF_RESET = -306,
628 #define NPA_AURA_SZ_0 0
629 #define NPA_AURA_SZ_128 1
630 #define NPA_AURA_SZ_256 2
631 #define NPA_AURA_SZ_512 3
632 #define NPA_AURA_SZ_1K 4
633 #define NPA_AURA_SZ_2K 5
634 #define NPA_AURA_SZ_4K 6
635 #define NPA_AURA_SZ_8K 7
636 #define NPA_AURA_SZ_16K 8
637 #define NPA_AURA_SZ_32K 9
638 #define NPA_AURA_SZ_64K 10
639 #define NPA_AURA_SZ_128K 11
640 #define NPA_AURA_SZ_256K 12
641 #define NPA_AURA_SZ_512K 13
642 #define NPA_AURA_SZ_1M 14
643 #define NPA_AURA_SZ_MAX 15
645 /* For NPA LF context alloc and init */
646 struct npa_lf_alloc_req {
647 struct mbox_msghdr hdr;
649 int __io aura_sz; /* No of auras. See NPA_AURA_SZ_* */
650 uint32_t __io nr_pools; /* No of pools */
651 uint64_t __io way_mask;
654 struct npa_lf_alloc_rsp {
655 struct mbox_msghdr hdr;
656 uint32_t __io stack_pg_ptrs; /* No of ptrs per stack page */
657 uint32_t __io stack_pg_bytes; /* Size of stack page */
658 uint16_t __io qints; /* NPA_AF_CONST::QINTS */
659 uint8_t __io cache_lines; /* Batch Alloc DMA */
662 /* NPA AQ enqueue msg */
663 struct npa_aq_enq_req {
664 struct mbox_msghdr hdr;
665 uint32_t __io aura_id;
669 /* Valid when op == WRITE/INIT and ctype == AURA.
670 * LF fills the pool_id in aura.pool_addr. AF will translate
671 * the pool_id to pool context pointer.
673 __io struct npa_aura_s aura;
674 /* Valid when op == WRITE/INIT and ctype == POOL */
675 __io struct npa_pool_s pool;
677 /* Mask data when op == WRITE (1=write, 0=don't write) */
679 /* Valid when op == WRITE and ctype == AURA */
680 __io struct npa_aura_s aura_mask;
681 /* Valid when op == WRITE and ctype == POOL */
682 __io struct npa_pool_s pool_mask;
686 struct npa_aq_enq_rsp {
687 struct mbox_msghdr hdr;
689 /* Valid when op == READ and ctype == AURA */
690 __io struct npa_aura_s aura;
691 /* Valid when op == READ and ctype == POOL */
692 __io struct npa_pool_s pool;
696 /* Disable all contexts of type 'ctype' */
697 struct hwctx_disable_req {
698 struct mbox_msghdr hdr;
702 /* NIX mbox message formats */
704 /* NIX mailbox error codes
708 NIX_AF_ERR_PARAM = -401,
709 NIX_AF_ERR_AQ_FULL = -402,
710 NIX_AF_ERR_AQ_ENQUEUE = -403,
711 NIX_AF_ERR_AF_LF_INVALID = -404,
712 NIX_AF_ERR_AF_LF_ALLOC = -405,
713 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
714 NIX_AF_ERR_TLX_INVALID = -407,
715 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
716 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
717 NIX_AF_ERR_FRS_INVALID = -410,
718 NIX_AF_ERR_RX_LINK_INVALID = -411,
719 NIX_AF_INVAL_TXSCHQ_CFG = -412,
720 NIX_AF_SMQ_FLUSH_FAILED = -413,
721 NIX_AF_ERR_LF_RESET = -414,
722 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
723 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
724 NIX_AF_ERR_MARK_CFG_FAIL = -417,
725 NIX_AF_ERR_LSO_CFG_FAIL = -418,
726 NIX_AF_INVAL_NPA_PF_FUNC = -419,
727 NIX_AF_INVAL_SSO_PF_FUNC = -420,
728 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
729 NIX_AF_ERR_RX_VTAG_INUSE = -422,
730 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
733 /* For NIX LF context alloc and init */
734 struct nix_lf_alloc_req {
735 struct mbox_msghdr hdr;
737 uint32_t __io rq_cnt; /* No of receive queues */
738 uint32_t __io sq_cnt; /* No of send queues */
739 uint32_t __io cq_cnt; /* No of completion queues */
741 uint16_t __io rss_sz;
742 uint8_t __io rss_grps;
743 uint16_t __io npa_func;
744 /* RVU_DEFAULT_PF_FUNC == default pf_func associated with lf */
745 uint16_t __io sso_func;
746 uint64_t __io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
747 uint64_t __io way_mask;
748 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
749 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1)
753 struct nix_lf_alloc_rsp {
754 struct mbox_msghdr hdr;
755 uint16_t __io sqb_size;
756 uint16_t __io rx_chan_base;
757 uint16_t __io tx_chan_base;
758 uint8_t __io rx_chan_cnt; /* Total number of RX channels */
759 uint8_t __io tx_chan_cnt; /* Total number of TX channels */
760 uint8_t __io lso_tsov4_idx;
761 uint8_t __io lso_tsov6_idx;
762 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
763 uint8_t __io lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
764 uint8_t __io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
765 uint16_t __io cints; /* NIX_AF_CONST2::CINTS */
766 uint16_t __io qints; /* NIX_AF_CONST2::QINTS */
767 uint8_t __io hw_rx_tstamp_en; /*set if rx timestamping enabled */
768 uint8_t __io cgx_links; /* No. of CGX links present in HW */
769 uint8_t __io lbk_links; /* No. of LBK links present in HW */
770 uint8_t __io sdp_links; /* No. of SDP links present in HW */
771 uint8_t tx_link; /* Transmit channel link number */
774 struct nix_lf_free_req {
775 struct mbox_msghdr hdr;
776 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
777 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
781 /* CN10x NIX AQ enqueue msg */
782 struct nix_cn10k_aq_enq_req {
783 struct mbox_msghdr hdr;
788 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
789 __io struct nix_cn10k_rq_ctx_s rq;
790 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
791 __io struct nix_cn10k_sq_ctx_s sq;
792 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
793 __io struct nix_cq_ctx_s cq;
794 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
795 __io struct nix_rsse_s rss;
796 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
797 __io struct nix_rx_mce_s mce;
798 /* Valid when op == WRITE/INIT and
799 * ctype == NIX_AQ_CTYPE_BAND_PROF
801 __io struct nix_band_prof_s prof;
803 /* Mask data when op == WRITE (1=write, 0=don't write) */
805 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
806 __io struct nix_cn10k_rq_ctx_s rq_mask;
807 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
808 __io struct nix_cn10k_sq_ctx_s sq_mask;
809 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
810 __io struct nix_cq_ctx_s cq_mask;
811 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
812 __io struct nix_rsse_s rss_mask;
813 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
814 __io struct nix_rx_mce_s mce_mask;
815 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_BAND_PROF */
816 __io struct nix_band_prof_s prof_mask;
820 struct nix_cn10k_aq_enq_rsp {
821 struct mbox_msghdr hdr;
823 struct nix_cn10k_rq_ctx_s rq;
824 struct nix_cn10k_sq_ctx_s sq;
825 struct nix_cq_ctx_s cq;
826 struct nix_rsse_s rss;
827 struct nix_rx_mce_s mce;
828 struct nix_band_prof_s prof;
832 /* NIX AQ enqueue msg */
833 struct nix_aq_enq_req {
834 struct mbox_msghdr hdr;
839 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
840 __io struct nix_rq_ctx_s rq;
841 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
842 __io struct nix_sq_ctx_s sq;
843 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
844 __io struct nix_cq_ctx_s cq;
845 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
846 __io struct nix_rsse_s rss;
847 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
848 __io struct nix_rx_mce_s mce;
850 /* Mask data when op == WRITE (1=write, 0=don't write) */
852 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
853 __io struct nix_rq_ctx_s rq_mask;
854 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
855 __io struct nix_sq_ctx_s sq_mask;
856 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
857 __io struct nix_cq_ctx_s cq_mask;
858 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
859 __io struct nix_rsse_s rss_mask;
860 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
861 __io struct nix_rx_mce_s mce_mask;
865 struct nix_aq_enq_rsp {
866 struct mbox_msghdr hdr;
868 __io struct nix_rq_ctx_s rq;
869 __io struct nix_sq_ctx_s sq;
870 __io struct nix_cq_ctx_s cq;
871 __io struct nix_rsse_s rss;
872 __io struct nix_rx_mce_s mce;
876 /* Tx scheduler/shaper mailbox messages */
878 #define MAX_TXSCHQ_PER_FUNC 128
880 struct nix_txsch_alloc_req {
881 struct mbox_msghdr hdr;
882 /* Scheduler queue count request at each level */
883 uint16_t __io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
884 uint16_t __io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
887 struct nix_txsch_alloc_rsp {
888 struct mbox_msghdr hdr;
889 /* Scheduler queue count allocated at each level */
890 uint16_t __io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
891 uint16_t __io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
892 /* Scheduler queue list allocated at each level */
893 uint16_t __io schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
894 uint16_t __io schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
895 /* Traffic aggregation scheduler level */
896 uint8_t __io aggr_level;
897 /* Aggregation lvl's RR_PRIO config */
898 uint8_t __io aggr_lvl_rr_prio;
899 /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
900 uint8_t __io link_cfg_lvl;
903 struct nix_txsch_free_req {
904 struct mbox_msghdr hdr;
905 #define TXSCHQ_FREE_ALL BIT_ULL(0)
907 /* Scheduler queue level to be freed */
908 uint16_t __io schq_lvl;
909 /* List of scheduler queues to be freed */
913 struct nix_txschq_config {
914 struct mbox_msghdr hdr;
915 uint8_t __io lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
917 #define TXSCHQ_IDX_SHIFT 16
918 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
919 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
920 uint8_t __io num_regs;
921 #define MAX_REGS_PER_MBOX_MSG 20
922 uint64_t __io reg[MAX_REGS_PER_MBOX_MSG];
923 uint64_t __io regval[MAX_REGS_PER_MBOX_MSG];
924 /* All 0's => overwrite with new value */
925 uint64_t __io regval_mask[MAX_REGS_PER_MBOX_MSG];
928 struct nix_vtag_config {
929 struct mbox_msghdr hdr;
930 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
931 uint8_t __io vtag_size;
932 /* cfg_type is '0' for tx vlan cfg
933 * cfg_type is '1' for rx vlan cfg
935 uint8_t __io cfg_type;
937 /* Valid when cfg_type is '0' */
942 /* cfg_vtag0 & cfg_vtag1 fields are valid
943 * when free_vtag0 & free_vtag1 are '0's.
945 /* cfg_vtag0 = 1 to configure vtag0 */
946 uint8_t __io cfg_vtag0 : 1;
947 /* cfg_vtag1 = 1 to configure vtag1 */
948 uint8_t __io cfg_vtag1 : 1;
950 /* vtag0_idx & vtag1_idx are only valid when
951 * both cfg_vtag0 & cfg_vtag1 are '0's,
952 * these fields are used along with free_vtag0
953 * & free_vtag1 to free the nix lf's tx_vlan
956 * Denotes the indices of tx_vtag def registers
957 * that needs to be cleared and freed.
962 /* Free_vtag0 & free_vtag1 fields are valid
963 * when cfg_vtag0 & cfg_vtag1 are '0's.
965 /* Free_vtag0 = 1 clears vtag0 configuration
966 * vtag0_idx denotes the index to be cleared.
968 uint8_t __io free_vtag0 : 1;
969 /* Free_vtag1 = 1 clears vtag1 configuration
970 * vtag1_idx denotes the index to be cleared.
972 uint8_t __io free_vtag1 : 1;
975 /* Valid when cfg_type is '1' */
977 /* Rx vtag type index, valid values are in 0..7 range */
978 uint8_t __io vtag_type;
980 uint8_t __io strip_vtag : 1;
981 /* Rx vtag capture */
982 uint8_t __io capture_vtag : 1;
987 struct nix_vtag_config_rsp {
988 struct mbox_msghdr hdr;
989 /* Indices of tx_vtag def registers used to configure
990 * tx vtag0 & vtag1 headers, these indices are valid
991 * when nix_vtag_config mbox requested for vtag0 and/
992 * or vtag1 configuration.
998 struct nix_rss_flowkey_cfg {
999 struct mbox_msghdr hdr;
1000 int __io mcam_index; /* MCAM entry index to modify */
1001 uint32_t __io flowkey_cfg; /* Flowkey types selected */
1002 #define FLOW_KEY_TYPE_PORT BIT(0)
1003 #define FLOW_KEY_TYPE_IPV4 BIT(1)
1004 #define FLOW_KEY_TYPE_IPV6 BIT(2)
1005 #define FLOW_KEY_TYPE_TCP BIT(3)
1006 #define FLOW_KEY_TYPE_UDP BIT(4)
1007 #define FLOW_KEY_TYPE_SCTP BIT(5)
1008 #define FLOW_KEY_TYPE_NVGRE BIT(6)
1009 #define FLOW_KEY_TYPE_VXLAN BIT(7)
1010 #define FLOW_KEY_TYPE_GENEVE BIT(8)
1011 #define FLOW_KEY_TYPE_ETH_DMAC BIT(9)
1012 #define FLOW_KEY_TYPE_IPV6_EXT BIT(10)
1013 #define FLOW_KEY_TYPE_GTPU BIT(11)
1014 #define FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
1015 #define FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
1016 #define FLOW_KEY_TYPE_INNR_TCP BIT(14)
1017 #define FLOW_KEY_TYPE_INNR_UDP BIT(15)
1018 #define FLOW_KEY_TYPE_INNR_SCTP BIT(16)
1019 #define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
1020 #define FLOW_KEY_TYPE_CH_LEN_90B BIT(18)
1021 #define FLOW_KEY_TYPE_CUSTOM0 BIT(19)
1022 #define FLOW_KEY_TYPE_VLAN BIT(20)
1023 #define FLOW_KEY_TYPE_L4_DST BIT(28)
1024 #define FLOW_KEY_TYPE_L4_SRC BIT(29)
1025 #define FLOW_KEY_TYPE_L3_DST BIT(30)
1026 #define FLOW_KEY_TYPE_L3_SRC BIT(31)
1027 uint8_t __io group; /* RSS context or group */
1030 struct nix_rss_flowkey_cfg_rsp {
1031 struct mbox_msghdr hdr;
1032 uint8_t __io alg_idx; /* Selected algo index */
1035 struct nix_set_mac_addr {
1036 struct mbox_msghdr hdr;
1037 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
1040 struct nix_get_mac_addr_rsp {
1041 struct mbox_msghdr hdr;
1042 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
1045 struct nix_mark_format_cfg {
1046 struct mbox_msghdr hdr;
1047 uint8_t __io offset;
1048 uint8_t __io y_mask;
1050 uint8_t __io r_mask;
1054 struct nix_mark_format_cfg_rsp {
1055 struct mbox_msghdr hdr;
1056 uint8_t __io mark_format_idx;
1059 struct nix_lso_format_cfg {
1060 struct mbox_msghdr hdr;
1061 uint64_t __io field_mask;
1062 uint64_t __io fields[NIX_LSO_FIELD_MAX];
1065 struct nix_lso_format_cfg_rsp {
1066 struct mbox_msghdr hdr;
1067 uint8_t __io lso_format_idx;
1070 struct nix_rx_mode {
1071 struct mbox_msghdr hdr;
1072 #define NIX_RX_MODE_UCAST BIT(0)
1073 #define NIX_RX_MODE_PROMISC BIT(1)
1074 #define NIX_RX_MODE_ALLMULTI BIT(2)
1079 struct mbox_msghdr hdr;
1080 #define NIX_RX_OL3_VERIFY BIT(0)
1081 #define NIX_RX_OL4_VERIFY BIT(1)
1082 #define NIX_RX_DROP_RE BIT(2)
1083 uint8_t __io len_verify; /* Outer L3/L4 len check */
1084 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1085 uint8_t __io csum_verify; /* Outer L4 checksum verification */
1088 struct nix_frs_cfg {
1089 struct mbox_msghdr hdr;
1090 uint8_t __io update_smq; /* Update SMQ's min/max lens */
1091 uint8_t __io update_minlen; /* Set minlen also */
1092 uint8_t __io sdp_link; /* Set SDP RX link */
1093 uint16_t __io maxlen;
1094 uint16_t __io minlen;
1097 struct nix_set_vlan_tpid {
1098 struct mbox_msghdr hdr;
1099 #define NIX_VLAN_TYPE_INNER 0
1100 #define NIX_VLAN_TYPE_OUTER 1
1101 uint8_t __io vlan_type;
1105 struct nix_bp_cfg_req {
1106 struct mbox_msghdr hdr;
1107 uint16_t __io chan_base; /* Starting channel number */
1108 uint8_t __io chan_cnt; /* Number of channels */
1109 uint8_t __io bpid_per_chan;
1110 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1111 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1114 /* PF can be mapped to either CGX or LBK interface,
1115 * so maximum 64 channels are possible.
1117 #define NIX_MAX_CHAN 64
1118 struct nix_bp_cfg_rsp {
1119 struct mbox_msghdr hdr;
1120 /* Channel and bpid mapping */
1121 uint16_t __io chan_bpid[NIX_MAX_CHAN];
1122 /* Number of channel for which bpids are assigned */
1123 uint8_t __io chan_cnt;
1126 /* Global NIX inline IPSec configuration */
1127 struct nix_inline_ipsec_cfg {
1128 struct mbox_msghdr hdr;
1129 uint32_t __io cpt_credit;
1132 uint8_t __io opcode;
1135 uint16_t __io cpt_pf_func;
1136 uint8_t __io cpt_slot;
1138 uint8_t __io enable;
1141 /* Per NIX LF inline IPSec configuration */
1142 struct nix_inline_ipsec_lf_cfg {
1143 struct mbox_msghdr hdr;
1144 uint64_t __io sa_base_addr;
1146 uint32_t __io tag_const;
1147 uint16_t __io lenm1_max;
1148 uint8_t __io sa_pow2_size;
1152 uint32_t __io sa_idx_max;
1153 uint8_t __io sa_idx_w;
1155 uint8_t __io enable;
1158 struct nix_hw_info {
1159 struct mbox_msghdr hdr;
1160 uint16_t __io vwqe_delay;
1161 uint16_t __io rsvd[15];
1164 struct nix_bandprof_alloc_req {
1165 struct mbox_msghdr hdr;
1166 /* Count of profiles needed per layer */
1167 uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX];
1170 struct nix_bandprof_alloc_rsp {
1171 struct mbox_msghdr hdr;
1172 uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX];
1174 #define BANDPROF_PER_PFFUNC 64
1175 uint16_t __io prof_idx[NIX_RX_BAND_PROF_LAYER_MAX][BANDPROF_PER_PFFUNC];
1178 struct nix_bandprof_free_req {
1179 struct mbox_msghdr hdr;
1180 uint8_t __io free_all;
1181 uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX];
1182 uint16_t __io prof_idx[NIX_RX_BAND_PROF_LAYER_MAX][BANDPROF_PER_PFFUNC];
1185 struct nix_bandprof_get_hwinfo_rsp {
1186 struct mbox_msghdr hdr;
1187 uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX];
1188 uint32_t __io policer_timeunit;
1191 /* SSO mailbox error codes
1194 enum sso_af_status {
1195 SSO_AF_ERR_PARAM = -501,
1196 SSO_AF_ERR_LF_INVALID = -502,
1197 SSO_AF_ERR_AF_LF_ALLOC = -503,
1198 SSO_AF_ERR_GRP_EBUSY = -504,
1199 SSO_AF_INVAL_NPA_PF_FUNC = -505,
1202 struct sso_lf_alloc_req {
1203 struct mbox_msghdr hdr;
1205 uint16_t __io hwgrps;
1208 struct sso_lf_alloc_rsp {
1209 struct mbox_msghdr hdr;
1210 uint32_t __io xaq_buf_size;
1211 uint32_t __io xaq_wq_entries;
1212 uint32_t __io in_unit_entries;
1213 uint16_t __io hwgrps;
1216 struct sso_lf_free_req {
1217 struct mbox_msghdr hdr;
1219 uint16_t __io hwgrps;
1222 /* SSOW mailbox error codes
1225 enum ssow_af_status {
1226 SSOW_AF_ERR_PARAM = -601,
1227 SSOW_AF_ERR_LF_INVALID = -602,
1228 SSOW_AF_ERR_AF_LF_ALLOC = -603,
1231 struct ssow_lf_alloc_req {
1232 struct mbox_msghdr hdr;
1237 struct ssow_lf_free_req {
1238 struct mbox_msghdr hdr;
1243 struct sso_hw_setconfig {
1244 struct mbox_msghdr hdr;
1245 uint32_t __io npa_aura_id;
1246 uint16_t __io npa_pf_func;
1247 uint16_t __io hwgrps;
1250 struct sso_hw_xaq_release {
1251 struct mbox_msghdr hdr;
1252 uint16_t __io hwgrps;
1255 struct sso_info_req {
1256 struct mbox_msghdr hdr;
1263 struct sso_grp_priority {
1264 struct mbox_msghdr hdr;
1266 uint8_t __io priority;
1267 uint8_t __io affinity;
1268 uint8_t __io weight;
1271 struct sso_grp_qos_cfg {
1272 struct mbox_msghdr hdr;
1274 uint32_t __io xaq_limit;
1275 uint16_t __io taq_thr;
1276 uint16_t __io iaq_thr;
1279 struct sso_grp_stats {
1280 struct mbox_msghdr hdr;
1282 uint64_t __io ws_pc;
1283 uint64_t __io ext_pc;
1284 uint64_t __io wa_pc;
1285 uint64_t __io ts_pc;
1286 uint64_t __io ds_pc;
1287 uint64_t __io dq_pc;
1288 uint64_t __io aw_status;
1289 uint64_t __io page_cnt;
1292 struct sso_hws_stats {
1293 struct mbox_msghdr hdr;
1295 uint64_t __io arbitration;
1298 /* CPT mailbox error codes
1301 enum cpt_af_status {
1302 CPT_AF_ERR_PARAM = -901,
1303 CPT_AF_ERR_GRP_INVALID = -902,
1304 CPT_AF_ERR_LF_INVALID = -903,
1305 CPT_AF_ERR_ACCESS_DENIED = -904,
1306 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1307 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1308 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1309 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1312 /* CPT mbox message formats */
1314 struct cpt_rd_wr_reg_msg {
1315 struct mbox_msghdr hdr;
1316 uint64_t __io reg_offset;
1317 uint64_t __io *ret_val;
1319 uint8_t __io is_write;
1322 struct cpt_set_crypto_grp_req_msg {
1323 struct mbox_msghdr hdr;
1324 uint8_t __io crypto_eng_grp;
1327 struct cpt_lf_alloc_req_msg {
1328 struct mbox_msghdr hdr;
1329 uint16_t __io nix_pf_func;
1330 uint16_t __io sso_pf_func;
1331 uint16_t __io eng_grpmsk;
1332 uint8_t __io blkaddr;
1335 #define CPT_INLINE_INBOUND 0
1336 #define CPT_INLINE_OUTBOUND 1
1338 struct cpt_inline_ipsec_cfg_msg {
1339 struct mbox_msghdr hdr;
1340 uint8_t __io enable;
1343 uint8_t __io sso_pf_func_ovrd;
1344 uint16_t __io sso_pf_func; /* Inbound path SSO_PF_FUNC */
1345 uint16_t __io nix_pf_func; /* Outbound path NIX_PF_FUNC */
1348 struct cpt_sts_req {
1349 struct mbox_msghdr hdr;
1350 uint8_t __io blkaddr;
1353 struct cpt_sts_rsp {
1354 struct mbox_msghdr hdr;
1355 uint64_t __io inst_req_pc;
1356 uint64_t __io inst_lat_pc;
1357 uint64_t __io rd_req_pc;
1358 uint64_t __io rd_lat_pc;
1359 uint64_t __io rd_uc_pc;
1360 uint64_t __io active_cycles_pc;
1361 uint64_t __io ctx_mis_pc;
1362 uint64_t __io ctx_hit_pc;
1363 uint64_t __io ctx_aop_pc;
1364 uint64_t __io ctx_aop_lat_pc;
1365 uint64_t __io ctx_ifetch_pc;
1366 uint64_t __io ctx_ifetch_lat_pc;
1367 uint64_t __io ctx_ffetch_pc;
1368 uint64_t __io ctx_ffetch_lat_pc;
1369 uint64_t __io ctx_wback_pc;
1370 uint64_t __io ctx_wback_lat_pc;
1371 uint64_t __io ctx_psh_pc;
1372 uint64_t __io ctx_psh_lat_pc;
1373 uint64_t __io ctx_err;
1374 uint64_t __io ctx_enc_id;
1375 uint64_t __io ctx_flush_timer;
1376 uint64_t __io rxc_time;
1377 uint64_t __io rxc_time_cfg;
1378 uint64_t __io rxc_active_sts;
1379 uint64_t __io rxc_zombie_sts;
1380 uint64_t __io busy_sts_ae;
1381 uint64_t __io free_sts_ae;
1382 uint64_t __io busy_sts_se;
1383 uint64_t __io free_sts_se;
1384 uint64_t __io busy_sts_ie;
1385 uint64_t __io free_sts_ie;
1386 uint64_t __io exe_err_info;
1387 uint64_t __io cptclk_cnt;
1389 uint64_t __io rxc_dfrg;
1390 uint64_t __io x2p_link_cfg0;
1391 uint64_t __io x2p_link_cfg1;
1394 struct cpt_rxc_time_cfg_req {
1395 struct mbox_msghdr hdr;
1398 uint16_t zombie_thres;
1399 uint16_t zombie_limit;
1400 uint16_t active_thres;
1401 uint16_t active_limit;
1404 struct cpt_rx_inline_lf_cfg_msg {
1405 struct mbox_msghdr hdr;
1406 uint16_t __io sso_pf_func;
1407 uint16_t __io param1;
1408 uint16_t __io param2;
1409 uint16_t __io reserved;
1413 CPT_ENG_TYPE_AE = 1,
1414 CPT_ENG_TYPE_SE = 2,
1415 CPT_ENG_TYPE_IE = 3,
1419 /* CPT HW capabilities */
1420 union cpt_eng_caps {
1423 uint64_t __io reserved_0_4 : 5;
1424 uint64_t __io mul : 1;
1425 uint64_t __io sha1_sha2 : 1;
1426 uint64_t __io chacha20 : 1;
1427 uint64_t __io zuc_snow3g : 1;
1428 uint64_t __io sha3 : 1;
1429 uint64_t __io aes : 1;
1430 uint64_t __io kasumi : 1;
1431 uint64_t __io des : 1;
1432 uint64_t __io crc : 1;
1433 uint64_t __io reserved_14_63 : 50;
1437 struct cpt_caps_rsp_msg {
1438 struct mbox_msghdr hdr;
1439 uint16_t __io cpt_pf_drv_version;
1440 uint8_t __io cpt_revision;
1441 union cpt_eng_caps eng_caps[CPT_MAX_ENG_TYPES];
1444 struct cpt_eng_grp_req {
1445 struct mbox_msghdr hdr;
1446 uint8_t __io eng_type;
1449 struct cpt_eng_grp_rsp {
1450 struct mbox_msghdr hdr;
1451 uint8_t __io eng_type;
1452 uint8_t __io eng_grp_num;
1455 /* NPC mbox message structs */
1457 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1458 #define NPC_MCAM_INVALID_MAP 0xFFFF
1460 /* NPC mailbox error codes
1463 enum npc_af_status {
1464 NPC_MCAM_INVALID_REQ = -701,
1465 NPC_MCAM_ALLOC_DENIED = -702,
1466 NPC_MCAM_ALLOC_FAILED = -703,
1467 NPC_MCAM_PERM_DENIED = -704,
1468 NPC_AF_ERR_HIGIG_CONFIG_FAIL = -705,
1471 struct npc_mcam_alloc_entry_req {
1472 struct mbox_msghdr hdr;
1473 #define NPC_MAX_NONCONTIG_ENTRIES 256
1474 uint8_t __io contig; /* Contiguous entries ? */
1475 #define NPC_MCAM_ANY_PRIO 0
1476 #define NPC_MCAM_LOWER_PRIO 1
1477 #define NPC_MCAM_HIGHER_PRIO 2
1478 uint8_t __io priority; /* Lower or higher w.r.t ref_entry */
1479 uint16_t __io ref_entry;
1480 uint16_t __io count; /* Number of entries requested */
1483 struct npc_mcam_alloc_entry_rsp {
1484 struct mbox_msghdr hdr;
1485 /* Entry alloc'ed or start index if contiguous.
1486 * Invalid in case of non-contiguous.
1488 uint16_t __io entry;
1489 uint16_t __io count; /* Number of entries allocated */
1490 uint16_t __io free_count; /* Number of entries available */
1491 uint16_t __io entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1494 struct npc_mcam_free_entry_req {
1495 struct mbox_msghdr hdr;
1496 uint16_t __io entry; /* Entry index to be freed */
1497 uint8_t __io all; /* Free all entries alloc'ed to this PFVF */
1501 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max key width */
1502 uint64_t __io kw[NPC_MAX_KWS_IN_KEY];
1503 uint64_t __io kw_mask[NPC_MAX_KWS_IN_KEY];
1504 uint64_t __io action;
1505 uint64_t __io vtag_action;
1508 struct npc_mcam_write_entry_req {
1509 struct mbox_msghdr hdr;
1510 struct mcam_entry entry_data;
1511 uint16_t __io entry; /* MCAM entry to write this match key */
1512 uint16_t __io cntr; /* Counter for this MCAM entry */
1513 uint8_t __io intf; /* Rx or Tx interface */
1514 uint8_t __io enable_entry; /* Enable this MCAM entry ? */
1515 uint8_t __io set_cntr; /* Set counter for this entry ? */
1518 /* Enable/Disable a given entry */
1519 struct npc_mcam_ena_dis_entry_req {
1520 struct mbox_msghdr hdr;
1521 uint16_t __io entry;
1524 struct npc_mcam_shift_entry_req {
1525 struct mbox_msghdr hdr;
1526 #define NPC_MCAM_MAX_SHIFTS 64
1527 uint16_t __io curr_entry[NPC_MCAM_MAX_SHIFTS];
1528 uint16_t __io new_entry[NPC_MCAM_MAX_SHIFTS];
1529 uint16_t __io shift_count; /* Number of entries to shift */
1532 struct npc_mcam_shift_entry_rsp {
1533 struct mbox_msghdr hdr;
1534 /* Index in 'curr_entry', not entry itself */
1535 uint16_t __io failed_entry_idx;
1538 struct npc_mcam_alloc_counter_req {
1539 struct mbox_msghdr hdr;
1540 uint8_t __io contig; /* Contiguous counters ? */
1541 #define NPC_MAX_NONCONTIG_COUNTERS 64
1542 uint16_t __io count; /* Number of counters requested */
1545 struct npc_mcam_alloc_counter_rsp {
1546 struct mbox_msghdr hdr;
1547 /* Counter alloc'ed or start idx if contiguous.
1548 * Invalid in case of non-contiguous.
1551 uint16_t __io count; /* Number of counters allocated */
1552 uint16_t __io cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1555 struct npc_mcam_oper_counter_req {
1556 struct mbox_msghdr hdr;
1557 uint16_t __io cntr; /* Free a counter or clear/fetch it's stats */
1560 struct npc_mcam_oper_counter_rsp {
1561 struct mbox_msghdr hdr;
1562 /* valid only while fetching counter's stats */
1566 struct npc_mcam_unmap_counter_req {
1567 struct mbox_msghdr hdr;
1569 uint16_t __io entry; /* Entry and counter to be unmapped */
1570 uint8_t __io all; /* Unmap all entries using this counter ? */
1573 struct npc_mcam_alloc_and_write_entry_req {
1574 struct mbox_msghdr hdr;
1575 struct mcam_entry entry_data;
1576 uint16_t __io ref_entry;
1577 uint8_t __io priority; /* Lower or higher w.r.t ref_entry */
1578 uint8_t __io intf; /* Rx or Tx interface */
1579 uint8_t __io enable_entry; /* Enable this MCAM entry ? */
1580 uint8_t __io alloc_cntr; /* Allocate counter and map ? */
1583 struct npc_mcam_alloc_and_write_entry_rsp {
1584 struct mbox_msghdr hdr;
1585 uint16_t __io entry;
1589 struct npc_get_kex_cfg_rsp {
1590 struct mbox_msghdr hdr;
1591 uint64_t __io rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1592 uint64_t __io tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1593 #define NPC_MAX_INTF 2
1594 #define NPC_MAX_LID 8
1595 #define NPC_MAX_LT 16
1596 #define NPC_MAX_LD 2
1597 #define NPC_MAX_LFL 16
1598 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1599 uint64_t __io kex_ld_flags[NPC_MAX_LD];
1600 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1601 uint64_t __io intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT]
1603 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1604 uint64_t __io intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1605 #define MKEX_NAME_LEN 128
1606 uint8_t __io mkex_pfl_name[MKEX_NAME_LEN];
1609 enum header_fields {
1624 NPC_HEADER_FIELDS_MAX,
1628 unsigned char __io dmac[6];
1629 unsigned char __io smac[6];
1630 uint16_t __io etype;
1631 uint16_t __io vlan_etype;
1632 uint16_t __io vlan_tci;
1634 uint32_t __io ip4src;
1635 uint32_t __io ip6src[4];
1638 uint32_t __io ip4dst;
1639 uint32_t __io ip6dst[4];
1642 uint8_t __io ip_ver;
1643 uint8_t __io ip_proto;
1645 uint16_t __io sport;
1646 uint16_t __io dport;
1649 struct npc_install_flow_req {
1650 struct mbox_msghdr hdr;
1651 struct flow_msg packet;
1652 struct flow_msg mask;
1653 uint64_t __io features;
1654 uint16_t __io entry;
1655 uint16_t __io channel;
1657 uint8_t __io set_cntr;
1658 uint8_t __io default_rule;
1659 /* Overwrite(0) or append(1) flow to default rule? */
1660 uint8_t __io append;
1663 uint32_t __io index;
1664 uint16_t __io match_id;
1665 uint8_t __io flow_key_alg;
1668 uint8_t __io vtag0_type;
1669 uint8_t __io vtag0_valid;
1670 uint8_t __io vtag1_type;
1671 uint8_t __io vtag1_valid;
1673 /* vtag tx action */
1674 uint16_t __io vtag0_def;
1675 uint8_t __io vtag0_op;
1676 uint16_t __io vtag1_def;
1677 uint8_t __io vtag1_op;
1680 struct npc_install_flow_rsp {
1681 struct mbox_msghdr hdr;
1682 /* Negative if no counter else counter number */
1686 struct npc_delete_flow_req {
1687 struct mbox_msghdr hdr;
1688 uint16_t __io entry;
1689 uint16_t __io start; /*Disable range of entries */
1691 uint8_t __io all; /* PF + VFs */
1694 struct npc_mcam_read_entry_req {
1695 struct mbox_msghdr hdr;
1696 /* MCAM entry to read */
1697 uint16_t __io entry;
1700 struct npc_mcam_read_entry_rsp {
1701 struct mbox_msghdr hdr;
1702 struct mcam_entry entry_data;
1704 uint8_t __io enable;
1707 struct npc_mcam_read_base_rule_rsp {
1708 struct mbox_msghdr hdr;
1709 struct mcam_entry entry_data;
1712 struct npc_mcam_get_stats_req {
1713 struct mbox_msghdr hdr;
1714 uint16_t __io entry; /* mcam entry */
1717 struct npc_mcam_get_stats_rsp {
1718 struct mbox_msghdr hdr;
1719 uint64_t __io stat; /* counter stats */
1720 uint8_t __io stat_ena; /* enabled */
1723 /* TIM mailbox error codes
1726 enum tim_af_status {
1727 TIM_AF_NO_RINGS_LEFT = -801,
1728 TIM_AF_INVALID_NPA_PF_FUNC = -802,
1729 TIM_AF_INVALID_SSO_PF_FUNC = -803,
1730 TIM_AF_RING_STILL_RUNNING = -804,
1731 TIM_AF_LF_INVALID = -805,
1732 TIM_AF_CSIZE_NOT_ALIGNED = -806,
1733 TIM_AF_CSIZE_TOO_SMALL = -807,
1734 TIM_AF_CSIZE_TOO_BIG = -808,
1735 TIM_AF_INTERVAL_TOO_SMALL = -809,
1736 TIM_AF_INVALID_BIG_ENDIAN_VALUE = -810,
1737 TIM_AF_INVALID_CLOCK_SOURCE = -811,
1738 TIM_AF_GPIO_CLK_SRC_NOT_ENABLED = -812,
1739 TIM_AF_INVALID_BSIZE = -813,
1740 TIM_AF_INVALID_ENABLE_PERIODIC = -814,
1741 TIM_AF_INVALID_ENABLE_DONTFREE = -815,
1742 TIM_AF_ENA_DONTFRE_NSET_PERIODIC = -816,
1743 TIM_AF_RING_ALREADY_DISABLED = -817,
1747 TIM_CLK_SRCS_TENNS = 0,
1748 TIM_CLK_SRCS_GPIO = 1,
1749 TIM_CLK_SRCS_GTI = 2,
1750 TIM_CLK_SRCS_PTP = 3,
1751 TIM_CLK_SRSC_INVALID,
1754 enum tim_gpio_edge {
1755 TIM_GPIO_NO_EDGE = 0,
1756 TIM_GPIO_LTOH_TRANS = 1,
1757 TIM_GPIO_HTOL_TRANS = 2,
1758 TIM_GPIO_BOTH_TRANS = 3,
1763 PTP_OP_ADJFINE = 0, /* adjfine(req.scaled_ppm); */
1764 PTP_OP_GET_CLOCK = 1, /* rsp.clk = get_clock() */
1768 struct mbox_msghdr hdr;
1770 int64_t __io scaled_ppm;
1771 uint8_t __io is_pmu;
1775 struct mbox_msghdr hdr;
1780 struct get_hw_cap_rsp {
1781 struct mbox_msghdr hdr;
1782 /* Schq mapping fixed or flexible */
1783 uint8_t __io nix_fixed_txschq_mapping;
1784 uint8_t __io nix_shaping; /* Is shaping and coloring supported */
1787 struct ndc_sync_op {
1788 struct mbox_msghdr hdr;
1789 uint8_t __io nix_lf_tx_sync;
1790 uint8_t __io nix_lf_rx_sync;
1791 uint8_t __io npa_lf_sync;
1794 struct tim_lf_alloc_req {
1795 struct mbox_msghdr hdr;
1797 uint16_t __io npa_pf_func;
1798 uint16_t __io sso_pf_func;
1801 struct tim_ring_req {
1802 struct mbox_msghdr hdr;
1806 struct tim_config_req {
1807 struct mbox_msghdr hdr;
1809 uint8_t __io bigendian;
1810 uint8_t __io clocksource;
1811 uint8_t __io enableperiodic;
1812 uint8_t __io enabledontfreebuffer;
1813 uint32_t __io bucketsize;
1814 uint32_t __io chunksize;
1815 uint32_t __io interval;
1816 uint8_t __io gpioedge;
1817 uint8_t __io rsvd[7];
1818 uint64_t __io intervalns;
1819 uint64_t __io clockfreq;
1822 struct tim_lf_alloc_rsp {
1823 struct mbox_msghdr hdr;
1824 uint64_t __io tenns_clk;
1827 struct tim_enable_rsp {
1828 struct mbox_msghdr hdr;
1829 uint64_t __io timestarted;
1830 uint32_t __io currentbucket;
1833 struct tim_intvl_req {
1834 struct mbox_msghdr hdr;
1835 uint8_t __io clocksource;
1836 uint64_t __io clockfreq;
1839 struct tim_intvl_rsp {
1840 struct mbox_msghdr hdr;
1841 uint64_t __io intvl_cyc;
1842 uint64_t __io intvl_ns;
1845 struct sdp_node_info {
1846 /* Node to which this PF belons to */
1847 uint8_t __io node_id;
1848 uint8_t __io max_vfs;
1849 uint8_t __io num_pf_rings;
1850 uint8_t __io pf_srn;
1851 #define SDP_MAX_VFS 128
1852 uint8_t __io vf_rings[SDP_MAX_VFS];
1855 struct sdp_chan_info_msg {
1856 struct mbox_msghdr hdr;
1857 struct sdp_node_info info;
1860 #endif /* __ROC_MBOX_H__ */