1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
12 /* Device memory does not support unaligned access, instruct compiler to
13 * not optimize the memory access when working with mailbox memory.
17 /* Header which precedes all mbox messages */
19 uint64_t __io msg_size; /* Total msgs size embedded */
20 uint16_t __io num_msgs; /* No of msgs embedded */
23 /* Header which precedes every msg and is also part of it */
25 uint16_t __io pcifunc; /* Who's sending this msg */
26 uint16_t __io id; /* Mbox message ID */
27 #define MBOX_REQ_SIG (0xdead)
28 #define MBOX_RSP_SIG (0xbeef)
29 /* Signature, for validating corrupted msgs */
31 #define MBOX_VERSION (0x000b)
32 /* Version of msg's structure for this ID */
34 /* Offset of next msg within mailbox region */
35 uint16_t __io next_msgoff;
36 int __io rc; /* Msg processed response code */
39 /* Mailbox message types */
40 #define MBOX_MSG_MASK 0xFFFF
41 #define MBOX_MSG_INVALID 0xFFFE
42 #define MBOX_MSG_MAX 0xFFFF
44 #define MBOX_MESSAGES \
45 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
46 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
47 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach_req, msg_rsp) \
48 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach_req, msg_rsp) \
49 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
50 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
51 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
52 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
53 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
54 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
55 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
57 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
58 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
59 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
60 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
61 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
62 cgx_mac_addr_set_or_get) \
63 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
64 cgx_mac_addr_set_or_get) \
65 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
66 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
67 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
68 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
69 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, \
71 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
72 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
73 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
74 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
75 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
77 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
78 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
79 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
80 cgx_mac_addr_add_rsp) \
81 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
83 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
84 cgx_max_dmac_entries_get_rsp) \
85 M(CGX_SET_LINK_STATE, 0x214, cgx_set_link_state, \
86 cgx_set_link_state_msg, msg_rsp) \
87 M(CGX_GET_PHY_MOD_TYPE, 0x215, cgx_get_phy_mod_type, msg_req, \
89 M(CGX_SET_PHY_MOD_TYPE, 0x216, cgx_set_phy_mod_type, cgx_phy_mod_type, \
91 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
92 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req, \
93 cgx_set_link_mode_rsp) \
94 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, \
96 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \
97 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
98 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
99 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, npa_lf_alloc_req, \
101 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
102 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
103 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, \
105 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
106 M(SSO_LF_ALLOC, 0x600, sso_lf_alloc, sso_lf_alloc_req, \
108 M(SSO_LF_FREE, 0x601, sso_lf_free, sso_lf_free_req, msg_rsp) \
109 M(SSOW_LF_ALLOC, 0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp) \
110 M(SSOW_LF_FREE, 0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp) \
111 M(SSO_HW_SETCONFIG, 0x604, sso_hw_setconfig, sso_hw_setconfig, \
113 M(SSO_GRP_SET_PRIORITY, 0x605, sso_grp_set_priority, sso_grp_priority, \
115 M(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req, \
117 M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp) \
118 M(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg, \
120 M(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req, \
122 M(SSO_HWS_GET_STATS, 0x610, sso_hws_get_stats, sso_info_req, \
124 M(SSO_HW_RELEASE_XAQ, 0x611, sso_hw_release_xaq_aura, \
125 sso_hw_xaq_release, msg_rsp) \
126 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
127 M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \
129 M(TIM_LF_FREE, 0x801, tim_lf_free, tim_ring_req, msg_rsp) \
130 M(TIM_CONFIG_RING, 0x802, tim_config_ring, tim_config_req, msg_rsp) \
131 M(TIM_ENABLE_RING, 0x803, tim_enable_ring, tim_ring_req, \
133 M(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \
134 M(TIM_GET_MIN_INTVL, 0x805, tim_get_min_intvl, tim_intvl_req, \
136 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
137 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, msg_rsp) \
138 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
139 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
141 M(CPT_SET_CRYPTO_GRP, 0xA03, cpt_set_crypto_grp, \
142 cpt_set_crypto_grp_req_msg, msg_rsp) \
143 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
144 cpt_inline_ipsec_cfg_msg, msg_rsp) \
145 M(CPT_STATS, 0xA05, cpt_sts_get, cpt_sts_req, cpt_sts_rsp) \
146 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
148 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \
149 M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \
150 cpt_rx_inline_lf_cfg_msg, msg_rsp) \
151 M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg) \
152 M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req, \
154 /* REE mbox IDs (range 0xE00 - 0xFFF) */ \
155 M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, msg_rsp) \
156 M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg, \
158 M(REE_RULE_DB_PROG, 0xE03, ree_rule_db_prog, ree_rule_db_prog_req_msg, \
160 M(REE_RULE_DB_LEN_GET, 0xE04, ree_rule_db_len_get, ree_req_msg, \
161 ree_rule_db_len_rsp_msg) \
162 M(REE_RULE_DB_GET, 0xE05, ree_rule_db_get, ree_rule_db_get_req_msg, \
163 ree_rule_db_get_rsp_msg) \
164 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
165 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, \
167 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
168 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, \
169 npc_mcam_alloc_entry_req, npc_mcam_alloc_entry_rsp) \
170 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
171 npc_mcam_free_entry_req, msg_rsp) \
172 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
173 npc_mcam_write_entry_req, msg_rsp) \
174 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
175 npc_mcam_ena_dis_entry_req, msg_rsp) \
176 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
177 npc_mcam_ena_dis_entry_req, msg_rsp) \
178 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, \
179 npc_mcam_shift_entry_req, npc_mcam_shift_entry_rsp) \
180 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
181 npc_mcam_alloc_counter_req, npc_mcam_alloc_counter_rsp) \
182 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
183 npc_mcam_oper_counter_req, msg_rsp) \
184 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
185 npc_mcam_unmap_counter_req, msg_rsp) \
186 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
187 npc_mcam_oper_counter_req, msg_rsp) \
188 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
189 npc_mcam_oper_counter_req, npc_mcam_oper_counter_rsp) \
190 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, \
191 npc_mcam_alloc_and_write_entry, npc_mcam_alloc_and_write_entry_req, \
192 npc_mcam_alloc_and_write_entry_rsp) \
193 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, msg_req, \
194 npc_get_kex_cfg_rsp) \
195 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, npc_install_flow_req, \
196 npc_install_flow_rsp) \
197 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, npc_delete_flow_req, \
199 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
200 npc_mcam_read_entry_req, npc_mcam_read_entry_rsp) \
201 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, npc_set_pkind, msg_rsp) \
202 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, msg_req, \
203 npc_mcam_read_base_rule_rsp) \
204 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
205 npc_mcam_get_stats_req, npc_mcam_get_stats_rsp) \
206 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
207 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, nix_lf_alloc_req, \
209 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
210 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
211 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, hwctx_disable_req, \
213 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, nix_txsch_alloc_req, \
214 nix_txsch_alloc_rsp) \
215 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
216 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
218 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
219 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
220 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
221 nix_rss_flowkey_cfg, nix_rss_flowkey_cfg_rsp) \
222 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, \
224 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
225 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
226 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
227 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
228 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
229 nix_mark_format_cfg, nix_mark_format_cfg_rsp) \
230 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
231 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, nix_lso_format_cfg, \
232 nix_lso_format_cfg_rsp) \
233 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, \
235 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, \
237 M(NIX_SET_VLAN_TPID, 0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid, \
239 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
241 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
242 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, \
243 nix_get_mac_addr_rsp) \
244 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
245 nix_inline_ipsec_cfg, msg_rsp) \
246 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \
247 nix_inline_ipsec_lf_cfg, msg_rsp) \
248 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
249 nix_cn10k_aq_enq_rsp) \
250 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \
251 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, \
252 nix_bandprof_alloc_req, nix_bandprof_alloc_rsp) \
253 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
255 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
256 nix_bandprof_get_hwinfo_rsp) \
257 M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \
259 M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \
262 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
263 #define MBOX_UP_CGX_MESSAGES \
264 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) \
265 M(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, msg_rsp)
268 #define M(_name, _id, _1, _2, _3) MBOX_MSG_##_name = _id,
269 MBOX_MESSAGES MBOX_UP_CGX_MESSAGES
273 /* Mailbox message formats */
275 #define RVU_DEFAULT_PF_FUNC 0xFFFF
277 /* Generic request msg used for those mbox messages which
278 * don't send any data in the request.
281 struct mbox_msghdr hdr;
284 /* Generic response msg used a ack or response for those mbox
285 * messages which does not have a specific rsp msg format.
288 struct mbox_msghdr hdr;
291 /* RVU mailbox error codes
295 RVU_INVALID_VF_ID = -256,
298 struct ready_msg_rsp {
299 struct mbox_msghdr hdr;
300 uint16_t __io sclk_freq; /* SCLK frequency */
301 uint16_t __io rclk_freq; /* RCLK frequency */
304 enum npc_pkind_type {
305 NPC_RX_CUSTOM_PRE_L2_PKIND = 55ULL,
306 NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
307 NPC_RX_CHLEN24B_PKIND,
308 NPC_RX_CPT_HDR_PKIND,
309 NPC_RX_CHLEN90B_PKIND,
317 /* Struct to set pkind */
318 struct npc_set_pkind {
319 struct mbox_msghdr hdr;
320 #define ROC_PRIV_FLAGS_DEFAULT BIT_ULL(0)
321 #define ROC_PRIV_FLAGS_EDSA BIT_ULL(1)
322 #define ROC_PRIV_FLAGS_HIGIG BIT_ULL(2)
323 #define ROC_PRIV_FLAGS_LEN_90B BIT_ULL(3)
324 #define ROC_PRIV_FLAGS_EXDSA BIT_ULL(4)
325 #define ROC_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5)
326 #define ROC_PRIV_FLAGS_CUSTOM BIT_ULL(63)
328 #define PKIND_TX BIT_ULL(0)
329 #define PKIND_RX BIT_ULL(1)
331 uint8_t __io pkind; /* valid only in case custom flag */
332 uint8_t __io var_len_off;
333 /* Offset of custom header length field.
334 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
336 uint8_t __io var_len_off_mask; /* Mask for length with in offset */
337 uint8_t __io shift_dir;
338 /* Shift direction to get length of the
339 * header at var_len_off
343 /* Structure for requesting resource provisioning.
344 * 'modify' flag to be used when either requesting more
345 * or to detach partial of a certain resource type.
346 * Rest of the fields specify how many of what type to
348 * To request LFs from two blocks of same type this mailbox
349 * can be sent twice as below:
350 * struct rsrc_attach *attach;
351 * .. Allocate memory for message ..
352 * attach->cptlfs = 3; <3 LFs from CPT0>
354 * .. Allocate memory for message ..
355 * attach->modify = 1;
356 * attach->cpt_blkaddr = BLKADDR_CPT1;
357 * attach->cptlfs = 2; <2 LFs from CPT1>
360 struct rsrc_attach_req {
361 struct mbox_msghdr hdr;
362 uint8_t __io modify : 1;
363 uint8_t __io npalf : 1;
364 uint8_t __io nixlf : 1;
367 uint16_t __io timlfs;
368 uint16_t __io cptlfs;
369 uint16_t __io reelfs;
370 /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
371 int __io cpt_blkaddr;
372 /* BLKADDR_REE0/BLKADDR_REE1 or 0 for BLKADDR_REE0 */
373 int __io ree_blkaddr;
376 /* Structure for relinquishing resources.
377 * 'partial' flag to be used when relinquishing all resources
378 * but only of a certain type. If not set, all resources of all
379 * types provisioned to the RVU function will be detached.
381 struct rsrc_detach_req {
382 struct mbox_msghdr hdr;
383 uint8_t __io partial : 1;
384 uint8_t __io npalf : 1;
385 uint8_t __io nixlf : 1;
386 uint8_t __io sso : 1;
387 uint8_t __io ssow : 1;
388 uint8_t __io timlfs : 1;
389 uint8_t __io cptlfs : 1;
390 uint8_t __io reelfs : 1;
393 /* NIX Transmit schedulers */
394 #define NIX_TXSCH_LVL_SMQ 0x0
395 #define NIX_TXSCH_LVL_MDQ 0x0
396 #define NIX_TXSCH_LVL_TL4 0x1
397 #define NIX_TXSCH_LVL_TL3 0x2
398 #define NIX_TXSCH_LVL_TL2 0x3
399 #define NIX_TXSCH_LVL_TL1 0x4
400 #define NIX_TXSCH_LVL_CNT 0x5
403 * Number of resources available to the caller.
404 * In reply to MBOX_MSG_FREE_RSRC_CNT.
406 struct free_rsrcs_rsp {
407 struct mbox_msghdr hdr;
408 uint16_t __io schq[NIX_TXSCH_LVL_CNT];
415 uint16_t __io schq_nix1[NIX_TXSCH_LVL_CNT];
422 #define MSIX_VECTOR_INVALID 0xFFFF
423 #define MAX_RVU_BLKLF_CNT 256
425 struct msix_offset_rsp {
426 struct mbox_msghdr hdr;
427 uint16_t __io npa_msixoff;
428 uint16_t __io nix_msixoff;
431 uint16_t __io timlfs;
432 uint16_t __io cptlfs;
433 uint16_t __io sso_msixoff[MAX_RVU_BLKLF_CNT];
434 uint16_t __io ssow_msixoff[MAX_RVU_BLKLF_CNT];
435 uint16_t __io timlf_msixoff[MAX_RVU_BLKLF_CNT];
436 uint16_t __io cptlf_msixoff[MAX_RVU_BLKLF_CNT];
437 uint16_t __io cpt1_lfs;
438 uint16_t __io ree0_lfs;
439 uint16_t __io ree1_lfs;
440 uint16_t __io cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
441 uint16_t __io ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
442 uint16_t __io ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
445 struct lmtst_tbl_setup_req {
446 struct mbox_msghdr hdr;
448 uint64_t __io dis_sched_early_comp : 1;
449 uint64_t __io sched_ena : 1;
450 uint64_t __io dis_line_pref : 1;
451 uint64_t __io ssow_pf_func : 13;
452 uint16_t __io pcifunc;
453 uint8_t __io use_local_lmt_region;
454 uint64_t __io lmt_iova;
455 uint64_t __io rsvd[2]; /* Future use */
458 /* CGX mbox message formats */
460 struct cgx_stats_rsp {
461 struct mbox_msghdr hdr;
462 #define CGX_RX_STATS_COUNT 13
463 #define CGX_TX_STATS_COUNT 18
464 uint64_t __io rx_stats[CGX_RX_STATS_COUNT];
465 uint64_t __io tx_stats[CGX_TX_STATS_COUNT];
468 struct rpm_stats_rsp {
469 struct mbox_msghdr hdr;
470 #define RPM_RX_STATS_COUNT 43
471 #define RPM_TX_STATS_COUNT 34
472 uint64_t __io rx_stats[RPM_RX_STATS_COUNT];
473 uint64_t __io tx_stats[RPM_TX_STATS_COUNT];
476 struct cgx_fec_stats_rsp {
477 struct mbox_msghdr hdr;
478 uint64_t __io fec_corr_blks;
479 uint64_t __io fec_uncorr_blks;
482 /* Structure for requesting the operation for
483 * setting/getting mac address in the CGX interface
485 struct cgx_mac_addr_set_or_get {
486 struct mbox_msghdr hdr;
487 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
490 /* Structure for requesting the operation to
491 * add DMAC filter entry into CGX interface
493 struct cgx_mac_addr_add_req {
494 struct mbox_msghdr hdr;
495 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
498 /* Structure for response against the operation to
499 * add DMAC filter entry into CGX interface
501 struct cgx_mac_addr_add_rsp {
502 struct mbox_msghdr hdr;
506 /* Structure for requesting the operation to
507 * delete DMAC filter entry from CGX interface
509 struct cgx_mac_addr_del_req {
510 struct mbox_msghdr hdr;
514 /* Structure for response against the operation to
515 * get maximum supported DMAC filter entries
517 struct cgx_max_dmac_entries_get_rsp {
518 struct mbox_msghdr hdr;
519 uint8_t __io max_dmac_filters;
522 struct cgx_link_user_info {
523 uint64_t __io link_up : 1;
524 uint64_t __io full_duplex : 1;
525 uint64_t __io lmac_type_id : 4;
526 uint64_t __io speed : 20; /* speed in Mbps */
527 uint64_t __io an : 1; /* AN supported or not */
528 uint64_t __io fec : 2; /* FEC type if enabled else 0 */
529 uint64_t __io port : 8;
530 #define LMACTYPE_STR_LEN 16
531 char lmac_type[LMACTYPE_STR_LEN];
534 struct cgx_link_info_msg {
535 struct mbox_msghdr hdr;
536 struct cgx_link_user_info link_info;
539 struct cgx_ptp_rx_info_msg {
540 struct mbox_msghdr hdr;
544 struct cgx_pause_frm_cfg {
545 struct mbox_msghdr hdr;
547 /* set = 1 if the request is to config pause frames */
548 /* set = 0 if the request is to fetch pause frames config */
549 uint8_t __io rx_pause;
550 uint8_t __io tx_pause;
553 struct sfp_eeprom_s {
554 #define SFP_EEPROM_SIZE 256
555 uint16_t __io sff_id;
556 uint8_t __io buf[SFP_EEPROM_SIZE];
557 uint64_t __io reserved;
567 uint64_t __io can_change_mod_type : 1;
568 uint64_t __io mod_type : 1;
571 struct cgx_lmac_fwdata_s {
572 uint16_t __io rw_valid;
573 uint64_t __io supported_fec;
574 uint64_t __io supported_an;
575 uint64_t __io supported_link_modes;
576 /* Only applicable if AN is supported */
577 uint64_t __io advertised_fec;
578 uint64_t __io advertised_link_modes;
579 /* Only applicable if SFP/QSFP slot is present */
580 struct sfp_eeprom_s sfp_eeprom;
582 #define LMAC_FWDATA_RESERVED_MEM 1023
583 uint64_t __io reserved[LMAC_FWDATA_RESERVED_MEM];
587 struct mbox_msghdr hdr;
588 struct cgx_lmac_fwdata_s fwdata;
592 struct mbox_msghdr hdr;
596 struct cgx_set_link_state_msg {
597 struct mbox_msghdr hdr;
601 struct cgx_phy_mod_type {
602 struct mbox_msghdr hdr;
606 struct cgx_set_link_mode_args {
614 struct cgx_set_link_mode_req {
615 struct mbox_msghdr hdr;
616 struct cgx_set_link_mode_args args;
619 struct cgx_set_link_mode_rsp {
620 struct mbox_msghdr hdr;
624 /* NPA mbox message formats */
626 /* NPA mailbox error codes
630 NPA_AF_ERR_PARAM = -301,
631 NPA_AF_ERR_AQ_FULL = -302,
632 NPA_AF_ERR_AQ_ENQUEUE = -303,
633 NPA_AF_ERR_AF_LF_INVALID = -304,
634 NPA_AF_ERR_AF_LF_ALLOC = -305,
635 NPA_AF_ERR_LF_RESET = -306,
638 #define NPA_AURA_SZ_0 0
639 #define NPA_AURA_SZ_128 1
640 #define NPA_AURA_SZ_256 2
641 #define NPA_AURA_SZ_512 3
642 #define NPA_AURA_SZ_1K 4
643 #define NPA_AURA_SZ_2K 5
644 #define NPA_AURA_SZ_4K 6
645 #define NPA_AURA_SZ_8K 7
646 #define NPA_AURA_SZ_16K 8
647 #define NPA_AURA_SZ_32K 9
648 #define NPA_AURA_SZ_64K 10
649 #define NPA_AURA_SZ_128K 11
650 #define NPA_AURA_SZ_256K 12
651 #define NPA_AURA_SZ_512K 13
652 #define NPA_AURA_SZ_1M 14
653 #define NPA_AURA_SZ_MAX 15
655 /* For NPA LF context alloc and init */
656 struct npa_lf_alloc_req {
657 struct mbox_msghdr hdr;
659 int __io aura_sz; /* No of auras. See NPA_AURA_SZ_* */
660 uint32_t __io nr_pools; /* No of pools */
661 uint64_t __io way_mask;
664 struct npa_lf_alloc_rsp {
665 struct mbox_msghdr hdr;
666 uint32_t __io stack_pg_ptrs; /* No of ptrs per stack page */
667 uint32_t __io stack_pg_bytes; /* Size of stack page */
668 uint16_t __io qints; /* NPA_AF_CONST::QINTS */
669 uint8_t __io cache_lines; /* Batch Alloc DMA */
672 /* NPA AQ enqueue msg */
673 struct npa_aq_enq_req {
674 struct mbox_msghdr hdr;
675 uint32_t __io aura_id;
679 /* Valid when op == WRITE/INIT and ctype == AURA.
680 * LF fills the pool_id in aura.pool_addr. AF will translate
681 * the pool_id to pool context pointer.
683 __io struct npa_aura_s aura;
684 /* Valid when op == WRITE/INIT and ctype == POOL */
685 __io struct npa_pool_s pool;
687 /* Mask data when op == WRITE (1=write, 0=don't write) */
689 /* Valid when op == WRITE and ctype == AURA */
690 __io struct npa_aura_s aura_mask;
691 /* Valid when op == WRITE and ctype == POOL */
692 __io struct npa_pool_s pool_mask;
696 struct npa_aq_enq_rsp {
697 struct mbox_msghdr hdr;
699 /* Valid when op == READ and ctype == AURA */
700 __io struct npa_aura_s aura;
701 /* Valid when op == READ and ctype == POOL */
702 __io struct npa_pool_s pool;
706 /* Disable all contexts of type 'ctype' */
707 struct hwctx_disable_req {
708 struct mbox_msghdr hdr;
712 /* NIX mbox message formats */
714 /* NIX mailbox error codes
718 NIX_AF_ERR_PARAM = -401,
719 NIX_AF_ERR_AQ_FULL = -402,
720 NIX_AF_ERR_AQ_ENQUEUE = -403,
721 NIX_AF_ERR_AF_LF_INVALID = -404,
722 NIX_AF_ERR_AF_LF_ALLOC = -405,
723 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
724 NIX_AF_ERR_TLX_INVALID = -407,
725 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
726 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
727 NIX_AF_ERR_FRS_INVALID = -410,
728 NIX_AF_ERR_RX_LINK_INVALID = -411,
729 NIX_AF_INVAL_TXSCHQ_CFG = -412,
730 NIX_AF_SMQ_FLUSH_FAILED = -413,
731 NIX_AF_ERR_LF_RESET = -414,
732 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
733 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
734 NIX_AF_ERR_MARK_CFG_FAIL = -417,
735 NIX_AF_ERR_LSO_CFG_FAIL = -418,
736 NIX_AF_INVAL_NPA_PF_FUNC = -419,
737 NIX_AF_INVAL_SSO_PF_FUNC = -420,
738 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
739 NIX_AF_ERR_RX_VTAG_INUSE = -422,
740 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
743 /* For NIX LF context alloc and init */
744 struct nix_lf_alloc_req {
745 struct mbox_msghdr hdr;
747 uint32_t __io rq_cnt; /* No of receive queues */
748 uint32_t __io sq_cnt; /* No of send queues */
749 uint32_t __io cq_cnt; /* No of completion queues */
751 uint16_t __io rss_sz;
752 uint8_t __io rss_grps;
753 uint16_t __io npa_func;
754 /* RVU_DEFAULT_PF_FUNC == default pf_func associated with lf */
755 uint16_t __io sso_func;
756 uint64_t __io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
757 uint64_t __io way_mask;
758 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
759 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1)
763 struct nix_lf_alloc_rsp {
764 struct mbox_msghdr hdr;
765 uint16_t __io sqb_size;
766 uint16_t __io rx_chan_base;
767 uint16_t __io tx_chan_base;
768 uint8_t __io rx_chan_cnt; /* Total number of RX channels */
769 uint8_t __io tx_chan_cnt; /* Total number of TX channels */
770 uint8_t __io lso_tsov4_idx;
771 uint8_t __io lso_tsov6_idx;
772 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
773 uint8_t __io lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
774 uint8_t __io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
775 uint16_t __io cints; /* NIX_AF_CONST2::CINTS */
776 uint16_t __io qints; /* NIX_AF_CONST2::QINTS */
777 uint8_t __io hw_rx_tstamp_en; /*set if rx timestamping enabled */
778 uint8_t __io cgx_links; /* No. of CGX links present in HW */
779 uint8_t __io lbk_links; /* No. of LBK links present in HW */
780 uint8_t __io sdp_links; /* No. of SDP links present in HW */
781 uint8_t tx_link; /* Transmit channel link number */
784 struct nix_lf_free_req {
785 struct mbox_msghdr hdr;
786 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
787 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
791 /* CN10x NIX AQ enqueue msg */
792 struct nix_cn10k_aq_enq_req {
793 struct mbox_msghdr hdr;
798 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
799 __io struct nix_cn10k_rq_ctx_s rq;
800 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
801 __io struct nix_cn10k_sq_ctx_s sq;
802 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
803 __io struct nix_cq_ctx_s cq;
804 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
805 __io struct nix_rsse_s rss;
806 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
807 __io struct nix_rx_mce_s mce;
808 /* Valid when op == WRITE/INIT and
809 * ctype == NIX_AQ_CTYPE_BAND_PROF
811 __io struct nix_band_prof_s prof;
813 /* Mask data when op == WRITE (1=write, 0=don't write) */
815 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
816 __io struct nix_cn10k_rq_ctx_s rq_mask;
817 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
818 __io struct nix_cn10k_sq_ctx_s sq_mask;
819 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
820 __io struct nix_cq_ctx_s cq_mask;
821 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
822 __io struct nix_rsse_s rss_mask;
823 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
824 __io struct nix_rx_mce_s mce_mask;
825 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_BAND_PROF */
826 __io struct nix_band_prof_s prof_mask;
830 struct nix_cn10k_aq_enq_rsp {
831 struct mbox_msghdr hdr;
833 struct nix_cn10k_rq_ctx_s rq;
834 struct nix_cn10k_sq_ctx_s sq;
835 struct nix_cq_ctx_s cq;
836 struct nix_rsse_s rss;
837 struct nix_rx_mce_s mce;
838 struct nix_band_prof_s prof;
842 /* NIX AQ enqueue msg */
843 struct nix_aq_enq_req {
844 struct mbox_msghdr hdr;
849 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
850 __io struct nix_rq_ctx_s rq;
851 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
852 __io struct nix_sq_ctx_s sq;
853 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
854 __io struct nix_cq_ctx_s cq;
855 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
856 __io struct nix_rsse_s rss;
857 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
858 __io struct nix_rx_mce_s mce;
860 /* Mask data when op == WRITE (1=write, 0=don't write) */
862 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
863 __io struct nix_rq_ctx_s rq_mask;
864 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
865 __io struct nix_sq_ctx_s sq_mask;
866 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
867 __io struct nix_cq_ctx_s cq_mask;
868 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
869 __io struct nix_rsse_s rss_mask;
870 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
871 __io struct nix_rx_mce_s mce_mask;
875 struct nix_aq_enq_rsp {
876 struct mbox_msghdr hdr;
878 __io struct nix_rq_ctx_s rq;
879 __io struct nix_sq_ctx_s sq;
880 __io struct nix_cq_ctx_s cq;
881 __io struct nix_rsse_s rss;
882 __io struct nix_rx_mce_s mce;
886 /* Tx scheduler/shaper mailbox messages */
888 #define MAX_TXSCHQ_PER_FUNC 128
890 struct nix_txsch_alloc_req {
891 struct mbox_msghdr hdr;
892 /* Scheduler queue count request at each level */
893 uint16_t __io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
894 uint16_t __io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
897 struct nix_txsch_alloc_rsp {
898 struct mbox_msghdr hdr;
899 /* Scheduler queue count allocated at each level */
900 uint16_t __io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
901 uint16_t __io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
902 /* Scheduler queue list allocated at each level */
903 uint16_t __io schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
904 uint16_t __io schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
905 /* Traffic aggregation scheduler level */
906 uint8_t __io aggr_level;
907 /* Aggregation lvl's RR_PRIO config */
908 uint8_t __io aggr_lvl_rr_prio;
909 /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
910 uint8_t __io link_cfg_lvl;
913 struct nix_txsch_free_req {
914 struct mbox_msghdr hdr;
915 #define TXSCHQ_FREE_ALL BIT_ULL(0)
917 /* Scheduler queue level to be freed */
918 uint16_t __io schq_lvl;
919 /* List of scheduler queues to be freed */
923 struct nix_txschq_config {
924 struct mbox_msghdr hdr;
925 uint8_t __io lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
927 #define TXSCHQ_IDX_SHIFT 16
928 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
929 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
930 uint8_t __io num_regs;
931 #define MAX_REGS_PER_MBOX_MSG 20
932 uint64_t __io reg[MAX_REGS_PER_MBOX_MSG];
933 uint64_t __io regval[MAX_REGS_PER_MBOX_MSG];
934 /* All 0's => overwrite with new value */
935 uint64_t __io regval_mask[MAX_REGS_PER_MBOX_MSG];
938 struct nix_vtag_config {
939 struct mbox_msghdr hdr;
940 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
941 uint8_t __io vtag_size;
942 /* cfg_type is '0' for tx vlan cfg
943 * cfg_type is '1' for rx vlan cfg
945 uint8_t __io cfg_type;
947 /* Valid when cfg_type is '0' */
952 /* cfg_vtag0 & cfg_vtag1 fields are valid
953 * when free_vtag0 & free_vtag1 are '0's.
955 /* cfg_vtag0 = 1 to configure vtag0 */
956 uint8_t __io cfg_vtag0 : 1;
957 /* cfg_vtag1 = 1 to configure vtag1 */
958 uint8_t __io cfg_vtag1 : 1;
960 /* vtag0_idx & vtag1_idx are only valid when
961 * both cfg_vtag0 & cfg_vtag1 are '0's,
962 * these fields are used along with free_vtag0
963 * & free_vtag1 to free the nix lf's tx_vlan
966 * Denotes the indices of tx_vtag def registers
967 * that needs to be cleared and freed.
972 /* Free_vtag0 & free_vtag1 fields are valid
973 * when cfg_vtag0 & cfg_vtag1 are '0's.
975 /* Free_vtag0 = 1 clears vtag0 configuration
976 * vtag0_idx denotes the index to be cleared.
978 uint8_t __io free_vtag0 : 1;
979 /* Free_vtag1 = 1 clears vtag1 configuration
980 * vtag1_idx denotes the index to be cleared.
982 uint8_t __io free_vtag1 : 1;
985 /* Valid when cfg_type is '1' */
987 /* Rx vtag type index, valid values are in 0..7 range */
988 uint8_t __io vtag_type;
990 uint8_t __io strip_vtag : 1;
991 /* Rx vtag capture */
992 uint8_t __io capture_vtag : 1;
997 struct nix_vtag_config_rsp {
998 struct mbox_msghdr hdr;
999 /* Indices of tx_vtag def registers used to configure
1000 * tx vtag0 & vtag1 headers, these indices are valid
1001 * when nix_vtag_config mbox requested for vtag0 and/
1002 * or vtag1 configuration.
1008 struct nix_rss_flowkey_cfg {
1009 struct mbox_msghdr hdr;
1010 int __io mcam_index; /* MCAM entry index to modify */
1011 uint32_t __io flowkey_cfg; /* Flowkey types selected */
1012 #define FLOW_KEY_TYPE_PORT BIT(0)
1013 #define FLOW_KEY_TYPE_IPV4 BIT(1)
1014 #define FLOW_KEY_TYPE_IPV6 BIT(2)
1015 #define FLOW_KEY_TYPE_TCP BIT(3)
1016 #define FLOW_KEY_TYPE_UDP BIT(4)
1017 #define FLOW_KEY_TYPE_SCTP BIT(5)
1018 #define FLOW_KEY_TYPE_NVGRE BIT(6)
1019 #define FLOW_KEY_TYPE_VXLAN BIT(7)
1020 #define FLOW_KEY_TYPE_GENEVE BIT(8)
1021 #define FLOW_KEY_TYPE_ETH_DMAC BIT(9)
1022 #define FLOW_KEY_TYPE_IPV6_EXT BIT(10)
1023 #define FLOW_KEY_TYPE_GTPU BIT(11)
1024 #define FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
1025 #define FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
1026 #define FLOW_KEY_TYPE_INNR_TCP BIT(14)
1027 #define FLOW_KEY_TYPE_INNR_UDP BIT(15)
1028 #define FLOW_KEY_TYPE_INNR_SCTP BIT(16)
1029 #define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
1030 #define FLOW_KEY_TYPE_CH_LEN_90B BIT(18)
1031 #define FLOW_KEY_TYPE_CUSTOM0 BIT(19)
1032 #define FLOW_KEY_TYPE_VLAN BIT(20)
1033 #define FLOW_KEY_TYPE_L4_DST BIT(28)
1034 #define FLOW_KEY_TYPE_L4_SRC BIT(29)
1035 #define FLOW_KEY_TYPE_L3_DST BIT(30)
1036 #define FLOW_KEY_TYPE_L3_SRC BIT(31)
1037 uint8_t __io group; /* RSS context or group */
1040 struct nix_rss_flowkey_cfg_rsp {
1041 struct mbox_msghdr hdr;
1042 uint8_t __io alg_idx; /* Selected algo index */
1045 struct nix_set_mac_addr {
1046 struct mbox_msghdr hdr;
1047 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
1050 struct nix_get_mac_addr_rsp {
1051 struct mbox_msghdr hdr;
1052 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
1055 struct nix_mark_format_cfg {
1056 struct mbox_msghdr hdr;
1057 uint8_t __io offset;
1058 uint8_t __io y_mask;
1060 uint8_t __io r_mask;
1064 struct nix_mark_format_cfg_rsp {
1065 struct mbox_msghdr hdr;
1066 uint8_t __io mark_format_idx;
1069 struct nix_lso_format_cfg {
1070 struct mbox_msghdr hdr;
1071 uint64_t __io field_mask;
1072 uint64_t __io fields[NIX_LSO_FIELD_MAX];
1075 struct nix_lso_format_cfg_rsp {
1076 struct mbox_msghdr hdr;
1077 uint8_t __io lso_format_idx;
1080 struct nix_rx_mode {
1081 struct mbox_msghdr hdr;
1082 #define NIX_RX_MODE_UCAST BIT(0)
1083 #define NIX_RX_MODE_PROMISC BIT(1)
1084 #define NIX_RX_MODE_ALLMULTI BIT(2)
1089 struct mbox_msghdr hdr;
1090 #define NIX_RX_OL3_VERIFY BIT(0)
1091 #define NIX_RX_OL4_VERIFY BIT(1)
1092 #define NIX_RX_DROP_RE BIT(2)
1093 uint8_t __io len_verify; /* Outer L3/L4 len check */
1094 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1095 uint8_t __io csum_verify; /* Outer L4 checksum verification */
1098 struct nix_frs_cfg {
1099 struct mbox_msghdr hdr;
1100 uint8_t __io update_smq; /* Update SMQ's min/max lens */
1101 uint8_t __io update_minlen; /* Set minlen also */
1102 uint8_t __io sdp_link; /* Set SDP RX link */
1103 uint16_t __io maxlen;
1104 uint16_t __io minlen;
1107 struct nix_set_vlan_tpid {
1108 struct mbox_msghdr hdr;
1109 #define NIX_VLAN_TYPE_INNER 0
1110 #define NIX_VLAN_TYPE_OUTER 1
1111 uint8_t __io vlan_type;
1115 struct nix_bp_cfg_req {
1116 struct mbox_msghdr hdr;
1117 uint16_t __io chan_base; /* Starting channel number */
1118 uint8_t __io chan_cnt; /* Number of channels */
1119 uint8_t __io bpid_per_chan;
1120 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1121 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1124 /* PF can be mapped to either CGX or LBK interface,
1125 * so maximum 64 channels are possible.
1127 #define NIX_MAX_CHAN 64
1128 struct nix_bp_cfg_rsp {
1129 struct mbox_msghdr hdr;
1130 /* Channel and bpid mapping */
1131 uint16_t __io chan_bpid[NIX_MAX_CHAN];
1132 /* Number of channel for which bpids are assigned */
1133 uint8_t __io chan_cnt;
1136 /* Global NIX inline IPSec configuration */
1137 struct nix_inline_ipsec_cfg {
1138 struct mbox_msghdr hdr;
1139 uint32_t __io cpt_credit;
1142 uint8_t __io opcode;
1145 uint16_t __io cpt_pf_func;
1146 uint8_t __io cpt_slot;
1148 uint8_t __io enable;
1151 /* Per NIX LF inline IPSec configuration */
1152 struct nix_inline_ipsec_lf_cfg {
1153 struct mbox_msghdr hdr;
1154 uint64_t __io sa_base_addr;
1156 uint32_t __io tag_const;
1157 uint16_t __io lenm1_max;
1158 uint8_t __io sa_pow2_size;
1162 uint32_t __io sa_idx_max;
1163 uint8_t __io sa_idx_w;
1165 uint8_t __io enable;
1168 struct nix_hw_info {
1169 struct mbox_msghdr hdr;
1170 uint16_t __io vwqe_delay;
1171 uint16_t __io rsvd[15];
1174 struct nix_bandprof_alloc_req {
1175 struct mbox_msghdr hdr;
1176 /* Count of profiles needed per layer */
1177 uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX];
1180 struct nix_bandprof_alloc_rsp {
1181 struct mbox_msghdr hdr;
1182 uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX];
1184 #define BANDPROF_PER_PFFUNC 64
1185 uint16_t __io prof_idx[NIX_RX_BAND_PROF_LAYER_MAX][BANDPROF_PER_PFFUNC];
1188 struct nix_bandprof_free_req {
1189 struct mbox_msghdr hdr;
1190 uint8_t __io free_all;
1191 uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX];
1192 uint16_t __io prof_idx[NIX_RX_BAND_PROF_LAYER_MAX][BANDPROF_PER_PFFUNC];
1195 struct nix_bandprof_get_hwinfo_rsp {
1196 struct mbox_msghdr hdr;
1197 uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX];
1198 uint32_t __io policer_timeunit;
1201 /* SSO mailbox error codes
1204 enum sso_af_status {
1205 SSO_AF_ERR_PARAM = -501,
1206 SSO_AF_ERR_LF_INVALID = -502,
1207 SSO_AF_ERR_AF_LF_ALLOC = -503,
1208 SSO_AF_ERR_GRP_EBUSY = -504,
1209 SSO_AF_INVAL_NPA_PF_FUNC = -505,
1212 struct sso_lf_alloc_req {
1213 struct mbox_msghdr hdr;
1215 uint16_t __io hwgrps;
1218 struct sso_lf_alloc_rsp {
1219 struct mbox_msghdr hdr;
1220 uint32_t __io xaq_buf_size;
1221 uint32_t __io xaq_wq_entries;
1222 uint32_t __io in_unit_entries;
1223 uint16_t __io hwgrps;
1226 struct sso_lf_free_req {
1227 struct mbox_msghdr hdr;
1229 uint16_t __io hwgrps;
1232 /* SSOW mailbox error codes
1235 enum ssow_af_status {
1236 SSOW_AF_ERR_PARAM = -601,
1237 SSOW_AF_ERR_LF_INVALID = -602,
1238 SSOW_AF_ERR_AF_LF_ALLOC = -603,
1241 struct ssow_lf_alloc_req {
1242 struct mbox_msghdr hdr;
1247 struct ssow_lf_free_req {
1248 struct mbox_msghdr hdr;
1253 struct sso_hw_setconfig {
1254 struct mbox_msghdr hdr;
1255 uint32_t __io npa_aura_id;
1256 uint16_t __io npa_pf_func;
1257 uint16_t __io hwgrps;
1260 struct sso_hw_xaq_release {
1261 struct mbox_msghdr hdr;
1262 uint16_t __io hwgrps;
1265 struct sso_info_req {
1266 struct mbox_msghdr hdr;
1273 struct sso_grp_priority {
1274 struct mbox_msghdr hdr;
1276 uint8_t __io priority;
1277 uint8_t __io affinity;
1278 uint8_t __io weight;
1281 struct sso_grp_qos_cfg {
1282 struct mbox_msghdr hdr;
1284 uint32_t __io xaq_limit;
1285 uint16_t __io taq_thr;
1286 uint16_t __io iaq_thr;
1289 struct sso_grp_stats {
1290 struct mbox_msghdr hdr;
1292 uint64_t __io ws_pc;
1293 uint64_t __io ext_pc;
1294 uint64_t __io wa_pc;
1295 uint64_t __io ts_pc;
1296 uint64_t __io ds_pc;
1297 uint64_t __io dq_pc;
1298 uint64_t __io aw_status;
1299 uint64_t __io page_cnt;
1302 struct sso_hws_stats {
1303 struct mbox_msghdr hdr;
1305 uint64_t __io arbitration;
1308 /* CPT mailbox error codes
1311 enum cpt_af_status {
1312 CPT_AF_ERR_PARAM = -901,
1313 CPT_AF_ERR_GRP_INVALID = -902,
1314 CPT_AF_ERR_LF_INVALID = -903,
1315 CPT_AF_ERR_ACCESS_DENIED = -904,
1316 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1317 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1318 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1319 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1322 /* CPT mbox message formats */
1324 struct cpt_rd_wr_reg_msg {
1325 struct mbox_msghdr hdr;
1326 uint64_t __io reg_offset;
1327 uint64_t __io *ret_val;
1329 uint8_t __io is_write;
1332 struct cpt_set_crypto_grp_req_msg {
1333 struct mbox_msghdr hdr;
1334 uint8_t __io crypto_eng_grp;
1337 struct cpt_lf_alloc_req_msg {
1338 struct mbox_msghdr hdr;
1339 uint16_t __io nix_pf_func;
1340 uint16_t __io sso_pf_func;
1341 uint16_t __io eng_grpmsk;
1342 uint8_t __io blkaddr;
1345 #define CPT_INLINE_INBOUND 0
1346 #define CPT_INLINE_OUTBOUND 1
1348 struct cpt_inline_ipsec_cfg_msg {
1349 struct mbox_msghdr hdr;
1350 uint8_t __io enable;
1353 uint8_t __io sso_pf_func_ovrd;
1354 uint16_t __io sso_pf_func; /* Inbound path SSO_PF_FUNC */
1355 uint16_t __io nix_pf_func; /* Outbound path NIX_PF_FUNC */
1358 struct cpt_sts_req {
1359 struct mbox_msghdr hdr;
1360 uint8_t __io blkaddr;
1363 struct cpt_sts_rsp {
1364 struct mbox_msghdr hdr;
1365 uint64_t __io inst_req_pc;
1366 uint64_t __io inst_lat_pc;
1367 uint64_t __io rd_req_pc;
1368 uint64_t __io rd_lat_pc;
1369 uint64_t __io rd_uc_pc;
1370 uint64_t __io active_cycles_pc;
1371 uint64_t __io ctx_mis_pc;
1372 uint64_t __io ctx_hit_pc;
1373 uint64_t __io ctx_aop_pc;
1374 uint64_t __io ctx_aop_lat_pc;
1375 uint64_t __io ctx_ifetch_pc;
1376 uint64_t __io ctx_ifetch_lat_pc;
1377 uint64_t __io ctx_ffetch_pc;
1378 uint64_t __io ctx_ffetch_lat_pc;
1379 uint64_t __io ctx_wback_pc;
1380 uint64_t __io ctx_wback_lat_pc;
1381 uint64_t __io ctx_psh_pc;
1382 uint64_t __io ctx_psh_lat_pc;
1383 uint64_t __io ctx_err;
1384 uint64_t __io ctx_enc_id;
1385 uint64_t __io ctx_flush_timer;
1386 uint64_t __io rxc_time;
1387 uint64_t __io rxc_time_cfg;
1388 uint64_t __io rxc_active_sts;
1389 uint64_t __io rxc_zombie_sts;
1390 uint64_t __io busy_sts_ae;
1391 uint64_t __io free_sts_ae;
1392 uint64_t __io busy_sts_se;
1393 uint64_t __io free_sts_se;
1394 uint64_t __io busy_sts_ie;
1395 uint64_t __io free_sts_ie;
1396 uint64_t __io exe_err_info;
1397 uint64_t __io cptclk_cnt;
1399 uint64_t __io rxc_dfrg;
1400 uint64_t __io x2p_link_cfg0;
1401 uint64_t __io x2p_link_cfg1;
1404 struct cpt_rxc_time_cfg_req {
1405 struct mbox_msghdr hdr;
1408 uint16_t zombie_thres;
1409 uint16_t zombie_limit;
1410 uint16_t active_thres;
1411 uint16_t active_limit;
1414 struct cpt_rx_inline_lf_cfg_msg {
1415 struct mbox_msghdr hdr;
1416 uint16_t __io sso_pf_func;
1417 uint16_t __io param1;
1418 uint16_t __io param2;
1419 uint16_t __io reserved;
1423 CPT_ENG_TYPE_AE = 1,
1424 CPT_ENG_TYPE_SE = 2,
1425 CPT_ENG_TYPE_IE = 3,
1429 /* CPT HW capabilities */
1430 union cpt_eng_caps {
1433 uint64_t __io reserved_0_4 : 5;
1434 uint64_t __io mul : 1;
1435 uint64_t __io sha1_sha2 : 1;
1436 uint64_t __io chacha20 : 1;
1437 uint64_t __io zuc_snow3g : 1;
1438 uint64_t __io sha3 : 1;
1439 uint64_t __io aes : 1;
1440 uint64_t __io kasumi : 1;
1441 uint64_t __io des : 1;
1442 uint64_t __io crc : 1;
1443 uint64_t __io reserved_14_63 : 50;
1447 struct cpt_caps_rsp_msg {
1448 struct mbox_msghdr hdr;
1449 uint16_t __io cpt_pf_drv_version;
1450 uint8_t __io cpt_revision;
1451 union cpt_eng_caps eng_caps[CPT_MAX_ENG_TYPES];
1454 struct cpt_eng_grp_req {
1455 struct mbox_msghdr hdr;
1456 uint8_t __io eng_type;
1459 struct cpt_eng_grp_rsp {
1460 struct mbox_msghdr hdr;
1461 uint8_t __io eng_type;
1462 uint8_t __io eng_grp_num;
1465 /* REE mailbox error codes
1466 * Range 1001 - 1100.
1468 enum ree_af_status {
1469 REE_AF_ERR_RULE_UNKNOWN_VALUE = -1001,
1470 REE_AF_ERR_LF_NO_MORE_RESOURCES = -1002,
1471 REE_AF_ERR_LF_INVALID = -1003,
1472 REE_AF_ERR_ACCESS_DENIED = -1004,
1473 REE_AF_ERR_RULE_DB_PARTIAL = -1005,
1474 REE_AF_ERR_RULE_DB_EQ_BAD_VALUE = -1006,
1475 REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED = -1007,
1476 REE_AF_ERR_BLOCK_NOT_IMPLEMENTED = -1008,
1477 REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG = -1009,
1478 REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG = -1010,
1479 REE_AF_ERR_Q_IS_GRACEFUL_DIS = -1011,
1480 REE_AF_ERR_Q_NOT_GRACEFUL_DIS = -1012,
1481 REE_AF_ERR_RULE_DB_ALLOC_FAILED = -1013,
1482 REE_AF_ERR_RULE_DB_TOO_BIG = -1014,
1483 REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE = -1015,
1484 REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE = -1016,
1485 REE_AF_ERR_RULE_DB_WRONG_LENGTH = -1017,
1486 REE_AF_ERR_RULE_DB_WRONG_OFFSET = -1018,
1487 REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG = -1019,
1488 REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST = -1020,
1489 REE_AF_ERR_RULE_DBI_ALLOC_FAILED = -1021,
1490 REE_AF_ERR_LF_WRONG_PRIORITY = -1022,
1491 REE_AF_ERR_LF_SIZE_TOO_BIG = -1023,
1494 /* REE mbox message formats */
1496 struct ree_req_msg {
1497 struct mbox_msghdr hdr;
1498 uint32_t __io blkaddr;
1501 struct ree_lf_req_msg {
1502 struct mbox_msghdr hdr;
1503 uint32_t __io blkaddr;
1509 struct ree_rule_db_prog_req_msg {
1510 struct mbox_msghdr hdr;
1511 #define REE_RULE_DB_REQ_BLOCK_SIZE ((64ULL * 1024ULL) >> 1)
1512 uint8_t __io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];
1513 uint32_t __io blkaddr; /* REE0 or REE1 */
1514 uint32_t __io total_len; /* total len of rule db */
1515 uint32_t __io offset; /* offset of current rule db block */
1516 uint16_t __io len; /* length of rule db block */
1517 uint8_t __io is_last; /* is this the last block */
1518 uint8_t __io is_incremental; /* is incremental flow */
1519 uint8_t __io is_dbi; /* is rule db incremental */
1522 struct ree_rule_db_get_req_msg {
1523 struct mbox_msghdr hdr;
1524 uint32_t __io blkaddr;
1525 uint32_t __io offset; /* retrieve db from this offset */
1526 uint8_t __io is_dbi; /* is request for rule db incremental */
1529 struct ree_rd_wr_reg_msg {
1530 struct mbox_msghdr hdr;
1531 uint64_t __io reg_offset;
1532 uint64_t __io *ret_val;
1534 uint32_t __io blkaddr;
1535 uint8_t __io is_write;
1538 struct ree_rule_db_len_rsp_msg {
1539 struct mbox_msghdr hdr;
1540 uint32_t __io blkaddr;
1542 uint32_t __io inc_len;
1545 struct ree_rule_db_get_rsp_msg {
1546 struct mbox_msghdr hdr;
1547 #define REE_RULE_DB_RSP_BLOCK_SIZE (15ULL * 1024ULL)
1548 uint8_t __io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];
1549 uint32_t __io total_len; /* total len of rule db */
1550 uint32_t __io offset; /* offset of current rule db block */
1551 uint16_t __io len; /* length of rule db block */
1552 uint8_t __io is_last; /* is this the last block */
1555 /* NPC mbox message structs */
1557 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1558 #define NPC_MCAM_INVALID_MAP 0xFFFF
1560 /* NPC mailbox error codes
1563 enum npc_af_status {
1564 NPC_MCAM_INVALID_REQ = -701,
1565 NPC_MCAM_ALLOC_DENIED = -702,
1566 NPC_MCAM_ALLOC_FAILED = -703,
1567 NPC_MCAM_PERM_DENIED = -704,
1568 NPC_AF_ERR_HIGIG_CONFIG_FAIL = -705,
1571 struct npc_mcam_alloc_entry_req {
1572 struct mbox_msghdr hdr;
1573 #define NPC_MAX_NONCONTIG_ENTRIES 256
1574 uint8_t __io contig; /* Contiguous entries ? */
1575 #define NPC_MCAM_ANY_PRIO 0
1576 #define NPC_MCAM_LOWER_PRIO 1
1577 #define NPC_MCAM_HIGHER_PRIO 2
1578 uint8_t __io priority; /* Lower or higher w.r.t ref_entry */
1579 uint16_t __io ref_entry;
1580 uint16_t __io count; /* Number of entries requested */
1583 struct npc_mcam_alloc_entry_rsp {
1584 struct mbox_msghdr hdr;
1585 /* Entry alloc'ed or start index if contiguous.
1586 * Invalid in case of non-contiguous.
1588 uint16_t __io entry;
1589 uint16_t __io count; /* Number of entries allocated */
1590 uint16_t __io free_count; /* Number of entries available */
1591 uint16_t __io entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1594 struct npc_mcam_free_entry_req {
1595 struct mbox_msghdr hdr;
1596 uint16_t __io entry; /* Entry index to be freed */
1597 uint8_t __io all; /* Free all entries alloc'ed to this PFVF */
1601 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max key width */
1602 uint64_t __io kw[NPC_MAX_KWS_IN_KEY];
1603 uint64_t __io kw_mask[NPC_MAX_KWS_IN_KEY];
1604 uint64_t __io action;
1605 uint64_t __io vtag_action;
1608 struct npc_mcam_write_entry_req {
1609 struct mbox_msghdr hdr;
1610 struct mcam_entry entry_data;
1611 uint16_t __io entry; /* MCAM entry to write this match key */
1612 uint16_t __io cntr; /* Counter for this MCAM entry */
1613 uint8_t __io intf; /* Rx or Tx interface */
1614 uint8_t __io enable_entry; /* Enable this MCAM entry ? */
1615 uint8_t __io set_cntr; /* Set counter for this entry ? */
1618 /* Enable/Disable a given entry */
1619 struct npc_mcam_ena_dis_entry_req {
1620 struct mbox_msghdr hdr;
1621 uint16_t __io entry;
1624 struct npc_mcam_shift_entry_req {
1625 struct mbox_msghdr hdr;
1626 #define NPC_MCAM_MAX_SHIFTS 64
1627 uint16_t __io curr_entry[NPC_MCAM_MAX_SHIFTS];
1628 uint16_t __io new_entry[NPC_MCAM_MAX_SHIFTS];
1629 uint16_t __io shift_count; /* Number of entries to shift */
1632 struct npc_mcam_shift_entry_rsp {
1633 struct mbox_msghdr hdr;
1634 /* Index in 'curr_entry', not entry itself */
1635 uint16_t __io failed_entry_idx;
1638 struct npc_mcam_alloc_counter_req {
1639 struct mbox_msghdr hdr;
1640 uint8_t __io contig; /* Contiguous counters ? */
1641 #define NPC_MAX_NONCONTIG_COUNTERS 64
1642 uint16_t __io count; /* Number of counters requested */
1645 struct npc_mcam_alloc_counter_rsp {
1646 struct mbox_msghdr hdr;
1647 /* Counter alloc'ed or start idx if contiguous.
1648 * Invalid in case of non-contiguous.
1651 uint16_t __io count; /* Number of counters allocated */
1652 uint16_t __io cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1655 struct npc_mcam_oper_counter_req {
1656 struct mbox_msghdr hdr;
1657 uint16_t __io cntr; /* Free a counter or clear/fetch it's stats */
1660 struct npc_mcam_oper_counter_rsp {
1661 struct mbox_msghdr hdr;
1662 /* valid only while fetching counter's stats */
1666 struct npc_mcam_unmap_counter_req {
1667 struct mbox_msghdr hdr;
1669 uint16_t __io entry; /* Entry and counter to be unmapped */
1670 uint8_t __io all; /* Unmap all entries using this counter ? */
1673 struct npc_mcam_alloc_and_write_entry_req {
1674 struct mbox_msghdr hdr;
1675 struct mcam_entry entry_data;
1676 uint16_t __io ref_entry;
1677 uint8_t __io priority; /* Lower or higher w.r.t ref_entry */
1678 uint8_t __io intf; /* Rx or Tx interface */
1679 uint8_t __io enable_entry; /* Enable this MCAM entry ? */
1680 uint8_t __io alloc_cntr; /* Allocate counter and map ? */
1683 struct npc_mcam_alloc_and_write_entry_rsp {
1684 struct mbox_msghdr hdr;
1685 uint16_t __io entry;
1689 struct npc_get_kex_cfg_rsp {
1690 struct mbox_msghdr hdr;
1691 uint64_t __io rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1692 uint64_t __io tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1693 #define NPC_MAX_INTF 2
1694 #define NPC_MAX_LID 8
1695 #define NPC_MAX_LT 16
1696 #define NPC_MAX_LD 2
1697 #define NPC_MAX_LFL 16
1698 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1699 uint64_t __io kex_ld_flags[NPC_MAX_LD];
1700 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1701 uint64_t __io intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT]
1703 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1704 uint64_t __io intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1705 #define MKEX_NAME_LEN 128
1706 uint8_t __io mkex_pfl_name[MKEX_NAME_LEN];
1709 enum header_fields {
1724 NPC_HEADER_FIELDS_MAX,
1728 unsigned char __io dmac[6];
1729 unsigned char __io smac[6];
1730 uint16_t __io etype;
1731 uint16_t __io vlan_etype;
1732 uint16_t __io vlan_tci;
1734 uint32_t __io ip4src;
1735 uint32_t __io ip6src[4];
1738 uint32_t __io ip4dst;
1739 uint32_t __io ip6dst[4];
1742 uint8_t __io ip_ver;
1743 uint8_t __io ip_proto;
1745 uint16_t __io sport;
1746 uint16_t __io dport;
1749 struct npc_install_flow_req {
1750 struct mbox_msghdr hdr;
1751 struct flow_msg packet;
1752 struct flow_msg mask;
1753 uint64_t __io features;
1754 uint16_t __io entry;
1755 uint16_t __io channel;
1757 uint8_t __io set_cntr;
1758 uint8_t __io default_rule;
1759 /* Overwrite(0) or append(1) flow to default rule? */
1760 uint8_t __io append;
1763 uint32_t __io index;
1764 uint16_t __io match_id;
1765 uint8_t __io flow_key_alg;
1768 uint8_t __io vtag0_type;
1769 uint8_t __io vtag0_valid;
1770 uint8_t __io vtag1_type;
1771 uint8_t __io vtag1_valid;
1773 /* vtag tx action */
1774 uint16_t __io vtag0_def;
1775 uint8_t __io vtag0_op;
1776 uint16_t __io vtag1_def;
1777 uint8_t __io vtag1_op;
1780 struct npc_install_flow_rsp {
1781 struct mbox_msghdr hdr;
1782 /* Negative if no counter else counter number */
1786 struct npc_delete_flow_req {
1787 struct mbox_msghdr hdr;
1788 uint16_t __io entry;
1789 uint16_t __io start; /*Disable range of entries */
1791 uint8_t __io all; /* PF + VFs */
1794 struct npc_mcam_read_entry_req {
1795 struct mbox_msghdr hdr;
1796 /* MCAM entry to read */
1797 uint16_t __io entry;
1800 struct npc_mcam_read_entry_rsp {
1801 struct mbox_msghdr hdr;
1802 struct mcam_entry entry_data;
1804 uint8_t __io enable;
1807 struct npc_mcam_read_base_rule_rsp {
1808 struct mbox_msghdr hdr;
1809 struct mcam_entry entry_data;
1812 struct npc_mcam_get_stats_req {
1813 struct mbox_msghdr hdr;
1814 uint16_t __io entry; /* mcam entry */
1817 struct npc_mcam_get_stats_rsp {
1818 struct mbox_msghdr hdr;
1819 uint64_t __io stat; /* counter stats */
1820 uint8_t __io stat_ena; /* enabled */
1823 /* TIM mailbox error codes
1826 enum tim_af_status {
1827 TIM_AF_NO_RINGS_LEFT = -801,
1828 TIM_AF_INVALID_NPA_PF_FUNC = -802,
1829 TIM_AF_INVALID_SSO_PF_FUNC = -803,
1830 TIM_AF_RING_STILL_RUNNING = -804,
1831 TIM_AF_LF_INVALID = -805,
1832 TIM_AF_CSIZE_NOT_ALIGNED = -806,
1833 TIM_AF_CSIZE_TOO_SMALL = -807,
1834 TIM_AF_CSIZE_TOO_BIG = -808,
1835 TIM_AF_INTERVAL_TOO_SMALL = -809,
1836 TIM_AF_INVALID_BIG_ENDIAN_VALUE = -810,
1837 TIM_AF_INVALID_CLOCK_SOURCE = -811,
1838 TIM_AF_GPIO_CLK_SRC_NOT_ENABLED = -812,
1839 TIM_AF_INVALID_BSIZE = -813,
1840 TIM_AF_INVALID_ENABLE_PERIODIC = -814,
1841 TIM_AF_INVALID_ENABLE_DONTFREE = -815,
1842 TIM_AF_ENA_DONTFRE_NSET_PERIODIC = -816,
1843 TIM_AF_RING_ALREADY_DISABLED = -817,
1847 TIM_CLK_SRCS_TENNS = 0,
1848 TIM_CLK_SRCS_GPIO = 1,
1849 TIM_CLK_SRCS_GTI = 2,
1850 TIM_CLK_SRCS_PTP = 3,
1851 TIM_CLK_SRSC_INVALID,
1854 enum tim_gpio_edge {
1855 TIM_GPIO_NO_EDGE = 0,
1856 TIM_GPIO_LTOH_TRANS = 1,
1857 TIM_GPIO_HTOL_TRANS = 2,
1858 TIM_GPIO_BOTH_TRANS = 3,
1863 PTP_OP_ADJFINE = 0, /* adjfine(req.scaled_ppm); */
1864 PTP_OP_GET_CLOCK = 1, /* rsp.clk = get_clock() */
1868 struct mbox_msghdr hdr;
1870 int64_t __io scaled_ppm;
1871 uint8_t __io is_pmu;
1875 struct mbox_msghdr hdr;
1880 struct get_hw_cap_rsp {
1881 struct mbox_msghdr hdr;
1882 /* Schq mapping fixed or flexible */
1883 uint8_t __io nix_fixed_txschq_mapping;
1884 uint8_t __io nix_shaping; /* Is shaping and coloring supported */
1887 struct ndc_sync_op {
1888 struct mbox_msghdr hdr;
1889 uint8_t __io nix_lf_tx_sync;
1890 uint8_t __io nix_lf_rx_sync;
1891 uint8_t __io npa_lf_sync;
1894 struct tim_lf_alloc_req {
1895 struct mbox_msghdr hdr;
1897 uint16_t __io npa_pf_func;
1898 uint16_t __io sso_pf_func;
1901 struct tim_ring_req {
1902 struct mbox_msghdr hdr;
1906 struct tim_config_req {
1907 struct mbox_msghdr hdr;
1909 uint8_t __io bigendian;
1910 uint8_t __io clocksource;
1911 uint8_t __io enableperiodic;
1912 uint8_t __io enabledontfreebuffer;
1913 uint32_t __io bucketsize;
1914 uint32_t __io chunksize;
1915 uint32_t __io interval;
1916 uint8_t __io gpioedge;
1917 uint8_t __io rsvd[7];
1918 uint64_t __io intervalns;
1919 uint64_t __io clockfreq;
1922 struct tim_lf_alloc_rsp {
1923 struct mbox_msghdr hdr;
1924 uint64_t __io tenns_clk;
1927 struct tim_enable_rsp {
1928 struct mbox_msghdr hdr;
1929 uint64_t __io timestarted;
1930 uint32_t __io currentbucket;
1933 struct tim_intvl_req {
1934 struct mbox_msghdr hdr;
1935 uint8_t __io clocksource;
1936 uint64_t __io clockfreq;
1939 struct tim_intvl_rsp {
1940 struct mbox_msghdr hdr;
1941 uint64_t __io intvl_cyc;
1942 uint64_t __io intvl_ns;
1945 struct sdp_node_info {
1946 /* Node to which this PF belons to */
1947 uint8_t __io node_id;
1948 uint8_t __io max_vfs;
1949 uint8_t __io num_pf_rings;
1950 uint8_t __io pf_srn;
1951 #define SDP_MAX_VFS 128
1952 uint8_t __io vf_rings[SDP_MAX_VFS];
1955 struct sdp_chan_info_msg {
1956 struct mbox_msghdr hdr;
1957 struct sdp_node_info info;
1960 #endif /* __ROC_MBOX_H__ */