1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
12 /* Device memory does not support unaligned access, instruct compiler to
13 * not optimize the memory access when working with mailbox memory.
17 /* Header which precedes all mbox messages */
19 uint64_t __io msg_size; /* Total msgs size embedded */
20 uint16_t __io num_msgs; /* No of msgs embedded */
23 /* Header which precedes every msg and is also part of it */
25 uint16_t __io pcifunc; /* Who's sending this msg */
26 uint16_t __io id; /* Mbox message ID */
27 #define MBOX_REQ_SIG (0xdead)
28 #define MBOX_RSP_SIG (0xbeef)
29 /* Signature, for validating corrupted msgs */
31 #define MBOX_VERSION (0x000a)
32 /* Version of msg's structure for this ID */
34 /* Offset of next msg within mailbox region */
35 uint16_t __io next_msgoff;
36 int __io rc; /* Msg processed response code */
39 /* Mailbox message types */
40 #define MBOX_MSG_MASK 0xFFFF
41 #define MBOX_MSG_INVALID 0xFFFE
42 #define MBOX_MSG_MAX 0xFFFF
44 #define MBOX_MESSAGES \
45 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
46 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
47 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach_req, msg_rsp) \
48 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach_req, msg_rsp) \
49 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
50 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
51 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
52 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
53 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
54 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
55 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
57 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
58 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
59 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
60 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
61 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
62 cgx_mac_addr_set_or_get) \
63 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
64 cgx_mac_addr_set_or_get) \
65 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
66 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
67 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
68 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
69 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, \
71 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
72 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
73 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
74 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
75 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
77 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
78 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
79 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
80 cgx_mac_addr_add_rsp) \
81 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
83 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
84 cgx_max_dmac_entries_get_rsp) \
85 M(CGX_SET_LINK_STATE, 0x214, cgx_set_link_state, \
86 cgx_set_link_state_msg, msg_rsp) \
87 M(CGX_GET_PHY_MOD_TYPE, 0x215, cgx_get_phy_mod_type, msg_req, \
89 M(CGX_SET_PHY_MOD_TYPE, 0x216, cgx_set_phy_mod_type, cgx_phy_mod_type, \
91 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
92 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req, \
93 cgx_set_link_mode_rsp) \
94 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, \
96 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \
97 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
98 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
99 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, npa_lf_alloc_req, \
101 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
102 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
103 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, \
105 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
106 M(SSO_LF_ALLOC, 0x600, sso_lf_alloc, sso_lf_alloc_req, \
108 M(SSO_LF_FREE, 0x601, sso_lf_free, sso_lf_free_req, msg_rsp) \
109 M(SSOW_LF_ALLOC, 0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp) \
110 M(SSOW_LF_FREE, 0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp) \
111 M(SSO_HW_SETCONFIG, 0x604, sso_hw_setconfig, sso_hw_setconfig, \
113 M(SSO_GRP_SET_PRIORITY, 0x605, sso_grp_set_priority, sso_grp_priority, \
115 M(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req, \
117 M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp) \
118 M(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg, \
120 M(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req, \
122 M(SSO_HWS_GET_STATS, 0x610, sso_hws_get_stats, sso_info_req, \
124 M(SSO_HW_RELEASE_XAQ, 0x611, sso_hw_release_xaq_aura, \
125 sso_hw_xaq_release, msg_rsp) \
126 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
127 M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \
129 M(TIM_LF_FREE, 0x801, tim_lf_free, tim_ring_req, msg_rsp) \
130 M(TIM_CONFIG_RING, 0x802, tim_config_ring, tim_config_req, msg_rsp) \
131 M(TIM_ENABLE_RING, 0x803, tim_enable_ring, tim_ring_req, \
133 M(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \
134 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
135 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, msg_rsp) \
136 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
137 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
139 M(CPT_SET_CRYPTO_GRP, 0xA03, cpt_set_crypto_grp, \
140 cpt_set_crypto_grp_req_msg, msg_rsp) \
141 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
142 cpt_inline_ipsec_cfg_msg, msg_rsp) \
143 M(CPT_STATS, 0xA05, cpt_sts_get, cpt_sts_req, cpt_sts_rsp) \
144 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
146 M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \
147 cpt_rx_inline_lf_cfg_msg, msg_rsp) \
148 M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg) \
149 M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req, \
151 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
152 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, \
154 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
155 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, \
156 npc_mcam_alloc_entry_req, npc_mcam_alloc_entry_rsp) \
157 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
158 npc_mcam_free_entry_req, msg_rsp) \
159 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
160 npc_mcam_write_entry_req, msg_rsp) \
161 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
162 npc_mcam_ena_dis_entry_req, msg_rsp) \
163 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
164 npc_mcam_ena_dis_entry_req, msg_rsp) \
165 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, \
166 npc_mcam_shift_entry_req, npc_mcam_shift_entry_rsp) \
167 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
168 npc_mcam_alloc_counter_req, npc_mcam_alloc_counter_rsp) \
169 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
170 npc_mcam_oper_counter_req, msg_rsp) \
171 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
172 npc_mcam_unmap_counter_req, msg_rsp) \
173 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
174 npc_mcam_oper_counter_req, msg_rsp) \
175 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
176 npc_mcam_oper_counter_req, npc_mcam_oper_counter_rsp) \
177 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, \
178 npc_mcam_alloc_and_write_entry, npc_mcam_alloc_and_write_entry_req, \
179 npc_mcam_alloc_and_write_entry_rsp) \
180 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, msg_req, \
181 npc_get_kex_cfg_rsp) \
182 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, npc_install_flow_req, \
183 npc_install_flow_rsp) \
184 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, npc_delete_flow_req, \
186 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
187 npc_mcam_read_entry_req, npc_mcam_read_entry_rsp) \
188 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, npc_set_pkind, msg_rsp) \
189 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, msg_req, \
190 npc_mcam_read_base_rule_rsp) \
191 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
192 npc_mcam_get_stats_req, npc_mcam_get_stats_rsp) \
193 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
194 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, nix_lf_alloc_req, \
196 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
197 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
198 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, hwctx_disable_req, \
200 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, nix_txsch_alloc_req, \
201 nix_txsch_alloc_rsp) \
202 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
203 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
205 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
206 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
207 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
208 nix_rss_flowkey_cfg, nix_rss_flowkey_cfg_rsp) \
209 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, \
211 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
212 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
213 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
214 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
215 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
216 nix_mark_format_cfg, nix_mark_format_cfg_rsp) \
217 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
218 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, nix_lso_format_cfg, \
219 nix_lso_format_cfg_rsp) \
220 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, \
222 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, \
224 M(NIX_SET_VLAN_TPID, 0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid, \
226 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
228 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
229 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, \
230 nix_get_mac_addr_rsp) \
231 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
232 nix_inline_ipsec_cfg, msg_rsp) \
233 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \
234 nix_inline_ipsec_lf_cfg, msg_rsp) \
235 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
236 nix_cn10k_aq_enq_rsp) \
237 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info)
239 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
240 #define MBOX_UP_CGX_MESSAGES \
241 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) \
242 M(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, msg_rsp)
245 #define M(_name, _id, _1, _2, _3) MBOX_MSG_##_name = _id,
246 MBOX_MESSAGES MBOX_UP_CGX_MESSAGES
250 /* Mailbox message formats */
252 #define RVU_DEFAULT_PF_FUNC 0xFFFF
254 /* Generic request msg used for those mbox messages which
255 * don't send any data in the request.
258 struct mbox_msghdr hdr;
261 /* Generic response msg used a ack or response for those mbox
262 * messages which does not have a specific rsp msg format.
265 struct mbox_msghdr hdr;
268 /* RVU mailbox error codes
272 RVU_INVALID_VF_ID = -256,
275 struct ready_msg_rsp {
276 struct mbox_msghdr hdr;
277 uint16_t __io sclk_freq; /* SCLK frequency */
278 uint16_t __io rclk_freq; /* RCLK frequency */
281 /* Struct to set pkind */
282 struct npc_set_pkind {
283 struct mbox_msghdr hdr;
284 #define ROC_PRIV_FLAGS_DEFAULT BIT_ULL(0)
285 #define ROC_PRIV_FLAGS_EDSA BIT_ULL(1)
286 #define ROC_PRIV_FLAGS_HIGIG BIT_ULL(2)
287 #define ROC_PRIV_FLAGS_LEN_90B BIT_ULL(3)
288 #define ROC_PRIV_FLAGS_CUSTOM BIT_ULL(63)
290 #define PKIND_TX BIT_ULL(0)
291 #define PKIND_RX BIT_ULL(1)
293 uint8_t __io pkind; /* valid only in case custom flag */
296 /* Structure for requesting resource provisioning.
297 * 'modify' flag to be used when either requesting more
298 * or to detach partial of a certain resource type.
299 * Rest of the fields specify how many of what type to
301 * To request LFs from two blocks of same type this mailbox
302 * can be sent twice as below:
303 * struct rsrc_attach *attach;
304 * .. Allocate memory for message ..
305 * attach->cptlfs = 3; <3 LFs from CPT0>
307 * .. Allocate memory for message ..
308 * attach->modify = 1;
309 * attach->cpt_blkaddr = BLKADDR_CPT1;
310 * attach->cptlfs = 2; <2 LFs from CPT1>
313 struct rsrc_attach_req {
314 struct mbox_msghdr hdr;
315 uint8_t __io modify : 1;
316 uint8_t __io npalf : 1;
317 uint8_t __io nixlf : 1;
320 uint16_t __io timlfs;
321 uint16_t __io cptlfs;
322 uint16_t __io reelfs;
323 /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
324 int __io cpt_blkaddr;
325 /* BLKADDR_REE0/BLKADDR_REE1 or 0 for BLKADDR_REE0 */
326 int __io ree_blkaddr;
329 /* Structure for relinquishing resources.
330 * 'partial' flag to be used when relinquishing all resources
331 * but only of a certain type. If not set, all resources of all
332 * types provisioned to the RVU function will be detached.
334 struct rsrc_detach_req {
335 struct mbox_msghdr hdr;
336 uint8_t __io partial : 1;
337 uint8_t __io npalf : 1;
338 uint8_t __io nixlf : 1;
339 uint8_t __io sso : 1;
340 uint8_t __io ssow : 1;
341 uint8_t __io timlfs : 1;
342 uint8_t __io cptlfs : 1;
343 uint8_t __io reelfs : 1;
346 /* NIX Transmit schedulers */
347 #define NIX_TXSCH_LVL_SMQ 0x0
348 #define NIX_TXSCH_LVL_MDQ 0x0
349 #define NIX_TXSCH_LVL_TL4 0x1
350 #define NIX_TXSCH_LVL_TL3 0x2
351 #define NIX_TXSCH_LVL_TL2 0x3
352 #define NIX_TXSCH_LVL_TL1 0x4
353 #define NIX_TXSCH_LVL_CNT 0x5
356 * Number of resources available to the caller.
357 * In reply to MBOX_MSG_FREE_RSRC_CNT.
359 struct free_rsrcs_rsp {
360 struct mbox_msghdr hdr;
361 uint16_t __io schq[NIX_TXSCH_LVL_CNT];
368 uint16_t __io schq_nix1[NIX_TXSCH_LVL_CNT];
375 #define MSIX_VECTOR_INVALID 0xFFFF
376 #define MAX_RVU_BLKLF_CNT 256
378 struct msix_offset_rsp {
379 struct mbox_msghdr hdr;
380 uint16_t __io npa_msixoff;
381 uint16_t __io nix_msixoff;
384 uint16_t __io timlfs;
385 uint16_t __io cptlfs;
386 uint16_t __io sso_msixoff[MAX_RVU_BLKLF_CNT];
387 uint16_t __io ssow_msixoff[MAX_RVU_BLKLF_CNT];
388 uint16_t __io timlf_msixoff[MAX_RVU_BLKLF_CNT];
389 uint16_t __io cptlf_msixoff[MAX_RVU_BLKLF_CNT];
390 uint16_t __io cpt1_lfs;
391 uint16_t __io ree0_lfs;
392 uint16_t __io ree1_lfs;
393 uint16_t __io cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
394 uint16_t __io ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
395 uint16_t __io ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
398 struct lmtst_tbl_setup_req {
399 struct mbox_msghdr hdr;
401 uint64_t __io dis_sched_early_comp : 1;
402 uint64_t __io sched_ena : 1;
403 uint64_t __io dis_line_pref : 1;
404 uint64_t __io ssow_pf_func : 13;
405 uint16_t __io pcifunc;
408 /* CGX mbox message formats */
410 struct cgx_stats_rsp {
411 struct mbox_msghdr hdr;
412 #define CGX_RX_STATS_COUNT 13
413 #define CGX_TX_STATS_COUNT 18
414 uint64_t __io rx_stats[CGX_RX_STATS_COUNT];
415 uint64_t __io tx_stats[CGX_TX_STATS_COUNT];
418 struct rpm_stats_rsp {
419 struct mbox_msghdr hdr;
420 #define RPM_RX_STATS_COUNT 43
421 #define RPM_TX_STATS_COUNT 34
422 uint64_t __io rx_stats[RPM_RX_STATS_COUNT];
423 uint64_t __io tx_stats[RPM_TX_STATS_COUNT];
426 struct cgx_fec_stats_rsp {
427 struct mbox_msghdr hdr;
428 uint64_t __io fec_corr_blks;
429 uint64_t __io fec_uncorr_blks;
432 /* Structure for requesting the operation for
433 * setting/getting mac address in the CGX interface
435 struct cgx_mac_addr_set_or_get {
436 struct mbox_msghdr hdr;
437 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
440 /* Structure for requesting the operation to
441 * add DMAC filter entry into CGX interface
443 struct cgx_mac_addr_add_req {
444 struct mbox_msghdr hdr;
445 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
448 /* Structure for response against the operation to
449 * add DMAC filter entry into CGX interface
451 struct cgx_mac_addr_add_rsp {
452 struct mbox_msghdr hdr;
456 /* Structure for requesting the operation to
457 * delete DMAC filter entry from CGX interface
459 struct cgx_mac_addr_del_req {
460 struct mbox_msghdr hdr;
464 /* Structure for response against the operation to
465 * get maximum supported DMAC filter entries
467 struct cgx_max_dmac_entries_get_rsp {
468 struct mbox_msghdr hdr;
469 uint8_t __io max_dmac_filters;
472 struct cgx_link_user_info {
473 uint64_t __io link_up : 1;
474 uint64_t __io full_duplex : 1;
475 uint64_t __io lmac_type_id : 4;
476 uint64_t __io speed : 20; /* speed in Mbps */
477 uint64_t __io an : 1; /* AN supported or not */
478 uint64_t __io fec : 2; /* FEC type if enabled else 0 */
479 uint64_t __io port : 8;
480 #define LMACTYPE_STR_LEN 16
481 char lmac_type[LMACTYPE_STR_LEN];
484 struct cgx_link_info_msg {
485 struct mbox_msghdr hdr;
486 struct cgx_link_user_info link_info;
489 struct cgx_ptp_rx_info_msg {
490 struct mbox_msghdr hdr;
494 struct cgx_pause_frm_cfg {
495 struct mbox_msghdr hdr;
497 /* set = 1 if the request is to config pause frames */
498 /* set = 0 if the request is to fetch pause frames config */
499 uint8_t __io rx_pause;
500 uint8_t __io tx_pause;
503 struct sfp_eeprom_s {
504 #define SFP_EEPROM_SIZE 256
505 uint16_t __io sff_id;
506 uint8_t __io buf[SFP_EEPROM_SIZE];
507 uint64_t __io reserved;
517 uint64_t __io can_change_mod_type : 1;
518 uint64_t __io mod_type : 1;
521 struct cgx_lmac_fwdata_s {
522 uint16_t __io rw_valid;
523 uint64_t __io supported_fec;
524 uint64_t __io supported_an;
525 uint64_t __io supported_link_modes;
526 /* Only applicable if AN is supported */
527 uint64_t __io advertised_fec;
528 uint64_t __io advertised_link_modes;
529 /* Only applicable if SFP/QSFP slot is present */
530 struct sfp_eeprom_s sfp_eeprom;
532 #define LMAC_FWDATA_RESERVED_MEM 1023
533 uint64_t __io reserved[LMAC_FWDATA_RESERVED_MEM];
537 struct mbox_msghdr hdr;
538 struct cgx_lmac_fwdata_s fwdata;
542 struct mbox_msghdr hdr;
546 struct cgx_set_link_state_msg {
547 struct mbox_msghdr hdr;
551 struct cgx_phy_mod_type {
552 struct mbox_msghdr hdr;
556 struct cgx_set_link_mode_args {
564 struct cgx_set_link_mode_req {
565 struct mbox_msghdr hdr;
566 struct cgx_set_link_mode_args args;
569 struct cgx_set_link_mode_rsp {
570 struct mbox_msghdr hdr;
574 /* NPA mbox message formats */
576 /* NPA mailbox error codes
580 NPA_AF_ERR_PARAM = -301,
581 NPA_AF_ERR_AQ_FULL = -302,
582 NPA_AF_ERR_AQ_ENQUEUE = -303,
583 NPA_AF_ERR_AF_LF_INVALID = -304,
584 NPA_AF_ERR_AF_LF_ALLOC = -305,
585 NPA_AF_ERR_LF_RESET = -306,
588 #define NPA_AURA_SZ_0 0
589 #define NPA_AURA_SZ_128 1
590 #define NPA_AURA_SZ_256 2
591 #define NPA_AURA_SZ_512 3
592 #define NPA_AURA_SZ_1K 4
593 #define NPA_AURA_SZ_2K 5
594 #define NPA_AURA_SZ_4K 6
595 #define NPA_AURA_SZ_8K 7
596 #define NPA_AURA_SZ_16K 8
597 #define NPA_AURA_SZ_32K 9
598 #define NPA_AURA_SZ_64K 10
599 #define NPA_AURA_SZ_128K 11
600 #define NPA_AURA_SZ_256K 12
601 #define NPA_AURA_SZ_512K 13
602 #define NPA_AURA_SZ_1M 14
603 #define NPA_AURA_SZ_MAX 15
605 /* For NPA LF context alloc and init */
606 struct npa_lf_alloc_req {
607 struct mbox_msghdr hdr;
609 int __io aura_sz; /* No of auras. See NPA_AURA_SZ_* */
610 uint32_t __io nr_pools; /* No of pools */
611 uint64_t __io way_mask;
614 struct npa_lf_alloc_rsp {
615 struct mbox_msghdr hdr;
616 uint32_t __io stack_pg_ptrs; /* No of ptrs per stack page */
617 uint32_t __io stack_pg_bytes; /* Size of stack page */
618 uint16_t __io qints; /* NPA_AF_CONST::QINTS */
619 uint8_t __io cache_lines; /* Batch Alloc DMA */
622 /* NPA AQ enqueue msg */
623 struct npa_aq_enq_req {
624 struct mbox_msghdr hdr;
625 uint32_t __io aura_id;
629 /* Valid when op == WRITE/INIT and ctype == AURA.
630 * LF fills the pool_id in aura.pool_addr. AF will translate
631 * the pool_id to pool context pointer.
633 __io struct npa_aura_s aura;
634 /* Valid when op == WRITE/INIT and ctype == POOL */
635 __io struct npa_pool_s pool;
637 /* Mask data when op == WRITE (1=write, 0=don't write) */
639 /* Valid when op == WRITE and ctype == AURA */
640 __io struct npa_aura_s aura_mask;
641 /* Valid when op == WRITE and ctype == POOL */
642 __io struct npa_pool_s pool_mask;
646 struct npa_aq_enq_rsp {
647 struct mbox_msghdr hdr;
649 /* Valid when op == READ and ctype == AURA */
650 __io struct npa_aura_s aura;
651 /* Valid when op == READ and ctype == POOL */
652 __io struct npa_pool_s pool;
656 /* Disable all contexts of type 'ctype' */
657 struct hwctx_disable_req {
658 struct mbox_msghdr hdr;
662 /* NIX mbox message formats */
664 /* NIX mailbox error codes
668 NIX_AF_ERR_PARAM = -401,
669 NIX_AF_ERR_AQ_FULL = -402,
670 NIX_AF_ERR_AQ_ENQUEUE = -403,
671 NIX_AF_ERR_AF_LF_INVALID = -404,
672 NIX_AF_ERR_AF_LF_ALLOC = -405,
673 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
674 NIX_AF_ERR_TLX_INVALID = -407,
675 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
676 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
677 NIX_AF_ERR_FRS_INVALID = -410,
678 NIX_AF_ERR_RX_LINK_INVALID = -411,
679 NIX_AF_INVAL_TXSCHQ_CFG = -412,
680 NIX_AF_SMQ_FLUSH_FAILED = -413,
681 NIX_AF_ERR_LF_RESET = -414,
682 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
683 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
684 NIX_AF_ERR_MARK_CFG_FAIL = -417,
685 NIX_AF_ERR_LSO_CFG_FAIL = -418,
686 NIX_AF_INVAL_NPA_PF_FUNC = -419,
687 NIX_AF_INVAL_SSO_PF_FUNC = -420,
688 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
689 NIX_AF_ERR_RX_VTAG_INUSE = -422,
690 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
693 /* For NIX LF context alloc and init */
694 struct nix_lf_alloc_req {
695 struct mbox_msghdr hdr;
697 uint32_t __io rq_cnt; /* No of receive queues */
698 uint32_t __io sq_cnt; /* No of send queues */
699 uint32_t __io cq_cnt; /* No of completion queues */
701 uint16_t __io rss_sz;
702 uint8_t __io rss_grps;
703 uint16_t __io npa_func;
704 /* RVU_DEFAULT_PF_FUNC == default pf_func associated with lf */
705 uint16_t __io sso_func;
706 uint64_t __io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
707 uint64_t __io way_mask;
708 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
712 struct nix_lf_alloc_rsp {
713 struct mbox_msghdr hdr;
714 uint16_t __io sqb_size;
715 uint16_t __io rx_chan_base;
716 uint16_t __io tx_chan_base;
717 uint8_t __io rx_chan_cnt; /* Total number of RX channels */
718 uint8_t __io tx_chan_cnt; /* Total number of TX channels */
719 uint8_t __io lso_tsov4_idx;
720 uint8_t __io lso_tsov6_idx;
721 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
722 uint8_t __io lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
723 uint8_t __io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
724 uint16_t __io cints; /* NIX_AF_CONST2::CINTS */
725 uint16_t __io qints; /* NIX_AF_CONST2::QINTS */
726 uint8_t __io hw_rx_tstamp_en; /*set if rx timestamping enabled */
727 uint8_t __io cgx_links; /* No. of CGX links present in HW */
728 uint8_t __io lbk_links; /* No. of LBK links present in HW */
729 uint8_t __io sdp_links; /* No. of SDP links present in HW */
730 uint8_t tx_link; /* Transmit channel link number */
733 struct nix_lf_free_req {
734 struct mbox_msghdr hdr;
735 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
736 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
740 /* CN10x NIX AQ enqueue msg */
741 struct nix_cn10k_aq_enq_req {
742 struct mbox_msghdr hdr;
747 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
748 __io struct nix_cn10k_rq_ctx_s rq;
749 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
750 __io struct nix_cn10k_sq_ctx_s sq;
751 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
752 __io struct nix_cq_ctx_s cq;
753 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
754 __io struct nix_rsse_s rss;
755 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
756 __io struct nix_rx_mce_s mce;
758 /* Mask data when op == WRITE (1=write, 0=don't write) */
760 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
761 __io struct nix_cn10k_rq_ctx_s rq_mask;
762 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
763 __io struct nix_cn10k_sq_ctx_s sq_mask;
764 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
765 __io struct nix_cq_ctx_s cq_mask;
766 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
767 __io struct nix_rsse_s rss_mask;
768 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
769 __io struct nix_rx_mce_s mce_mask;
773 struct nix_cn10k_aq_enq_rsp {
774 struct mbox_msghdr hdr;
776 struct nix_cn10k_rq_ctx_s rq;
777 struct nix_cn10k_sq_ctx_s sq;
778 struct nix_cq_ctx_s cq;
779 struct nix_rsse_s rss;
780 struct nix_rx_mce_s mce;
784 /* NIX AQ enqueue msg */
785 struct nix_aq_enq_req {
786 struct mbox_msghdr hdr;
791 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
792 __io struct nix_rq_ctx_s rq;
793 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
794 __io struct nix_sq_ctx_s sq;
795 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
796 __io struct nix_cq_ctx_s cq;
797 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
798 __io struct nix_rsse_s rss;
799 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
800 __io struct nix_rx_mce_s mce;
802 /* Mask data when op == WRITE (1=write, 0=don't write) */
804 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
805 __io struct nix_rq_ctx_s rq_mask;
806 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
807 __io struct nix_sq_ctx_s sq_mask;
808 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
809 __io struct nix_cq_ctx_s cq_mask;
810 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
811 __io struct nix_rsse_s rss_mask;
812 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
813 __io struct nix_rx_mce_s mce_mask;
817 struct nix_aq_enq_rsp {
818 struct mbox_msghdr hdr;
820 __io struct nix_rq_ctx_s rq;
821 __io struct nix_sq_ctx_s sq;
822 __io struct nix_cq_ctx_s cq;
823 __io struct nix_rsse_s rss;
824 __io struct nix_rx_mce_s mce;
828 /* Tx scheduler/shaper mailbox messages */
830 #define MAX_TXSCHQ_PER_FUNC 128
832 struct nix_txsch_alloc_req {
833 struct mbox_msghdr hdr;
834 /* Scheduler queue count request at each level */
835 uint16_t __io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
836 uint16_t __io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
839 struct nix_txsch_alloc_rsp {
840 struct mbox_msghdr hdr;
841 /* Scheduler queue count allocated at each level */
842 uint16_t __io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
843 uint16_t __io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
844 /* Scheduler queue list allocated at each level */
845 uint16_t __io schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
846 uint16_t __io schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
847 /* Traffic aggregation scheduler level */
848 uint8_t __io aggr_level;
849 /* Aggregation lvl's RR_PRIO config */
850 uint8_t __io aggr_lvl_rr_prio;
851 /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
852 uint8_t __io link_cfg_lvl;
855 struct nix_txsch_free_req {
856 struct mbox_msghdr hdr;
857 #define TXSCHQ_FREE_ALL BIT_ULL(0)
859 /* Scheduler queue level to be freed */
860 uint16_t __io schq_lvl;
861 /* List of scheduler queues to be freed */
865 struct nix_txschq_config {
866 struct mbox_msghdr hdr;
867 uint8_t __io lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
869 #define TXSCHQ_IDX_SHIFT 16
870 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
871 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
872 uint8_t __io num_regs;
873 #define MAX_REGS_PER_MBOX_MSG 20
874 uint64_t __io reg[MAX_REGS_PER_MBOX_MSG];
875 uint64_t __io regval[MAX_REGS_PER_MBOX_MSG];
876 /* All 0's => overwrite with new value */
877 uint64_t __io regval_mask[MAX_REGS_PER_MBOX_MSG];
880 struct nix_vtag_config {
881 struct mbox_msghdr hdr;
882 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
883 uint8_t __io vtag_size;
884 /* cfg_type is '0' for tx vlan cfg
885 * cfg_type is '1' for rx vlan cfg
887 uint8_t __io cfg_type;
889 /* Valid when cfg_type is '0' */
894 /* cfg_vtag0 & cfg_vtag1 fields are valid
895 * when free_vtag0 & free_vtag1 are '0's.
897 /* cfg_vtag0 = 1 to configure vtag0 */
898 uint8_t __io cfg_vtag0 : 1;
899 /* cfg_vtag1 = 1 to configure vtag1 */
900 uint8_t __io cfg_vtag1 : 1;
902 /* vtag0_idx & vtag1_idx are only valid when
903 * both cfg_vtag0 & cfg_vtag1 are '0's,
904 * these fields are used along with free_vtag0
905 * & free_vtag1 to free the nix lf's tx_vlan
908 * Denotes the indices of tx_vtag def registers
909 * that needs to be cleared and freed.
914 /* Free_vtag0 & free_vtag1 fields are valid
915 * when cfg_vtag0 & cfg_vtag1 are '0's.
917 /* Free_vtag0 = 1 clears vtag0 configuration
918 * vtag0_idx denotes the index to be cleared.
920 uint8_t __io free_vtag0 : 1;
921 /* Free_vtag1 = 1 clears vtag1 configuration
922 * vtag1_idx denotes the index to be cleared.
924 uint8_t __io free_vtag1 : 1;
927 /* Valid when cfg_type is '1' */
929 /* Rx vtag type index, valid values are in 0..7 range */
930 uint8_t __io vtag_type;
932 uint8_t __io strip_vtag : 1;
933 /* Rx vtag capture */
934 uint8_t __io capture_vtag : 1;
939 struct nix_vtag_config_rsp {
940 struct mbox_msghdr hdr;
941 /* Indices of tx_vtag def registers used to configure
942 * tx vtag0 & vtag1 headers, these indices are valid
943 * when nix_vtag_config mbox requested for vtag0 and/
944 * or vtag1 configuration.
950 struct nix_rss_flowkey_cfg {
951 struct mbox_msghdr hdr;
952 int __io mcam_index; /* MCAM entry index to modify */
953 uint32_t __io flowkey_cfg; /* Flowkey types selected */
954 #define FLOW_KEY_TYPE_PORT BIT(0)
955 #define FLOW_KEY_TYPE_IPV4 BIT(1)
956 #define FLOW_KEY_TYPE_IPV6 BIT(2)
957 #define FLOW_KEY_TYPE_TCP BIT(3)
958 #define FLOW_KEY_TYPE_UDP BIT(4)
959 #define FLOW_KEY_TYPE_SCTP BIT(5)
960 #define FLOW_KEY_TYPE_NVGRE BIT(6)
961 #define FLOW_KEY_TYPE_VXLAN BIT(7)
962 #define FLOW_KEY_TYPE_GENEVE BIT(8)
963 #define FLOW_KEY_TYPE_ETH_DMAC BIT(9)
964 #define FLOW_KEY_TYPE_IPV6_EXT BIT(10)
965 #define FLOW_KEY_TYPE_GTPU BIT(11)
966 #define FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
967 #define FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
968 #define FLOW_KEY_TYPE_INNR_TCP BIT(14)
969 #define FLOW_KEY_TYPE_INNR_UDP BIT(15)
970 #define FLOW_KEY_TYPE_INNR_SCTP BIT(16)
971 #define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
972 #define FLOW_KEY_TYPE_CH_LEN_90B BIT(18)
973 #define FLOW_KEY_TYPE_CUSTOM0 BIT(19)
974 #define FLOW_KEY_TYPE_VLAN BIT(20)
975 #define FLOW_KEY_TYPE_L4_DST BIT(28)
976 #define FLOW_KEY_TYPE_L4_SRC BIT(29)
977 #define FLOW_KEY_TYPE_L3_DST BIT(30)
978 #define FLOW_KEY_TYPE_L3_SRC BIT(31)
979 uint8_t __io group; /* RSS context or group */
982 struct nix_rss_flowkey_cfg_rsp {
983 struct mbox_msghdr hdr;
984 uint8_t __io alg_idx; /* Selected algo index */
987 struct nix_set_mac_addr {
988 struct mbox_msghdr hdr;
989 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
992 struct nix_get_mac_addr_rsp {
993 struct mbox_msghdr hdr;
994 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
997 struct nix_mark_format_cfg {
998 struct mbox_msghdr hdr;
1000 uint8_t __io y_mask;
1002 uint8_t __io r_mask;
1006 struct nix_mark_format_cfg_rsp {
1007 struct mbox_msghdr hdr;
1008 uint8_t __io mark_format_idx;
1011 struct nix_lso_format_cfg {
1012 struct mbox_msghdr hdr;
1013 uint64_t __io field_mask;
1014 uint64_t __io fields[NIX_LSO_FIELD_MAX];
1017 struct nix_lso_format_cfg_rsp {
1018 struct mbox_msghdr hdr;
1019 uint8_t __io lso_format_idx;
1022 struct nix_rx_mode {
1023 struct mbox_msghdr hdr;
1024 #define NIX_RX_MODE_UCAST BIT(0)
1025 #define NIX_RX_MODE_PROMISC BIT(1)
1026 #define NIX_RX_MODE_ALLMULTI BIT(2)
1031 struct mbox_msghdr hdr;
1032 #define NIX_RX_OL3_VERIFY BIT(0)
1033 #define NIX_RX_OL4_VERIFY BIT(1)
1034 uint8_t __io len_verify; /* Outer L3/L4 len check */
1035 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1036 uint8_t __io csum_verify; /* Outer L4 checksum verification */
1039 struct nix_frs_cfg {
1040 struct mbox_msghdr hdr;
1041 uint8_t __io update_smq; /* Update SMQ's min/max lens */
1042 uint8_t __io update_minlen; /* Set minlen also */
1043 uint8_t __io sdp_link; /* Set SDP RX link */
1044 uint16_t __io maxlen;
1045 uint16_t __io minlen;
1048 struct nix_set_vlan_tpid {
1049 struct mbox_msghdr hdr;
1050 #define NIX_VLAN_TYPE_INNER 0
1051 #define NIX_VLAN_TYPE_OUTER 1
1052 uint8_t __io vlan_type;
1056 struct nix_bp_cfg_req {
1057 struct mbox_msghdr hdr;
1058 uint16_t __io chan_base; /* Starting channel number */
1059 uint8_t __io chan_cnt; /* Number of channels */
1060 uint8_t __io bpid_per_chan;
1061 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1062 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1065 /* PF can be mapped to either CGX or LBK interface,
1066 * so maximum 64 channels are possible.
1068 #define NIX_MAX_CHAN 64
1069 struct nix_bp_cfg_rsp {
1070 struct mbox_msghdr hdr;
1071 /* Channel and bpid mapping */
1072 uint16_t __io chan_bpid[NIX_MAX_CHAN];
1073 /* Number of channel for which bpids are assigned */
1074 uint8_t __io chan_cnt;
1077 /* Global NIX inline IPSec configuration */
1078 struct nix_inline_ipsec_cfg {
1079 struct mbox_msghdr hdr;
1080 uint32_t __io cpt_credit;
1083 uint8_t __io opcode;
1086 uint16_t __io cpt_pf_func;
1087 uint8_t __io cpt_slot;
1089 uint8_t __io enable;
1092 /* Per NIX LF inline IPSec configuration */
1093 struct nix_inline_ipsec_lf_cfg {
1094 struct mbox_msghdr hdr;
1095 uint64_t __io sa_base_addr;
1097 uint32_t __io tag_const;
1098 uint16_t __io lenm1_max;
1099 uint8_t __io sa_pow2_size;
1103 uint32_t __io sa_idx_max;
1104 uint8_t __io sa_idx_w;
1106 uint8_t __io enable;
1109 struct nix_hw_info {
1110 struct mbox_msghdr hdr;
1111 uint16_t __io vwqe_delay;
1112 uint16_t __io rsvd[15];
1115 /* SSO mailbox error codes
1118 enum sso_af_status {
1119 SSO_AF_ERR_PARAM = -501,
1120 SSO_AF_ERR_LF_INVALID = -502,
1121 SSO_AF_ERR_AF_LF_ALLOC = -503,
1122 SSO_AF_ERR_GRP_EBUSY = -504,
1123 SSO_AF_INVAL_NPA_PF_FUNC = -505,
1126 struct sso_lf_alloc_req {
1127 struct mbox_msghdr hdr;
1129 uint16_t __io hwgrps;
1132 struct sso_lf_alloc_rsp {
1133 struct mbox_msghdr hdr;
1134 uint32_t __io xaq_buf_size;
1135 uint32_t __io xaq_wq_entries;
1136 uint32_t __io in_unit_entries;
1137 uint16_t __io hwgrps;
1140 struct sso_lf_free_req {
1141 struct mbox_msghdr hdr;
1143 uint16_t __io hwgrps;
1146 /* SSOW mailbox error codes
1149 enum ssow_af_status {
1150 SSOW_AF_ERR_PARAM = -601,
1151 SSOW_AF_ERR_LF_INVALID = -602,
1152 SSOW_AF_ERR_AF_LF_ALLOC = -603,
1155 struct ssow_lf_alloc_req {
1156 struct mbox_msghdr hdr;
1161 struct ssow_lf_free_req {
1162 struct mbox_msghdr hdr;
1167 struct sso_hw_setconfig {
1168 struct mbox_msghdr hdr;
1169 uint32_t __io npa_aura_id;
1170 uint16_t __io npa_pf_func;
1171 uint16_t __io hwgrps;
1174 struct sso_hw_xaq_release {
1175 struct mbox_msghdr hdr;
1176 uint16_t __io hwgrps;
1179 struct sso_info_req {
1180 struct mbox_msghdr hdr;
1187 struct sso_grp_priority {
1188 struct mbox_msghdr hdr;
1190 uint8_t __io priority;
1191 uint8_t __io affinity;
1192 uint8_t __io weight;
1195 struct sso_grp_qos_cfg {
1196 struct mbox_msghdr hdr;
1198 uint32_t __io xaq_limit;
1199 uint16_t __io taq_thr;
1200 uint16_t __io iaq_thr;
1203 struct sso_grp_stats {
1204 struct mbox_msghdr hdr;
1206 uint64_t __io ws_pc;
1207 uint64_t __io ext_pc;
1208 uint64_t __io wa_pc;
1209 uint64_t __io ts_pc;
1210 uint64_t __io ds_pc;
1211 uint64_t __io dq_pc;
1212 uint64_t __io aw_status;
1213 uint64_t __io page_cnt;
1216 struct sso_hws_stats {
1217 struct mbox_msghdr hdr;
1219 uint64_t __io arbitration;
1222 /* CPT mailbox error codes
1225 enum cpt_af_status {
1226 CPT_AF_ERR_PARAM = -901,
1227 CPT_AF_ERR_GRP_INVALID = -902,
1228 CPT_AF_ERR_LF_INVALID = -903,
1229 CPT_AF_ERR_ACCESS_DENIED = -904,
1230 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1231 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1232 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1233 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1236 /* CPT mbox message formats */
1238 struct cpt_rd_wr_reg_msg {
1239 struct mbox_msghdr hdr;
1240 uint64_t __io reg_offset;
1241 uint64_t __io *ret_val;
1243 uint8_t __io is_write;
1246 struct cpt_set_crypto_grp_req_msg {
1247 struct mbox_msghdr hdr;
1248 uint8_t __io crypto_eng_grp;
1251 struct cpt_lf_alloc_req_msg {
1252 struct mbox_msghdr hdr;
1253 uint16_t __io nix_pf_func;
1254 uint16_t __io sso_pf_func;
1255 uint16_t __io eng_grpmsk;
1256 uint8_t __io blkaddr;
1259 #define CPT_INLINE_INBOUND 0
1260 #define CPT_INLINE_OUTBOUND 1
1262 struct cpt_inline_ipsec_cfg_msg {
1263 struct mbox_msghdr hdr;
1264 uint8_t __io enable;
1267 uint8_t __io sso_pf_func_ovrd;
1268 uint16_t __io sso_pf_func; /* Inbound path SSO_PF_FUNC */
1269 uint16_t __io nix_pf_func; /* Outbound path NIX_PF_FUNC */
1272 struct cpt_sts_req {
1273 struct mbox_msghdr hdr;
1274 uint8_t __io blkaddr;
1277 struct cpt_sts_rsp {
1278 struct mbox_msghdr hdr;
1279 uint64_t __io inst_req_pc;
1280 uint64_t __io inst_lat_pc;
1281 uint64_t __io rd_req_pc;
1282 uint64_t __io rd_lat_pc;
1283 uint64_t __io rd_uc_pc;
1284 uint64_t __io active_cycles_pc;
1285 uint64_t __io ctx_mis_pc;
1286 uint64_t __io ctx_hit_pc;
1287 uint64_t __io ctx_aop_pc;
1288 uint64_t __io ctx_aop_lat_pc;
1289 uint64_t __io ctx_ifetch_pc;
1290 uint64_t __io ctx_ifetch_lat_pc;
1291 uint64_t __io ctx_ffetch_pc;
1292 uint64_t __io ctx_ffetch_lat_pc;
1293 uint64_t __io ctx_wback_pc;
1294 uint64_t __io ctx_wback_lat_pc;
1295 uint64_t __io ctx_psh_pc;
1296 uint64_t __io ctx_psh_lat_pc;
1297 uint64_t __io ctx_err;
1298 uint64_t __io ctx_enc_id;
1299 uint64_t __io ctx_flush_timer;
1300 uint64_t __io rxc_time;
1301 uint64_t __io rxc_time_cfg;
1302 uint64_t __io rxc_active_sts;
1303 uint64_t __io rxc_zombie_sts;
1304 uint64_t __io busy_sts_ae;
1305 uint64_t __io free_sts_ae;
1306 uint64_t __io busy_sts_se;
1307 uint64_t __io free_sts_se;
1308 uint64_t __io busy_sts_ie;
1309 uint64_t __io free_sts_ie;
1310 uint64_t __io exe_err_info;
1311 uint64_t __io cptclk_cnt;
1313 uint64_t __io rxc_dfrg;
1314 uint64_t __io x2p_link_cfg0;
1315 uint64_t __io x2p_link_cfg1;
1318 struct cpt_rxc_time_cfg_req {
1319 struct mbox_msghdr hdr;
1322 uint16_t zombie_thres;
1323 uint16_t zombie_limit;
1324 uint16_t active_thres;
1325 uint16_t active_limit;
1328 struct cpt_rx_inline_lf_cfg_msg {
1329 struct mbox_msghdr hdr;
1330 uint16_t __io sso_pf_func;
1334 CPT_ENG_TYPE_AE = 1,
1335 CPT_ENG_TYPE_SE = 2,
1336 CPT_ENG_TYPE_IE = 3,
1340 /* CPT HW capabilities */
1341 union cpt_eng_caps {
1344 uint64_t __io reserved_0_4 : 5;
1345 uint64_t __io mul : 1;
1346 uint64_t __io sha1_sha2 : 1;
1347 uint64_t __io chacha20 : 1;
1348 uint64_t __io zuc_snow3g : 1;
1349 uint64_t __io sha3 : 1;
1350 uint64_t __io aes : 1;
1351 uint64_t __io kasumi : 1;
1352 uint64_t __io des : 1;
1353 uint64_t __io crc : 1;
1354 uint64_t __io reserved_14_63 : 50;
1358 struct cpt_caps_rsp_msg {
1359 struct mbox_msghdr hdr;
1360 uint16_t __io cpt_pf_drv_version;
1361 uint8_t __io cpt_revision;
1362 union cpt_eng_caps eng_caps[CPT_MAX_ENG_TYPES];
1365 struct cpt_eng_grp_req {
1366 struct mbox_msghdr hdr;
1367 uint8_t __io eng_type;
1370 struct cpt_eng_grp_rsp {
1371 struct mbox_msghdr hdr;
1372 uint8_t __io eng_type;
1373 uint8_t __io eng_grp_num;
1376 /* NPC mbox message structs */
1378 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1379 #define NPC_MCAM_INVALID_MAP 0xFFFF
1381 /* NPC mailbox error codes
1384 enum npc_af_status {
1385 NPC_MCAM_INVALID_REQ = -701,
1386 NPC_MCAM_ALLOC_DENIED = -702,
1387 NPC_MCAM_ALLOC_FAILED = -703,
1388 NPC_MCAM_PERM_DENIED = -704,
1389 NPC_AF_ERR_HIGIG_CONFIG_FAIL = -705,
1392 struct npc_mcam_alloc_entry_req {
1393 struct mbox_msghdr hdr;
1394 #define NPC_MAX_NONCONTIG_ENTRIES 256
1395 uint8_t __io contig; /* Contiguous entries ? */
1396 #define NPC_MCAM_ANY_PRIO 0
1397 #define NPC_MCAM_LOWER_PRIO 1
1398 #define NPC_MCAM_HIGHER_PRIO 2
1399 uint8_t __io priority; /* Lower or higher w.r.t ref_entry */
1400 uint16_t __io ref_entry;
1401 uint16_t __io count; /* Number of entries requested */
1404 struct npc_mcam_alloc_entry_rsp {
1405 struct mbox_msghdr hdr;
1406 /* Entry alloc'ed or start index if contiguous.
1407 * Invalid in case of non-contiguous.
1409 uint16_t __io entry;
1410 uint16_t __io count; /* Number of entries allocated */
1411 uint16_t __io free_count; /* Number of entries available */
1412 uint16_t __io entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1415 struct npc_mcam_free_entry_req {
1416 struct mbox_msghdr hdr;
1417 uint16_t __io entry; /* Entry index to be freed */
1418 uint8_t __io all; /* Free all entries alloc'ed to this PFVF */
1422 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max key width */
1423 uint64_t __io kw[NPC_MAX_KWS_IN_KEY];
1424 uint64_t __io kw_mask[NPC_MAX_KWS_IN_KEY];
1425 uint64_t __io action;
1426 uint64_t __io vtag_action;
1429 struct npc_mcam_write_entry_req {
1430 struct mbox_msghdr hdr;
1431 struct mcam_entry entry_data;
1432 uint16_t __io entry; /* MCAM entry to write this match key */
1433 uint16_t __io cntr; /* Counter for this MCAM entry */
1434 uint8_t __io intf; /* Rx or Tx interface */
1435 uint8_t __io enable_entry; /* Enable this MCAM entry ? */
1436 uint8_t __io set_cntr; /* Set counter for this entry ? */
1439 /* Enable/Disable a given entry */
1440 struct npc_mcam_ena_dis_entry_req {
1441 struct mbox_msghdr hdr;
1442 uint16_t __io entry;
1445 struct npc_mcam_shift_entry_req {
1446 struct mbox_msghdr hdr;
1447 #define NPC_MCAM_MAX_SHIFTS 64
1448 uint16_t __io curr_entry[NPC_MCAM_MAX_SHIFTS];
1449 uint16_t __io new_entry[NPC_MCAM_MAX_SHIFTS];
1450 uint16_t __io shift_count; /* Number of entries to shift */
1453 struct npc_mcam_shift_entry_rsp {
1454 struct mbox_msghdr hdr;
1455 /* Index in 'curr_entry', not entry itself */
1456 uint16_t __io failed_entry_idx;
1459 struct npc_mcam_alloc_counter_req {
1460 struct mbox_msghdr hdr;
1461 uint8_t __io contig; /* Contiguous counters ? */
1462 #define NPC_MAX_NONCONTIG_COUNTERS 64
1463 uint16_t __io count; /* Number of counters requested */
1466 struct npc_mcam_alloc_counter_rsp {
1467 struct mbox_msghdr hdr;
1468 /* Counter alloc'ed or start idx if contiguous.
1469 * Invalid in case of non-contiguous.
1472 uint16_t __io count; /* Number of counters allocated */
1473 uint16_t __io cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1476 struct npc_mcam_oper_counter_req {
1477 struct mbox_msghdr hdr;
1478 uint16_t __io cntr; /* Free a counter or clear/fetch it's stats */
1481 struct npc_mcam_oper_counter_rsp {
1482 struct mbox_msghdr hdr;
1483 /* valid only while fetching counter's stats */
1487 struct npc_mcam_unmap_counter_req {
1488 struct mbox_msghdr hdr;
1490 uint16_t __io entry; /* Entry and counter to be unmapped */
1491 uint8_t __io all; /* Unmap all entries using this counter ? */
1494 struct npc_mcam_alloc_and_write_entry_req {
1495 struct mbox_msghdr hdr;
1496 struct mcam_entry entry_data;
1497 uint16_t __io ref_entry;
1498 uint8_t __io priority; /* Lower or higher w.r.t ref_entry */
1499 uint8_t __io intf; /* Rx or Tx interface */
1500 uint8_t __io enable_entry; /* Enable this MCAM entry ? */
1501 uint8_t __io alloc_cntr; /* Allocate counter and map ? */
1504 struct npc_mcam_alloc_and_write_entry_rsp {
1505 struct mbox_msghdr hdr;
1506 uint16_t __io entry;
1510 struct npc_get_kex_cfg_rsp {
1511 struct mbox_msghdr hdr;
1512 uint64_t __io rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1513 uint64_t __io tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1514 #define NPC_MAX_INTF 2
1515 #define NPC_MAX_LID 8
1516 #define NPC_MAX_LT 16
1517 #define NPC_MAX_LD 2
1518 #define NPC_MAX_LFL 16
1519 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1520 uint64_t __io kex_ld_flags[NPC_MAX_LD];
1521 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1522 uint64_t __io intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT]
1524 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1525 uint64_t __io intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1526 #define MKEX_NAME_LEN 128
1527 uint8_t __io mkex_pfl_name[MKEX_NAME_LEN];
1530 enum header_fields {
1545 NPC_HEADER_FIELDS_MAX,
1549 unsigned char __io dmac[6];
1550 unsigned char __io smac[6];
1551 uint16_t __io etype;
1552 uint16_t __io vlan_etype;
1553 uint16_t __io vlan_tci;
1555 uint32_t __io ip4src;
1556 uint32_t __io ip6src[4];
1559 uint32_t __io ip4dst;
1560 uint32_t __io ip6dst[4];
1563 uint8_t __io ip_ver;
1564 uint8_t __io ip_proto;
1566 uint16_t __io sport;
1567 uint16_t __io dport;
1570 struct npc_install_flow_req {
1571 struct mbox_msghdr hdr;
1572 struct flow_msg packet;
1573 struct flow_msg mask;
1574 uint64_t __io features;
1575 uint16_t __io entry;
1576 uint16_t __io channel;
1578 uint8_t __io set_cntr;
1579 uint8_t __io default_rule;
1580 /* Overwrite(0) or append(1) flow to default rule? */
1581 uint8_t __io append;
1584 uint32_t __io index;
1585 uint16_t __io match_id;
1586 uint8_t __io flow_key_alg;
1589 uint8_t __io vtag0_type;
1590 uint8_t __io vtag0_valid;
1591 uint8_t __io vtag1_type;
1592 uint8_t __io vtag1_valid;
1594 /* vtag tx action */
1595 uint16_t __io vtag0_def;
1596 uint8_t __io vtag0_op;
1597 uint16_t __io vtag1_def;
1598 uint8_t __io vtag1_op;
1601 struct npc_install_flow_rsp {
1602 struct mbox_msghdr hdr;
1603 /* Negative if no counter else counter number */
1607 struct npc_delete_flow_req {
1608 struct mbox_msghdr hdr;
1609 uint16_t __io entry;
1610 uint16_t __io start; /*Disable range of entries */
1612 uint8_t __io all; /* PF + VFs */
1615 struct npc_mcam_read_entry_req {
1616 struct mbox_msghdr hdr;
1617 /* MCAM entry to read */
1618 uint16_t __io entry;
1621 struct npc_mcam_read_entry_rsp {
1622 struct mbox_msghdr hdr;
1623 struct mcam_entry entry_data;
1625 uint8_t __io enable;
1628 struct npc_mcam_read_base_rule_rsp {
1629 struct mbox_msghdr hdr;
1630 struct mcam_entry entry_data;
1633 struct npc_mcam_get_stats_req {
1634 struct mbox_msghdr hdr;
1635 uint16_t __io entry; /* mcam entry */
1638 struct npc_mcam_get_stats_rsp {
1639 struct mbox_msghdr hdr;
1640 uint64_t __io stat; /* counter stats */
1641 uint8_t __io stat_ena; /* enabled */
1644 /* TIM mailbox error codes
1647 enum tim_af_status {
1648 TIM_AF_NO_RINGS_LEFT = -801,
1649 TIM_AF_INVALID_NPA_PF_FUNC = -802,
1650 TIM_AF_INVALID_SSO_PF_FUNC = -803,
1651 TIM_AF_RING_STILL_RUNNING = -804,
1652 TIM_AF_LF_INVALID = -805,
1653 TIM_AF_CSIZE_NOT_ALIGNED = -806,
1654 TIM_AF_CSIZE_TOO_SMALL = -807,
1655 TIM_AF_CSIZE_TOO_BIG = -808,
1656 TIM_AF_INTERVAL_TOO_SMALL = -809,
1657 TIM_AF_INVALID_BIG_ENDIAN_VALUE = -810,
1658 TIM_AF_INVALID_CLOCK_SOURCE = -811,
1659 TIM_AF_GPIO_CLK_SRC_NOT_ENABLED = -812,
1660 TIM_AF_INVALID_BSIZE = -813,
1661 TIM_AF_INVALID_ENABLE_PERIODIC = -814,
1662 TIM_AF_INVALID_ENABLE_DONTFREE = -815,
1663 TIM_AF_ENA_DONTFRE_NSET_PERIODIC = -816,
1664 TIM_AF_RING_ALREADY_DISABLED = -817,
1668 TIM_CLK_SRCS_TENNS = 0,
1669 TIM_CLK_SRCS_GPIO = 1,
1670 TIM_CLK_SRCS_GTI = 2,
1671 TIM_CLK_SRCS_PTP = 3,
1672 TIM_CLK_SRSC_INVALID,
1675 enum tim_gpio_edge {
1676 TIM_GPIO_NO_EDGE = 0,
1677 TIM_GPIO_LTOH_TRANS = 1,
1678 TIM_GPIO_HTOL_TRANS = 2,
1679 TIM_GPIO_BOTH_TRANS = 3,
1684 PTP_OP_ADJFINE = 0, /* adjfine(req.scaled_ppm); */
1685 PTP_OP_GET_CLOCK = 1, /* rsp.clk = get_clock() */
1689 struct mbox_msghdr hdr;
1691 int64_t __io scaled_ppm;
1692 uint8_t __io is_pmu;
1696 struct mbox_msghdr hdr;
1701 struct get_hw_cap_rsp {
1702 struct mbox_msghdr hdr;
1703 /* Schq mapping fixed or flexible */
1704 uint8_t __io nix_fixed_txschq_mapping;
1705 uint8_t __io nix_shaping; /* Is shaping and coloring supported */
1708 struct ndc_sync_op {
1709 struct mbox_msghdr hdr;
1710 uint8_t __io nix_lf_tx_sync;
1711 uint8_t __io nix_lf_rx_sync;
1712 uint8_t __io npa_lf_sync;
1715 struct tim_lf_alloc_req {
1716 struct mbox_msghdr hdr;
1718 uint16_t __io npa_pf_func;
1719 uint16_t __io sso_pf_func;
1722 struct tim_ring_req {
1723 struct mbox_msghdr hdr;
1727 struct tim_config_req {
1728 struct mbox_msghdr hdr;
1730 uint8_t __io bigendian;
1731 uint8_t __io clocksource;
1732 uint8_t __io enableperiodic;
1733 uint8_t __io enabledontfreebuffer;
1734 uint32_t __io bucketsize;
1735 uint32_t __io chunksize;
1736 uint32_t __io interval;
1737 uint8_t __io gpioedge;
1740 struct tim_lf_alloc_rsp {
1741 struct mbox_msghdr hdr;
1742 uint64_t __io tenns_clk;
1745 struct tim_enable_rsp {
1746 struct mbox_msghdr hdr;
1747 uint64_t __io timestarted;
1748 uint32_t __io currentbucket;
1751 struct sdp_node_info {
1752 /* Node to which this PF belons to */
1753 uint8_t __io node_id;
1754 uint8_t __io max_vfs;
1755 uint8_t __io num_pf_rings;
1756 uint8_t __io pf_srn;
1757 #define SDP_MAX_VFS 128
1758 uint8_t __io vf_rings[SDP_MAX_VFS];
1761 struct sdp_chan_info_msg {
1762 struct mbox_msghdr hdr;
1763 struct sdp_node_info info;
1766 #endif /* __ROC_MBOX_H__ */