1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
12 /* Device memory does not support unaligned access, instruct compiler to
13 * not optimize the memory access when working with mailbox memory.
17 /* Header which precedes all mbox messages */
19 uint64_t __io msg_size; /* Total msgs size embedded */
20 uint16_t __io num_msgs; /* No of msgs embedded */
23 /* Header which precedes every msg and is also part of it */
25 uint16_t __io pcifunc; /* Who's sending this msg */
26 uint16_t __io id; /* Mbox message ID */
27 #define MBOX_REQ_SIG (0xdead)
28 #define MBOX_RSP_SIG (0xbeef)
29 /* Signature, for validating corrupted msgs */
31 #define MBOX_VERSION (0x000b)
32 /* Version of msg's structure for this ID */
34 /* Offset of next msg within mailbox region */
35 uint16_t __io next_msgoff;
36 int __io rc; /* Msg processed response code */
39 /* Mailbox message types */
40 #define MBOX_MSG_MASK 0xFFFF
41 #define MBOX_MSG_INVALID 0xFFFE
42 #define MBOX_MSG_MAX 0xFFFF
44 #define MBOX_MESSAGES \
45 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
46 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
47 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach_req, msg_rsp) \
48 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach_req, msg_rsp) \
49 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
50 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
51 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
52 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
53 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
54 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
55 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
57 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
58 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
59 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
60 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
61 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
62 cgx_mac_addr_set_or_get) \
63 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
64 cgx_mac_addr_set_or_get) \
65 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
66 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
67 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
68 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
69 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, \
71 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
72 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
73 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
74 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
75 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
77 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
78 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
79 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
80 cgx_mac_addr_add_rsp) \
81 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
83 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
84 cgx_max_dmac_entries_get_rsp) \
85 M(CGX_SET_LINK_STATE, 0x214, cgx_set_link_state, \
86 cgx_set_link_state_msg, msg_rsp) \
87 M(CGX_GET_PHY_MOD_TYPE, 0x215, cgx_get_phy_mod_type, msg_req, \
89 M(CGX_SET_PHY_MOD_TYPE, 0x216, cgx_set_phy_mod_type, cgx_phy_mod_type, \
91 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
92 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req, \
93 cgx_set_link_mode_rsp) \
94 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, \
96 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \
97 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
98 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \
100 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
101 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, npa_lf_alloc_req, \
103 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
104 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
105 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, \
107 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
108 M(SSO_LF_ALLOC, 0x600, sso_lf_alloc, sso_lf_alloc_req, \
110 M(SSO_LF_FREE, 0x601, sso_lf_free, sso_lf_free_req, msg_rsp) \
111 M(SSOW_LF_ALLOC, 0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp) \
112 M(SSOW_LF_FREE, 0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp) \
113 M(SSO_HW_SETCONFIG, 0x604, sso_hw_setconfig, sso_hw_setconfig, \
115 M(SSO_GRP_SET_PRIORITY, 0x605, sso_grp_set_priority, sso_grp_priority, \
117 M(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req, \
119 M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp) \
120 M(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg, \
122 M(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req, \
124 M(SSO_HWS_GET_STATS, 0x610, sso_hws_get_stats, sso_info_req, \
126 M(SSO_HW_RELEASE_XAQ, 0x611, sso_hw_release_xaq_aura, \
127 sso_hw_xaq_release, msg_rsp) \
128 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
129 M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \
131 M(TIM_LF_FREE, 0x801, tim_lf_free, tim_ring_req, msg_rsp) \
132 M(TIM_CONFIG_RING, 0x802, tim_config_ring, tim_config_req, msg_rsp) \
133 M(TIM_ENABLE_RING, 0x803, tim_enable_ring, tim_ring_req, \
135 M(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \
136 M(TIM_GET_MIN_INTVL, 0x805, tim_get_min_intvl, tim_intvl_req, \
138 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
139 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, msg_rsp) \
140 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
141 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
143 M(CPT_SET_CRYPTO_GRP, 0xA03, cpt_set_crypto_grp, \
144 cpt_set_crypto_grp_req_msg, msg_rsp) \
145 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
146 cpt_inline_ipsec_cfg_msg, msg_rsp) \
147 M(CPT_STATS, 0xA05, cpt_sts_get, cpt_sts_req, cpt_sts_rsp) \
148 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
150 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \
151 M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \
152 cpt_rx_inline_lf_cfg_msg, msg_rsp) \
153 M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg) \
154 M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req, \
156 /* REE mbox IDs (range 0xE00 - 0xFFF) */ \
157 M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, msg_rsp) \
158 M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg, \
160 M(REE_RULE_DB_PROG, 0xE03, ree_rule_db_prog, ree_rule_db_prog_req_msg, \
162 M(REE_RULE_DB_LEN_GET, 0xE04, ree_rule_db_len_get, ree_req_msg, \
163 ree_rule_db_len_rsp_msg) \
164 M(REE_RULE_DB_GET, 0xE05, ree_rule_db_get, ree_rule_db_get_req_msg, \
165 ree_rule_db_get_rsp_msg) \
166 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
167 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, \
169 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
170 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, \
171 npc_mcam_alloc_entry_req, npc_mcam_alloc_entry_rsp) \
172 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
173 npc_mcam_free_entry_req, msg_rsp) \
174 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
175 npc_mcam_write_entry_req, msg_rsp) \
176 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
177 npc_mcam_ena_dis_entry_req, msg_rsp) \
178 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
179 npc_mcam_ena_dis_entry_req, msg_rsp) \
180 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, \
181 npc_mcam_shift_entry_req, npc_mcam_shift_entry_rsp) \
182 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
183 npc_mcam_alloc_counter_req, npc_mcam_alloc_counter_rsp) \
184 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
185 npc_mcam_oper_counter_req, msg_rsp) \
186 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
187 npc_mcam_unmap_counter_req, msg_rsp) \
188 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
189 npc_mcam_oper_counter_req, msg_rsp) \
190 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
191 npc_mcam_oper_counter_req, npc_mcam_oper_counter_rsp) \
192 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, \
193 npc_mcam_alloc_and_write_entry, npc_mcam_alloc_and_write_entry_req, \
194 npc_mcam_alloc_and_write_entry_rsp) \
195 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, msg_req, \
196 npc_get_kex_cfg_rsp) \
197 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, npc_install_flow_req, \
198 npc_install_flow_rsp) \
199 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, npc_delete_flow_req, \
201 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
202 npc_mcam_read_entry_req, npc_mcam_read_entry_rsp) \
203 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, npc_set_pkind, msg_rsp) \
204 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, msg_req, \
205 npc_mcam_read_base_rule_rsp) \
206 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
207 npc_mcam_get_stats_req, npc_mcam_get_stats_rsp) \
208 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
209 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, nix_lf_alloc_req, \
211 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
212 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
213 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, hwctx_disable_req, \
215 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, nix_txsch_alloc_req, \
216 nix_txsch_alloc_rsp) \
217 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
218 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
220 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
221 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
222 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
223 nix_rss_flowkey_cfg, nix_rss_flowkey_cfg_rsp) \
224 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, \
226 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
227 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
228 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
229 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
230 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
231 nix_mark_format_cfg, nix_mark_format_cfg_rsp) \
232 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
233 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, nix_lso_format_cfg, \
234 nix_lso_format_cfg_rsp) \
235 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, \
237 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, \
239 M(NIX_SET_VLAN_TPID, 0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid, \
241 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
243 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
244 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, \
245 nix_get_mac_addr_rsp) \
246 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
247 nix_inline_ipsec_cfg, msg_rsp) \
248 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \
249 nix_inline_ipsec_lf_cfg, msg_rsp) \
250 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
251 nix_cn10k_aq_enq_rsp) \
252 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \
253 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, \
254 nix_bandprof_alloc_req, nix_bandprof_alloc_rsp) \
255 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
257 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
258 nix_bandprof_get_hwinfo_rsp) \
259 M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \
261 M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \
264 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
265 #define MBOX_UP_CGX_MESSAGES \
266 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) \
267 M(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, msg_rsp)
270 #define M(_name, _id, _1, _2, _3) MBOX_MSG_##_name = _id,
271 MBOX_MESSAGES MBOX_UP_CGX_MESSAGES
275 /* Mailbox message formats */
277 #define RVU_DEFAULT_PF_FUNC 0xFFFF
279 /* Generic request msg used for those mbox messages which
280 * don't send any data in the request.
283 struct mbox_msghdr hdr;
286 /* Generic response msg used a ack or response for those mbox
287 * messages which does not have a specific rsp msg format.
290 struct mbox_msghdr hdr;
293 /* RVU mailbox error codes
297 RVU_INVALID_VF_ID = -256,
300 struct ready_msg_rsp {
301 struct mbox_msghdr hdr;
302 uint16_t __io sclk_freq; /* SCLK frequency */
303 uint16_t __io rclk_freq; /* RCLK frequency */
306 enum npc_pkind_type {
307 NPC_RX_CUSTOM_PRE_L2_PKIND = 55ULL,
308 NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
309 NPC_RX_CHLEN24B_PKIND,
310 NPC_RX_CPT_HDR_PKIND,
311 NPC_RX_CHLEN90B_PKIND,
319 /* Struct to set pkind */
320 struct npc_set_pkind {
321 struct mbox_msghdr hdr;
322 #define ROC_PRIV_FLAGS_DEFAULT BIT_ULL(0)
323 #define ROC_PRIV_FLAGS_EDSA BIT_ULL(1)
324 #define ROC_PRIV_FLAGS_HIGIG BIT_ULL(2)
325 #define ROC_PRIV_FLAGS_LEN_90B BIT_ULL(3)
326 #define ROC_PRIV_FLAGS_EXDSA BIT_ULL(4)
327 #define ROC_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5)
328 #define ROC_PRIV_FLAGS_PRE_L2 BIT_ULL(6)
329 #define ROC_PRIV_FLAGS_CUSTOM BIT_ULL(63)
331 #define PKIND_TX BIT_ULL(0)
332 #define PKIND_RX BIT_ULL(1)
334 uint8_t __io pkind; /* valid only in case custom flag */
335 uint8_t __io var_len_off;
336 /* Offset of custom header length field.
337 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
339 uint8_t __io var_len_off_mask; /* Mask for length with in offset */
340 uint8_t __io shift_dir;
341 /* Shift direction to get length of the
342 * header at var_len_off
346 /* Structure for requesting resource provisioning.
347 * 'modify' flag to be used when either requesting more
348 * or to detach partial of a certain resource type.
349 * Rest of the fields specify how many of what type to
351 * To request LFs from two blocks of same type this mailbox
352 * can be sent twice as below:
353 * struct rsrc_attach *attach;
354 * .. Allocate memory for message ..
355 * attach->cptlfs = 3; <3 LFs from CPT0>
357 * .. Allocate memory for message ..
358 * attach->modify = 1;
359 * attach->cpt_blkaddr = BLKADDR_CPT1;
360 * attach->cptlfs = 2; <2 LFs from CPT1>
363 struct rsrc_attach_req {
364 struct mbox_msghdr hdr;
365 uint8_t __io modify : 1;
366 uint8_t __io npalf : 1;
367 uint8_t __io nixlf : 1;
370 uint16_t __io timlfs;
371 uint16_t __io cptlfs;
372 uint16_t __io reelfs;
373 /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
374 int __io cpt_blkaddr;
375 /* BLKADDR_REE0/BLKADDR_REE1 or 0 for BLKADDR_REE0 */
376 int __io ree_blkaddr;
379 /* Structure for relinquishing resources.
380 * 'partial' flag to be used when relinquishing all resources
381 * but only of a certain type. If not set, all resources of all
382 * types provisioned to the RVU function will be detached.
384 struct rsrc_detach_req {
385 struct mbox_msghdr hdr;
386 uint8_t __io partial : 1;
387 uint8_t __io npalf : 1;
388 uint8_t __io nixlf : 1;
389 uint8_t __io sso : 1;
390 uint8_t __io ssow : 1;
391 uint8_t __io timlfs : 1;
392 uint8_t __io cptlfs : 1;
393 uint8_t __io reelfs : 1;
396 /* NIX Transmit schedulers */
397 #define NIX_TXSCH_LVL_SMQ 0x0
398 #define NIX_TXSCH_LVL_MDQ 0x0
399 #define NIX_TXSCH_LVL_TL4 0x1
400 #define NIX_TXSCH_LVL_TL3 0x2
401 #define NIX_TXSCH_LVL_TL2 0x3
402 #define NIX_TXSCH_LVL_TL1 0x4
403 #define NIX_TXSCH_LVL_CNT 0x5
406 * Number of resources available to the caller.
407 * In reply to MBOX_MSG_FREE_RSRC_CNT.
409 struct free_rsrcs_rsp {
410 struct mbox_msghdr hdr;
411 uint16_t __io schq[NIX_TXSCH_LVL_CNT];
418 uint16_t __io schq_nix1[NIX_TXSCH_LVL_CNT];
425 #define MSIX_VECTOR_INVALID 0xFFFF
426 #define MAX_RVU_BLKLF_CNT 256
428 struct msix_offset_rsp {
429 struct mbox_msghdr hdr;
430 uint16_t __io npa_msixoff;
431 uint16_t __io nix_msixoff;
434 uint16_t __io timlfs;
435 uint16_t __io cptlfs;
436 uint16_t __io sso_msixoff[MAX_RVU_BLKLF_CNT];
437 uint16_t __io ssow_msixoff[MAX_RVU_BLKLF_CNT];
438 uint16_t __io timlf_msixoff[MAX_RVU_BLKLF_CNT];
439 uint16_t __io cptlf_msixoff[MAX_RVU_BLKLF_CNT];
440 uint16_t __io cpt1_lfs;
441 uint16_t __io ree0_lfs;
442 uint16_t __io ree1_lfs;
443 uint16_t __io cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
444 uint16_t __io ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
445 uint16_t __io ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
448 struct lmtst_tbl_setup_req {
449 struct mbox_msghdr hdr;
451 uint64_t __io dis_sched_early_comp : 1;
452 uint64_t __io sched_ena : 1;
453 uint64_t __io dis_line_pref : 1;
454 uint64_t __io ssow_pf_func : 13;
455 uint16_t __io pcifunc;
456 uint8_t __io use_local_lmt_region;
457 uint64_t __io lmt_iova;
458 uint64_t __io rsvd[2]; /* Future use */
461 /* CGX mbox message formats */
463 struct cgx_stats_rsp {
464 struct mbox_msghdr hdr;
465 #define CGX_RX_STATS_COUNT 13
466 #define CGX_TX_STATS_COUNT 18
467 uint64_t __io rx_stats[CGX_RX_STATS_COUNT];
468 uint64_t __io tx_stats[CGX_TX_STATS_COUNT];
471 struct rpm_stats_rsp {
472 struct mbox_msghdr hdr;
473 #define RPM_RX_STATS_COUNT 43
474 #define RPM_TX_STATS_COUNT 34
475 uint64_t __io rx_stats[RPM_RX_STATS_COUNT];
476 uint64_t __io tx_stats[RPM_TX_STATS_COUNT];
479 struct cgx_fec_stats_rsp {
480 struct mbox_msghdr hdr;
481 uint64_t __io fec_corr_blks;
482 uint64_t __io fec_uncorr_blks;
485 /* Structure for requesting the operation for
486 * setting/getting mac address in the CGX interface
488 struct cgx_mac_addr_set_or_get {
489 struct mbox_msghdr hdr;
490 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
493 /* Structure for requesting the operation to
494 * add DMAC filter entry into CGX interface
496 struct cgx_mac_addr_add_req {
497 struct mbox_msghdr hdr;
498 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
501 /* Structure for response against the operation to
502 * add DMAC filter entry into CGX interface
504 struct cgx_mac_addr_add_rsp {
505 struct mbox_msghdr hdr;
509 /* Structure for requesting the operation to
510 * delete DMAC filter entry from CGX interface
512 struct cgx_mac_addr_del_req {
513 struct mbox_msghdr hdr;
517 /* Structure for response against the operation to
518 * get maximum supported DMAC filter entries
520 struct cgx_max_dmac_entries_get_rsp {
521 struct mbox_msghdr hdr;
522 uint8_t __io max_dmac_filters;
525 struct cgx_link_user_info {
526 uint64_t __io link_up : 1;
527 uint64_t __io full_duplex : 1;
528 uint64_t __io lmac_type_id : 4;
529 uint64_t __io speed : 20; /* speed in Mbps */
530 uint64_t __io an : 1; /* AN supported or not */
531 uint64_t __io fec : 2; /* FEC type if enabled else 0 */
532 uint64_t __io port : 8;
533 #define LMACTYPE_STR_LEN 16
534 char lmac_type[LMACTYPE_STR_LEN];
537 struct cgx_link_info_msg {
538 struct mbox_msghdr hdr;
539 struct cgx_link_user_info link_info;
542 struct cgx_ptp_rx_info_msg {
543 struct mbox_msghdr hdr;
547 struct cgx_pause_frm_cfg {
548 struct mbox_msghdr hdr;
550 /* set = 1 if the request is to config pause frames */
551 /* set = 0 if the request is to fetch pause frames config */
552 uint8_t __io rx_pause;
553 uint8_t __io tx_pause;
557 struct mbox_msghdr hdr;
558 uint8_t __io rx_pause;
559 uint8_t __io tx_pause;
560 uint16_t __io pfc_en; /* bitmap indicating enabled traffic classes */
564 struct mbox_msghdr hdr;
565 uint8_t __io rx_pause;
566 uint8_t __io tx_pause;
569 struct sfp_eeprom_s {
570 #define SFP_EEPROM_SIZE 256
571 uint16_t __io sff_id;
572 uint8_t __io buf[SFP_EEPROM_SIZE];
573 uint64_t __io reserved;
583 uint64_t __io can_change_mod_type : 1;
584 uint64_t __io mod_type : 1;
587 struct cgx_lmac_fwdata_s {
588 uint16_t __io rw_valid;
589 uint64_t __io supported_fec;
590 uint64_t __io supported_an;
591 uint64_t __io supported_link_modes;
592 /* Only applicable if AN is supported */
593 uint64_t __io advertised_fec;
594 uint64_t __io advertised_link_modes;
595 /* Only applicable if SFP/QSFP slot is present */
596 struct sfp_eeprom_s sfp_eeprom;
598 #define LMAC_FWDATA_RESERVED_MEM 1023
599 uint64_t __io reserved[LMAC_FWDATA_RESERVED_MEM];
603 struct mbox_msghdr hdr;
604 struct cgx_lmac_fwdata_s fwdata;
608 struct mbox_msghdr hdr;
612 struct cgx_set_link_state_msg {
613 struct mbox_msghdr hdr;
617 struct cgx_phy_mod_type {
618 struct mbox_msghdr hdr;
622 struct cgx_set_link_mode_args {
630 struct cgx_set_link_mode_req {
631 struct mbox_msghdr hdr;
632 struct cgx_set_link_mode_args args;
635 struct cgx_set_link_mode_rsp {
636 struct mbox_msghdr hdr;
640 /* NPA mbox message formats */
642 /* NPA mailbox error codes
646 NPA_AF_ERR_PARAM = -301,
647 NPA_AF_ERR_AQ_FULL = -302,
648 NPA_AF_ERR_AQ_ENQUEUE = -303,
649 NPA_AF_ERR_AF_LF_INVALID = -304,
650 NPA_AF_ERR_AF_LF_ALLOC = -305,
651 NPA_AF_ERR_LF_RESET = -306,
654 #define NPA_AURA_SZ_0 0
655 #define NPA_AURA_SZ_128 1
656 #define NPA_AURA_SZ_256 2
657 #define NPA_AURA_SZ_512 3
658 #define NPA_AURA_SZ_1K 4
659 #define NPA_AURA_SZ_2K 5
660 #define NPA_AURA_SZ_4K 6
661 #define NPA_AURA_SZ_8K 7
662 #define NPA_AURA_SZ_16K 8
663 #define NPA_AURA_SZ_32K 9
664 #define NPA_AURA_SZ_64K 10
665 #define NPA_AURA_SZ_128K 11
666 #define NPA_AURA_SZ_256K 12
667 #define NPA_AURA_SZ_512K 13
668 #define NPA_AURA_SZ_1M 14
669 #define NPA_AURA_SZ_MAX 15
671 /* For NPA LF context alloc and init */
672 struct npa_lf_alloc_req {
673 struct mbox_msghdr hdr;
675 int __io aura_sz; /* No of auras. See NPA_AURA_SZ_* */
676 uint32_t __io nr_pools; /* No of pools */
677 uint64_t __io way_mask;
680 struct npa_lf_alloc_rsp {
681 struct mbox_msghdr hdr;
682 uint32_t __io stack_pg_ptrs; /* No of ptrs per stack page */
683 uint32_t __io stack_pg_bytes; /* Size of stack page */
684 uint16_t __io qints; /* NPA_AF_CONST::QINTS */
685 uint8_t __io cache_lines; /* Batch Alloc DMA */
688 /* NPA AQ enqueue msg */
689 struct npa_aq_enq_req {
690 struct mbox_msghdr hdr;
691 uint32_t __io aura_id;
695 /* Valid when op == WRITE/INIT and ctype == AURA.
696 * LF fills the pool_id in aura.pool_addr. AF will translate
697 * the pool_id to pool context pointer.
699 __io struct npa_aura_s aura;
700 /* Valid when op == WRITE/INIT and ctype == POOL */
701 __io struct npa_pool_s pool;
703 /* Mask data when op == WRITE (1=write, 0=don't write) */
705 /* Valid when op == WRITE and ctype == AURA */
706 __io struct npa_aura_s aura_mask;
707 /* Valid when op == WRITE and ctype == POOL */
708 __io struct npa_pool_s pool_mask;
712 struct npa_aq_enq_rsp {
713 struct mbox_msghdr hdr;
715 /* Valid when op == READ and ctype == AURA */
716 __io struct npa_aura_s aura;
717 /* Valid when op == READ and ctype == POOL */
718 __io struct npa_pool_s pool;
722 /* Disable all contexts of type 'ctype' */
723 struct hwctx_disable_req {
724 struct mbox_msghdr hdr;
728 /* NIX mbox message formats */
730 /* NIX mailbox error codes
734 NIX_AF_ERR_PARAM = -401,
735 NIX_AF_ERR_AQ_FULL = -402,
736 NIX_AF_ERR_AQ_ENQUEUE = -403,
737 NIX_AF_ERR_AF_LF_INVALID = -404,
738 NIX_AF_ERR_AF_LF_ALLOC = -405,
739 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
740 NIX_AF_ERR_TLX_INVALID = -407,
741 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
742 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
743 NIX_AF_ERR_FRS_INVALID = -410,
744 NIX_AF_ERR_RX_LINK_INVALID = -411,
745 NIX_AF_INVAL_TXSCHQ_CFG = -412,
746 NIX_AF_SMQ_FLUSH_FAILED = -413,
747 NIX_AF_ERR_LF_RESET = -414,
748 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
749 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
750 NIX_AF_ERR_MARK_CFG_FAIL = -417,
751 NIX_AF_ERR_LSO_CFG_FAIL = -418,
752 NIX_AF_INVAL_NPA_PF_FUNC = -419,
753 NIX_AF_INVAL_SSO_PF_FUNC = -420,
754 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
755 NIX_AF_ERR_RX_VTAG_INUSE = -422,
756 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
759 /* For NIX LF context alloc and init */
760 struct nix_lf_alloc_req {
761 struct mbox_msghdr hdr;
763 uint32_t __io rq_cnt; /* No of receive queues */
764 uint32_t __io sq_cnt; /* No of send queues */
765 uint32_t __io cq_cnt; /* No of completion queues */
767 uint16_t __io rss_sz;
768 uint8_t __io rss_grps;
769 uint16_t __io npa_func;
770 /* RVU_DEFAULT_PF_FUNC == default pf_func associated with lf */
771 uint16_t __io sso_func;
772 uint64_t __io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
773 uint64_t __io way_mask;
774 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
775 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1)
779 struct nix_lf_alloc_rsp {
780 struct mbox_msghdr hdr;
781 uint16_t __io sqb_size;
782 uint16_t __io rx_chan_base;
783 uint16_t __io tx_chan_base;
784 uint8_t __io rx_chan_cnt; /* Total number of RX channels */
785 uint8_t __io tx_chan_cnt; /* Total number of TX channels */
786 uint8_t __io lso_tsov4_idx;
787 uint8_t __io lso_tsov6_idx;
788 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
789 uint8_t __io lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
790 uint8_t __io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
791 uint16_t __io cints; /* NIX_AF_CONST2::CINTS */
792 uint16_t __io qints; /* NIX_AF_CONST2::QINTS */
793 uint8_t __io hw_rx_tstamp_en; /*set if rx timestamping enabled */
794 uint8_t __io cgx_links; /* No. of CGX links present in HW */
795 uint8_t __io lbk_links; /* No. of LBK links present in HW */
796 uint8_t __io sdp_links; /* No. of SDP links present in HW */
797 uint8_t tx_link; /* Transmit channel link number */
800 struct nix_lf_free_req {
801 struct mbox_msghdr hdr;
802 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
803 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
807 /* CN10x NIX AQ enqueue msg */
808 struct nix_cn10k_aq_enq_req {
809 struct mbox_msghdr hdr;
814 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
815 __io struct nix_cn10k_rq_ctx_s rq;
816 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
817 __io struct nix_cn10k_sq_ctx_s sq;
818 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
819 __io struct nix_cq_ctx_s cq;
820 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
821 __io struct nix_rsse_s rss;
822 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
823 __io struct nix_rx_mce_s mce;
824 /* Valid when op == WRITE/INIT and
825 * ctype == NIX_AQ_CTYPE_BAND_PROF
827 __io struct nix_band_prof_s prof;
829 /* Mask data when op == WRITE (1=write, 0=don't write) */
831 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
832 __io struct nix_cn10k_rq_ctx_s rq_mask;
833 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
834 __io struct nix_cn10k_sq_ctx_s sq_mask;
835 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
836 __io struct nix_cq_ctx_s cq_mask;
837 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
838 __io struct nix_rsse_s rss_mask;
839 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
840 __io struct nix_rx_mce_s mce_mask;
841 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_BAND_PROF */
842 __io struct nix_band_prof_s prof_mask;
846 struct nix_cn10k_aq_enq_rsp {
847 struct mbox_msghdr hdr;
849 struct nix_cn10k_rq_ctx_s rq;
850 struct nix_cn10k_sq_ctx_s sq;
851 struct nix_cq_ctx_s cq;
852 struct nix_rsse_s rss;
853 struct nix_rx_mce_s mce;
854 struct nix_band_prof_s prof;
858 /* NIX AQ enqueue msg */
859 struct nix_aq_enq_req {
860 struct mbox_msghdr hdr;
865 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
866 __io struct nix_rq_ctx_s rq;
867 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
868 __io struct nix_sq_ctx_s sq;
869 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
870 __io struct nix_cq_ctx_s cq;
871 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
872 __io struct nix_rsse_s rss;
873 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
874 __io struct nix_rx_mce_s mce;
876 /* Mask data when op == WRITE (1=write, 0=don't write) */
878 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
879 __io struct nix_rq_ctx_s rq_mask;
880 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
881 __io struct nix_sq_ctx_s sq_mask;
882 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
883 __io struct nix_cq_ctx_s cq_mask;
884 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
885 __io struct nix_rsse_s rss_mask;
886 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
887 __io struct nix_rx_mce_s mce_mask;
891 struct nix_aq_enq_rsp {
892 struct mbox_msghdr hdr;
894 __io struct nix_rq_ctx_s rq;
895 __io struct nix_sq_ctx_s sq;
896 __io struct nix_cq_ctx_s cq;
897 __io struct nix_rsse_s rss;
898 __io struct nix_rx_mce_s mce;
902 /* Tx scheduler/shaper mailbox messages */
904 #define MAX_TXSCHQ_PER_FUNC 128
906 struct nix_txsch_alloc_req {
907 struct mbox_msghdr hdr;
908 /* Scheduler queue count request at each level */
909 uint16_t __io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
910 uint16_t __io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
913 struct nix_txsch_alloc_rsp {
914 struct mbox_msghdr hdr;
915 /* Scheduler queue count allocated at each level */
916 uint16_t __io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
917 uint16_t __io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
918 /* Scheduler queue list allocated at each level */
919 uint16_t __io schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
920 uint16_t __io schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
921 /* Traffic aggregation scheduler level */
922 uint8_t __io aggr_level;
923 /* Aggregation lvl's RR_PRIO config */
924 uint8_t __io aggr_lvl_rr_prio;
925 /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
926 uint8_t __io link_cfg_lvl;
929 struct nix_txsch_free_req {
930 struct mbox_msghdr hdr;
931 #define TXSCHQ_FREE_ALL BIT_ULL(0)
933 /* Scheduler queue level to be freed */
934 uint16_t __io schq_lvl;
935 /* List of scheduler queues to be freed */
939 struct nix_txschq_config {
940 struct mbox_msghdr hdr;
941 uint8_t __io lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
943 #define TXSCHQ_IDX_SHIFT 16
944 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
945 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
946 uint8_t __io num_regs;
947 #define MAX_REGS_PER_MBOX_MSG 20
948 uint64_t __io reg[MAX_REGS_PER_MBOX_MSG];
949 uint64_t __io regval[MAX_REGS_PER_MBOX_MSG];
950 /* All 0's => overwrite with new value */
951 uint64_t __io regval_mask[MAX_REGS_PER_MBOX_MSG];
954 struct nix_vtag_config {
955 struct mbox_msghdr hdr;
956 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
957 uint8_t __io vtag_size;
958 /* cfg_type is '0' for tx vlan cfg
959 * cfg_type is '1' for rx vlan cfg
961 uint8_t __io cfg_type;
963 /* Valid when cfg_type is '0' */
968 /* cfg_vtag0 & cfg_vtag1 fields are valid
969 * when free_vtag0 & free_vtag1 are '0's.
971 /* cfg_vtag0 = 1 to configure vtag0 */
972 uint8_t __io cfg_vtag0 : 1;
973 /* cfg_vtag1 = 1 to configure vtag1 */
974 uint8_t __io cfg_vtag1 : 1;
976 /* vtag0_idx & vtag1_idx are only valid when
977 * both cfg_vtag0 & cfg_vtag1 are '0's,
978 * these fields are used along with free_vtag0
979 * & free_vtag1 to free the nix lf's tx_vlan
982 * Denotes the indices of tx_vtag def registers
983 * that needs to be cleared and freed.
988 /* Free_vtag0 & free_vtag1 fields are valid
989 * when cfg_vtag0 & cfg_vtag1 are '0's.
991 /* Free_vtag0 = 1 clears vtag0 configuration
992 * vtag0_idx denotes the index to be cleared.
994 uint8_t __io free_vtag0 : 1;
995 /* Free_vtag1 = 1 clears vtag1 configuration
996 * vtag1_idx denotes the index to be cleared.
998 uint8_t __io free_vtag1 : 1;
1001 /* Valid when cfg_type is '1' */
1003 /* Rx vtag type index, valid values are in 0..7 range */
1004 uint8_t __io vtag_type;
1006 uint8_t __io strip_vtag : 1;
1007 /* Rx vtag capture */
1008 uint8_t __io capture_vtag : 1;
1013 struct nix_vtag_config_rsp {
1014 struct mbox_msghdr hdr;
1015 /* Indices of tx_vtag def registers used to configure
1016 * tx vtag0 & vtag1 headers, these indices are valid
1017 * when nix_vtag_config mbox requested for vtag0 and/
1018 * or vtag1 configuration.
1024 struct nix_rss_flowkey_cfg {
1025 struct mbox_msghdr hdr;
1026 int __io mcam_index; /* MCAM entry index to modify */
1027 uint32_t __io flowkey_cfg; /* Flowkey types selected */
1028 #define FLOW_KEY_TYPE_PORT BIT(0)
1029 #define FLOW_KEY_TYPE_IPV4 BIT(1)
1030 #define FLOW_KEY_TYPE_IPV6 BIT(2)
1031 #define FLOW_KEY_TYPE_TCP BIT(3)
1032 #define FLOW_KEY_TYPE_UDP BIT(4)
1033 #define FLOW_KEY_TYPE_SCTP BIT(5)
1034 #define FLOW_KEY_TYPE_NVGRE BIT(6)
1035 #define FLOW_KEY_TYPE_VXLAN BIT(7)
1036 #define FLOW_KEY_TYPE_GENEVE BIT(8)
1037 #define FLOW_KEY_TYPE_ETH_DMAC BIT(9)
1038 #define FLOW_KEY_TYPE_IPV6_EXT BIT(10)
1039 #define FLOW_KEY_TYPE_GTPU BIT(11)
1040 #define FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
1041 #define FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
1042 #define FLOW_KEY_TYPE_INNR_TCP BIT(14)
1043 #define FLOW_KEY_TYPE_INNR_UDP BIT(15)
1044 #define FLOW_KEY_TYPE_INNR_SCTP BIT(16)
1045 #define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
1046 #define FLOW_KEY_TYPE_CH_LEN_90B BIT(18)
1047 #define FLOW_KEY_TYPE_CUSTOM0 BIT(19)
1048 #define FLOW_KEY_TYPE_VLAN BIT(20)
1049 #define FLOW_KEY_TYPE_L4_DST BIT(28)
1050 #define FLOW_KEY_TYPE_L4_SRC BIT(29)
1051 #define FLOW_KEY_TYPE_L3_DST BIT(30)
1052 #define FLOW_KEY_TYPE_L3_SRC BIT(31)
1053 uint8_t __io group; /* RSS context or group */
1056 struct nix_rss_flowkey_cfg_rsp {
1057 struct mbox_msghdr hdr;
1058 uint8_t __io alg_idx; /* Selected algo index */
1061 struct nix_set_mac_addr {
1062 struct mbox_msghdr hdr;
1063 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
1066 struct nix_get_mac_addr_rsp {
1067 struct mbox_msghdr hdr;
1068 uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
1071 struct nix_mark_format_cfg {
1072 struct mbox_msghdr hdr;
1073 uint8_t __io offset;
1074 uint8_t __io y_mask;
1076 uint8_t __io r_mask;
1080 struct nix_mark_format_cfg_rsp {
1081 struct mbox_msghdr hdr;
1082 uint8_t __io mark_format_idx;
1085 struct nix_lso_format_cfg {
1086 struct mbox_msghdr hdr;
1087 uint64_t __io field_mask;
1088 uint64_t __io fields[NIX_LSO_FIELD_MAX];
1091 struct nix_lso_format_cfg_rsp {
1092 struct mbox_msghdr hdr;
1093 uint8_t __io lso_format_idx;
1096 struct nix_rx_mode {
1097 struct mbox_msghdr hdr;
1098 #define NIX_RX_MODE_UCAST BIT(0)
1099 #define NIX_RX_MODE_PROMISC BIT(1)
1100 #define NIX_RX_MODE_ALLMULTI BIT(2)
1105 struct mbox_msghdr hdr;
1106 #define NIX_RX_OL3_VERIFY BIT(0)
1107 #define NIX_RX_OL4_VERIFY BIT(1)
1108 #define NIX_RX_DROP_RE BIT(2)
1109 uint8_t __io len_verify; /* Outer L3/L4 len check */
1110 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1111 uint8_t __io csum_verify; /* Outer L4 checksum verification */
1114 struct nix_frs_cfg {
1115 struct mbox_msghdr hdr;
1116 uint8_t __io update_smq; /* Update SMQ's min/max lens */
1117 uint8_t __io update_minlen; /* Set minlen also */
1118 uint8_t __io sdp_link; /* Set SDP RX link */
1119 uint16_t __io maxlen;
1120 uint16_t __io minlen;
1123 struct nix_set_vlan_tpid {
1124 struct mbox_msghdr hdr;
1125 #define NIX_VLAN_TYPE_INNER 0
1126 #define NIX_VLAN_TYPE_OUTER 1
1127 uint8_t __io vlan_type;
1131 struct nix_bp_cfg_req {
1132 struct mbox_msghdr hdr;
1133 uint16_t __io chan_base; /* Starting channel number */
1134 uint8_t __io chan_cnt; /* Number of channels */
1135 uint8_t __io bpid_per_chan;
1136 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1137 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1140 /* PF can be mapped to either CGX or LBK interface,
1141 * so maximum 64 channels are possible.
1143 #define NIX_MAX_CHAN 64
1144 #define NIX_CGX_MAX_CHAN 16
1145 #define NIX_LBK_MAX_CHAN 1
1146 struct nix_bp_cfg_rsp {
1147 struct mbox_msghdr hdr;
1148 /* Channel and bpid mapping */
1149 uint16_t __io chan_bpid[NIX_MAX_CHAN];
1150 /* Number of channel for which bpids are assigned */
1151 uint8_t __io chan_cnt;
1154 /* Global NIX inline IPSec configuration */
1155 struct nix_inline_ipsec_cfg {
1156 struct mbox_msghdr hdr;
1157 uint32_t __io cpt_credit;
1160 uint8_t __io opcode;
1163 uint16_t __io cpt_pf_func;
1164 uint8_t __io cpt_slot;
1166 uint8_t __io enable;
1169 /* Per NIX LF inline IPSec configuration */
1170 struct nix_inline_ipsec_lf_cfg {
1171 struct mbox_msghdr hdr;
1172 uint64_t __io sa_base_addr;
1174 uint32_t __io tag_const;
1175 uint16_t __io lenm1_max;
1176 uint8_t __io sa_pow2_size;
1180 uint32_t __io sa_idx_max;
1181 uint8_t __io sa_idx_w;
1183 uint8_t __io enable;
1186 struct nix_hw_info {
1187 struct mbox_msghdr hdr;
1188 uint16_t __io vwqe_delay;
1189 uint16_t __io rsvd[15];
1192 struct nix_bandprof_alloc_req {
1193 struct mbox_msghdr hdr;
1194 /* Count of profiles needed per layer */
1195 uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX];
1198 struct nix_bandprof_alloc_rsp {
1199 struct mbox_msghdr hdr;
1200 uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX];
1202 #define BANDPROF_PER_PFFUNC 64
1203 uint16_t __io prof_idx[NIX_RX_BAND_PROF_LAYER_MAX][BANDPROF_PER_PFFUNC];
1206 struct nix_bandprof_free_req {
1207 struct mbox_msghdr hdr;
1208 uint8_t __io free_all;
1209 uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX];
1210 uint16_t __io prof_idx[NIX_RX_BAND_PROF_LAYER_MAX][BANDPROF_PER_PFFUNC];
1213 struct nix_bandprof_get_hwinfo_rsp {
1214 struct mbox_msghdr hdr;
1215 uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX];
1216 uint32_t __io policer_timeunit;
1219 /* SSO mailbox error codes
1222 enum sso_af_status {
1223 SSO_AF_ERR_PARAM = -501,
1224 SSO_AF_ERR_LF_INVALID = -502,
1225 SSO_AF_ERR_AF_LF_ALLOC = -503,
1226 SSO_AF_ERR_GRP_EBUSY = -504,
1227 SSO_AF_INVAL_NPA_PF_FUNC = -505,
1230 struct sso_lf_alloc_req {
1231 struct mbox_msghdr hdr;
1233 uint16_t __io hwgrps;
1236 struct sso_lf_alloc_rsp {
1237 struct mbox_msghdr hdr;
1238 uint32_t __io xaq_buf_size;
1239 uint32_t __io xaq_wq_entries;
1240 uint32_t __io in_unit_entries;
1241 uint16_t __io hwgrps;
1244 struct sso_lf_free_req {
1245 struct mbox_msghdr hdr;
1247 uint16_t __io hwgrps;
1250 /* SSOW mailbox error codes
1253 enum ssow_af_status {
1254 SSOW_AF_ERR_PARAM = -601,
1255 SSOW_AF_ERR_LF_INVALID = -602,
1256 SSOW_AF_ERR_AF_LF_ALLOC = -603,
1259 struct ssow_lf_alloc_req {
1260 struct mbox_msghdr hdr;
1265 struct ssow_lf_free_req {
1266 struct mbox_msghdr hdr;
1271 struct sso_hw_setconfig {
1272 struct mbox_msghdr hdr;
1273 uint32_t __io npa_aura_id;
1274 uint16_t __io npa_pf_func;
1275 uint16_t __io hwgrps;
1278 struct sso_hw_xaq_release {
1279 struct mbox_msghdr hdr;
1280 uint16_t __io hwgrps;
1283 struct sso_info_req {
1284 struct mbox_msghdr hdr;
1291 struct sso_grp_priority {
1292 struct mbox_msghdr hdr;
1294 uint8_t __io priority;
1295 uint8_t __io affinity;
1296 uint8_t __io weight;
1299 struct sso_grp_qos_cfg {
1300 struct mbox_msghdr hdr;
1302 uint32_t __io xaq_limit;
1303 uint16_t __io taq_thr;
1304 uint16_t __io iaq_thr;
1307 struct sso_grp_stats {
1308 struct mbox_msghdr hdr;
1310 uint64_t __io ws_pc;
1311 uint64_t __io ext_pc;
1312 uint64_t __io wa_pc;
1313 uint64_t __io ts_pc;
1314 uint64_t __io ds_pc;
1315 uint64_t __io dq_pc;
1316 uint64_t __io aw_status;
1317 uint64_t __io page_cnt;
1320 struct sso_hws_stats {
1321 struct mbox_msghdr hdr;
1323 uint64_t __io arbitration;
1326 /* CPT mailbox error codes
1329 enum cpt_af_status {
1330 CPT_AF_ERR_PARAM = -901,
1331 CPT_AF_ERR_GRP_INVALID = -902,
1332 CPT_AF_ERR_LF_INVALID = -903,
1333 CPT_AF_ERR_ACCESS_DENIED = -904,
1334 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1335 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1336 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1337 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1340 /* CPT mbox message formats */
1342 struct cpt_rd_wr_reg_msg {
1343 struct mbox_msghdr hdr;
1344 uint64_t __io reg_offset;
1345 uint64_t __io *ret_val;
1347 uint8_t __io is_write;
1350 struct cpt_set_crypto_grp_req_msg {
1351 struct mbox_msghdr hdr;
1352 uint8_t __io crypto_eng_grp;
1355 struct cpt_lf_alloc_req_msg {
1356 struct mbox_msghdr hdr;
1357 uint16_t __io nix_pf_func;
1358 uint16_t __io sso_pf_func;
1359 uint16_t __io eng_grpmsk;
1360 uint8_t __io blkaddr;
1363 #define CPT_INLINE_INBOUND 0
1364 #define CPT_INLINE_OUTBOUND 1
1366 struct cpt_inline_ipsec_cfg_msg {
1367 struct mbox_msghdr hdr;
1368 uint8_t __io enable;
1371 uint8_t __io sso_pf_func_ovrd;
1372 uint16_t __io sso_pf_func; /* Inbound path SSO_PF_FUNC */
1373 uint16_t __io nix_pf_func; /* Outbound path NIX_PF_FUNC */
1376 struct cpt_sts_req {
1377 struct mbox_msghdr hdr;
1378 uint8_t __io blkaddr;
1381 struct cpt_sts_rsp {
1382 struct mbox_msghdr hdr;
1383 uint64_t __io inst_req_pc;
1384 uint64_t __io inst_lat_pc;
1385 uint64_t __io rd_req_pc;
1386 uint64_t __io rd_lat_pc;
1387 uint64_t __io rd_uc_pc;
1388 uint64_t __io active_cycles_pc;
1389 uint64_t __io ctx_mis_pc;
1390 uint64_t __io ctx_hit_pc;
1391 uint64_t __io ctx_aop_pc;
1392 uint64_t __io ctx_aop_lat_pc;
1393 uint64_t __io ctx_ifetch_pc;
1394 uint64_t __io ctx_ifetch_lat_pc;
1395 uint64_t __io ctx_ffetch_pc;
1396 uint64_t __io ctx_ffetch_lat_pc;
1397 uint64_t __io ctx_wback_pc;
1398 uint64_t __io ctx_wback_lat_pc;
1399 uint64_t __io ctx_psh_pc;
1400 uint64_t __io ctx_psh_lat_pc;
1401 uint64_t __io ctx_err;
1402 uint64_t __io ctx_enc_id;
1403 uint64_t __io ctx_flush_timer;
1404 uint64_t __io rxc_time;
1405 uint64_t __io rxc_time_cfg;
1406 uint64_t __io rxc_active_sts;
1407 uint64_t __io rxc_zombie_sts;
1408 uint64_t __io busy_sts_ae;
1409 uint64_t __io free_sts_ae;
1410 uint64_t __io busy_sts_se;
1411 uint64_t __io free_sts_se;
1412 uint64_t __io busy_sts_ie;
1413 uint64_t __io free_sts_ie;
1414 uint64_t __io exe_err_info;
1415 uint64_t __io cptclk_cnt;
1417 uint64_t __io rxc_dfrg;
1418 uint64_t __io x2p_link_cfg0;
1419 uint64_t __io x2p_link_cfg1;
1422 struct cpt_rxc_time_cfg_req {
1423 struct mbox_msghdr hdr;
1426 uint16_t zombie_thres;
1427 uint16_t zombie_limit;
1428 uint16_t active_thres;
1429 uint16_t active_limit;
1432 struct cpt_rx_inline_lf_cfg_msg {
1433 struct mbox_msghdr hdr;
1434 uint16_t __io sso_pf_func;
1435 uint16_t __io param1;
1436 uint16_t __io param2;
1437 uint16_t __io reserved;
1441 CPT_ENG_TYPE_AE = 1,
1442 CPT_ENG_TYPE_SE = 2,
1443 CPT_ENG_TYPE_IE = 3,
1447 /* CPT HW capabilities */
1448 union cpt_eng_caps {
1451 uint64_t __io reserved_0_4 : 5;
1452 uint64_t __io mul : 1;
1453 uint64_t __io sha1_sha2 : 1;
1454 uint64_t __io chacha20 : 1;
1455 uint64_t __io zuc_snow3g : 1;
1456 uint64_t __io sha3 : 1;
1457 uint64_t __io aes : 1;
1458 uint64_t __io kasumi : 1;
1459 uint64_t __io des : 1;
1460 uint64_t __io crc : 1;
1461 uint64_t __io reserved_14_63 : 50;
1465 struct cpt_caps_rsp_msg {
1466 struct mbox_msghdr hdr;
1467 uint16_t __io cpt_pf_drv_version;
1468 uint8_t __io cpt_revision;
1469 union cpt_eng_caps eng_caps[CPT_MAX_ENG_TYPES];
1472 struct cpt_eng_grp_req {
1473 struct mbox_msghdr hdr;
1474 uint8_t __io eng_type;
1477 struct cpt_eng_grp_rsp {
1478 struct mbox_msghdr hdr;
1479 uint8_t __io eng_type;
1480 uint8_t __io eng_grp_num;
1483 /* REE mailbox error codes
1484 * Range 1001 - 1100.
1486 enum ree_af_status {
1487 REE_AF_ERR_RULE_UNKNOWN_VALUE = -1001,
1488 REE_AF_ERR_LF_NO_MORE_RESOURCES = -1002,
1489 REE_AF_ERR_LF_INVALID = -1003,
1490 REE_AF_ERR_ACCESS_DENIED = -1004,
1491 REE_AF_ERR_RULE_DB_PARTIAL = -1005,
1492 REE_AF_ERR_RULE_DB_EQ_BAD_VALUE = -1006,
1493 REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED = -1007,
1494 REE_AF_ERR_BLOCK_NOT_IMPLEMENTED = -1008,
1495 REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG = -1009,
1496 REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG = -1010,
1497 REE_AF_ERR_Q_IS_GRACEFUL_DIS = -1011,
1498 REE_AF_ERR_Q_NOT_GRACEFUL_DIS = -1012,
1499 REE_AF_ERR_RULE_DB_ALLOC_FAILED = -1013,
1500 REE_AF_ERR_RULE_DB_TOO_BIG = -1014,
1501 REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE = -1015,
1502 REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE = -1016,
1503 REE_AF_ERR_RULE_DB_WRONG_LENGTH = -1017,
1504 REE_AF_ERR_RULE_DB_WRONG_OFFSET = -1018,
1505 REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG = -1019,
1506 REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST = -1020,
1507 REE_AF_ERR_RULE_DBI_ALLOC_FAILED = -1021,
1508 REE_AF_ERR_LF_WRONG_PRIORITY = -1022,
1509 REE_AF_ERR_LF_SIZE_TOO_BIG = -1023,
1512 /* REE mbox message formats */
1514 struct ree_req_msg {
1515 struct mbox_msghdr hdr;
1516 uint32_t __io blkaddr;
1519 struct ree_lf_req_msg {
1520 struct mbox_msghdr hdr;
1521 uint32_t __io blkaddr;
1527 struct ree_rule_db_prog_req_msg {
1528 struct mbox_msghdr hdr;
1529 #define REE_RULE_DB_REQ_BLOCK_SIZE ((64ULL * 1024ULL) >> 1)
1530 uint8_t __io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];
1531 uint32_t __io blkaddr; /* REE0 or REE1 */
1532 uint32_t __io total_len; /* total len of rule db */
1533 uint32_t __io offset; /* offset of current rule db block */
1534 uint16_t __io len; /* length of rule db block */
1535 uint8_t __io is_last; /* is this the last block */
1536 uint8_t __io is_incremental; /* is incremental flow */
1537 uint8_t __io is_dbi; /* is rule db incremental */
1540 struct ree_rule_db_get_req_msg {
1541 struct mbox_msghdr hdr;
1542 uint32_t __io blkaddr;
1543 uint32_t __io offset; /* retrieve db from this offset */
1544 uint8_t __io is_dbi; /* is request for rule db incremental */
1547 struct ree_rd_wr_reg_msg {
1548 struct mbox_msghdr hdr;
1549 uint64_t __io reg_offset;
1550 uint64_t __io *ret_val;
1552 uint32_t __io blkaddr;
1553 uint8_t __io is_write;
1556 struct ree_rule_db_len_rsp_msg {
1557 struct mbox_msghdr hdr;
1558 uint32_t __io blkaddr;
1560 uint32_t __io inc_len;
1563 struct ree_rule_db_get_rsp_msg {
1564 struct mbox_msghdr hdr;
1565 #define REE_RULE_DB_RSP_BLOCK_SIZE (15ULL * 1024ULL)
1566 uint8_t __io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];
1567 uint32_t __io total_len; /* total len of rule db */
1568 uint32_t __io offset; /* offset of current rule db block */
1569 uint16_t __io len; /* length of rule db block */
1570 uint8_t __io is_last; /* is this the last block */
1573 /* NPC mbox message structs */
1575 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1576 #define NPC_MCAM_INVALID_MAP 0xFFFF
1578 /* NPC mailbox error codes
1581 enum npc_af_status {
1582 NPC_MCAM_INVALID_REQ = -701,
1583 NPC_MCAM_ALLOC_DENIED = -702,
1584 NPC_MCAM_ALLOC_FAILED = -703,
1585 NPC_MCAM_PERM_DENIED = -704,
1586 NPC_AF_ERR_HIGIG_CONFIG_FAIL = -705,
1589 struct npc_mcam_alloc_entry_req {
1590 struct mbox_msghdr hdr;
1591 #define NPC_MAX_NONCONTIG_ENTRIES 256
1592 uint8_t __io contig; /* Contiguous entries ? */
1593 #define NPC_MCAM_ANY_PRIO 0
1594 #define NPC_MCAM_LOWER_PRIO 1
1595 #define NPC_MCAM_HIGHER_PRIO 2
1596 uint8_t __io priority; /* Lower or higher w.r.t ref_entry */
1597 uint16_t __io ref_entry;
1598 uint16_t __io count; /* Number of entries requested */
1601 struct npc_mcam_alloc_entry_rsp {
1602 struct mbox_msghdr hdr;
1603 /* Entry alloc'ed or start index if contiguous.
1604 * Invalid in case of non-contiguous.
1606 uint16_t __io entry;
1607 uint16_t __io count; /* Number of entries allocated */
1608 uint16_t __io free_count; /* Number of entries available */
1609 uint16_t __io entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1612 struct npc_mcam_free_entry_req {
1613 struct mbox_msghdr hdr;
1614 uint16_t __io entry; /* Entry index to be freed */
1615 uint8_t __io all; /* Free all entries alloc'ed to this PFVF */
1619 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max key width */
1620 uint64_t __io kw[NPC_MAX_KWS_IN_KEY];
1621 uint64_t __io kw_mask[NPC_MAX_KWS_IN_KEY];
1622 uint64_t __io action;
1623 uint64_t __io vtag_action;
1626 struct npc_mcam_write_entry_req {
1627 struct mbox_msghdr hdr;
1628 struct mcam_entry entry_data;
1629 uint16_t __io entry; /* MCAM entry to write this match key */
1630 uint16_t __io cntr; /* Counter for this MCAM entry */
1631 uint8_t __io intf; /* Rx or Tx interface */
1632 uint8_t __io enable_entry; /* Enable this MCAM entry ? */
1633 uint8_t __io set_cntr; /* Set counter for this entry ? */
1636 /* Enable/Disable a given entry */
1637 struct npc_mcam_ena_dis_entry_req {
1638 struct mbox_msghdr hdr;
1639 uint16_t __io entry;
1642 struct npc_mcam_shift_entry_req {
1643 struct mbox_msghdr hdr;
1644 #define NPC_MCAM_MAX_SHIFTS 64
1645 uint16_t __io curr_entry[NPC_MCAM_MAX_SHIFTS];
1646 uint16_t __io new_entry[NPC_MCAM_MAX_SHIFTS];
1647 uint16_t __io shift_count; /* Number of entries to shift */
1650 struct npc_mcam_shift_entry_rsp {
1651 struct mbox_msghdr hdr;
1652 /* Index in 'curr_entry', not entry itself */
1653 uint16_t __io failed_entry_idx;
1656 struct npc_mcam_alloc_counter_req {
1657 struct mbox_msghdr hdr;
1658 uint8_t __io contig; /* Contiguous counters ? */
1659 #define NPC_MAX_NONCONTIG_COUNTERS 64
1660 uint16_t __io count; /* Number of counters requested */
1663 struct npc_mcam_alloc_counter_rsp {
1664 struct mbox_msghdr hdr;
1665 /* Counter alloc'ed or start idx if contiguous.
1666 * Invalid in case of non-contiguous.
1669 uint16_t __io count; /* Number of counters allocated */
1670 uint16_t __io cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1673 struct npc_mcam_oper_counter_req {
1674 struct mbox_msghdr hdr;
1675 uint16_t __io cntr; /* Free a counter or clear/fetch it's stats */
1678 struct npc_mcam_oper_counter_rsp {
1679 struct mbox_msghdr hdr;
1680 /* valid only while fetching counter's stats */
1684 struct npc_mcam_unmap_counter_req {
1685 struct mbox_msghdr hdr;
1687 uint16_t __io entry; /* Entry and counter to be unmapped */
1688 uint8_t __io all; /* Unmap all entries using this counter ? */
1691 struct npc_mcam_alloc_and_write_entry_req {
1692 struct mbox_msghdr hdr;
1693 struct mcam_entry entry_data;
1694 uint16_t __io ref_entry;
1695 uint8_t __io priority; /* Lower or higher w.r.t ref_entry */
1696 uint8_t __io intf; /* Rx or Tx interface */
1697 uint8_t __io enable_entry; /* Enable this MCAM entry ? */
1698 uint8_t __io alloc_cntr; /* Allocate counter and map ? */
1701 struct npc_mcam_alloc_and_write_entry_rsp {
1702 struct mbox_msghdr hdr;
1703 uint16_t __io entry;
1707 struct npc_get_kex_cfg_rsp {
1708 struct mbox_msghdr hdr;
1709 uint64_t __io rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1710 uint64_t __io tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1711 #define NPC_MAX_INTF 2
1712 #define NPC_MAX_LID 8
1713 #define NPC_MAX_LT 16
1714 #define NPC_MAX_LD 2
1715 #define NPC_MAX_LFL 16
1716 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1717 uint64_t __io kex_ld_flags[NPC_MAX_LD];
1718 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1719 uint64_t __io intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT]
1721 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1722 uint64_t __io intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1723 #define MKEX_NAME_LEN 128
1724 uint8_t __io mkex_pfl_name[MKEX_NAME_LEN];
1727 enum header_fields {
1742 NPC_HEADER_FIELDS_MAX,
1746 unsigned char __io dmac[6];
1747 unsigned char __io smac[6];
1748 uint16_t __io etype;
1749 uint16_t __io vlan_etype;
1750 uint16_t __io vlan_tci;
1752 uint32_t __io ip4src;
1753 uint32_t __io ip6src[4];
1756 uint32_t __io ip4dst;
1757 uint32_t __io ip6dst[4];
1760 uint8_t __io ip_ver;
1761 uint8_t __io ip_proto;
1763 uint16_t __io sport;
1764 uint16_t __io dport;
1767 struct npc_install_flow_req {
1768 struct mbox_msghdr hdr;
1769 struct flow_msg packet;
1770 struct flow_msg mask;
1771 uint64_t __io features;
1772 uint16_t __io entry;
1773 uint16_t __io channel;
1775 uint8_t __io set_cntr;
1776 uint8_t __io default_rule;
1777 /* Overwrite(0) or append(1) flow to default rule? */
1778 uint8_t __io append;
1781 uint32_t __io index;
1782 uint16_t __io match_id;
1783 uint8_t __io flow_key_alg;
1786 uint8_t __io vtag0_type;
1787 uint8_t __io vtag0_valid;
1788 uint8_t __io vtag1_type;
1789 uint8_t __io vtag1_valid;
1791 /* vtag tx action */
1792 uint16_t __io vtag0_def;
1793 uint8_t __io vtag0_op;
1794 uint16_t __io vtag1_def;
1795 uint8_t __io vtag1_op;
1798 struct npc_install_flow_rsp {
1799 struct mbox_msghdr hdr;
1800 /* Negative if no counter else counter number */
1804 struct npc_delete_flow_req {
1805 struct mbox_msghdr hdr;
1806 uint16_t __io entry;
1807 uint16_t __io start; /*Disable range of entries */
1809 uint8_t __io all; /* PF + VFs */
1812 struct npc_mcam_read_entry_req {
1813 struct mbox_msghdr hdr;
1814 /* MCAM entry to read */
1815 uint16_t __io entry;
1818 struct npc_mcam_read_entry_rsp {
1819 struct mbox_msghdr hdr;
1820 struct mcam_entry entry_data;
1822 uint8_t __io enable;
1825 struct npc_mcam_read_base_rule_rsp {
1826 struct mbox_msghdr hdr;
1827 struct mcam_entry entry_data;
1830 struct npc_mcam_get_stats_req {
1831 struct mbox_msghdr hdr;
1832 uint16_t __io entry; /* mcam entry */
1835 struct npc_mcam_get_stats_rsp {
1836 struct mbox_msghdr hdr;
1837 uint64_t __io stat; /* counter stats */
1838 uint8_t __io stat_ena; /* enabled */
1841 /* TIM mailbox error codes
1844 enum tim_af_status {
1845 TIM_AF_NO_RINGS_LEFT = -801,
1846 TIM_AF_INVALID_NPA_PF_FUNC = -802,
1847 TIM_AF_INVALID_SSO_PF_FUNC = -803,
1848 TIM_AF_RING_STILL_RUNNING = -804,
1849 TIM_AF_LF_INVALID = -805,
1850 TIM_AF_CSIZE_NOT_ALIGNED = -806,
1851 TIM_AF_CSIZE_TOO_SMALL = -807,
1852 TIM_AF_CSIZE_TOO_BIG = -808,
1853 TIM_AF_INTERVAL_TOO_SMALL = -809,
1854 TIM_AF_INVALID_BIG_ENDIAN_VALUE = -810,
1855 TIM_AF_INVALID_CLOCK_SOURCE = -811,
1856 TIM_AF_GPIO_CLK_SRC_NOT_ENABLED = -812,
1857 TIM_AF_INVALID_BSIZE = -813,
1858 TIM_AF_INVALID_ENABLE_PERIODIC = -814,
1859 TIM_AF_INVALID_ENABLE_DONTFREE = -815,
1860 TIM_AF_ENA_DONTFRE_NSET_PERIODIC = -816,
1861 TIM_AF_RING_ALREADY_DISABLED = -817,
1865 TIM_CLK_SRCS_TENNS = 0,
1866 TIM_CLK_SRCS_GPIO = 1,
1867 TIM_CLK_SRCS_GTI = 2,
1868 TIM_CLK_SRCS_PTP = 3,
1869 TIM_CLK_SRSC_INVALID,
1872 enum tim_gpio_edge {
1873 TIM_GPIO_NO_EDGE = 0,
1874 TIM_GPIO_LTOH_TRANS = 1,
1875 TIM_GPIO_HTOL_TRANS = 2,
1876 TIM_GPIO_BOTH_TRANS = 3,
1881 PTP_OP_ADJFINE = 0, /* adjfine(req.scaled_ppm); */
1882 PTP_OP_GET_CLOCK = 1, /* rsp.clk = get_clock() */
1886 struct mbox_msghdr hdr;
1888 int64_t __io scaled_ppm;
1889 uint8_t __io is_pmu;
1893 struct mbox_msghdr hdr;
1898 struct get_hw_cap_rsp {
1899 struct mbox_msghdr hdr;
1900 /* Schq mapping fixed or flexible */
1901 uint8_t __io nix_fixed_txschq_mapping;
1902 uint8_t __io nix_shaping; /* Is shaping and coloring supported */
1905 struct ndc_sync_op {
1906 struct mbox_msghdr hdr;
1907 uint8_t __io nix_lf_tx_sync;
1908 uint8_t __io nix_lf_rx_sync;
1909 uint8_t __io npa_lf_sync;
1912 struct tim_lf_alloc_req {
1913 struct mbox_msghdr hdr;
1915 uint16_t __io npa_pf_func;
1916 uint16_t __io sso_pf_func;
1919 struct tim_ring_req {
1920 struct mbox_msghdr hdr;
1924 struct tim_config_req {
1925 struct mbox_msghdr hdr;
1927 uint8_t __io bigendian;
1928 uint8_t __io clocksource;
1929 uint8_t __io enableperiodic;
1930 uint8_t __io enabledontfreebuffer;
1931 uint32_t __io bucketsize;
1932 uint32_t __io chunksize;
1933 uint32_t __io interval;
1934 uint8_t __io gpioedge;
1935 uint8_t __io rsvd[7];
1936 uint64_t __io intervalns;
1937 uint64_t __io clockfreq;
1940 struct tim_lf_alloc_rsp {
1941 struct mbox_msghdr hdr;
1942 uint64_t __io tenns_clk;
1945 struct tim_enable_rsp {
1946 struct mbox_msghdr hdr;
1947 uint64_t __io timestarted;
1948 uint32_t __io currentbucket;
1951 struct tim_intvl_req {
1952 struct mbox_msghdr hdr;
1953 uint8_t __io clocksource;
1954 uint64_t __io clockfreq;
1957 struct tim_intvl_rsp {
1958 struct mbox_msghdr hdr;
1959 uint64_t __io intvl_cyc;
1960 uint64_t __io intvl_ns;
1963 struct sdp_node_info {
1964 /* Node to which this PF belons to */
1965 uint8_t __io node_id;
1966 uint8_t __io max_vfs;
1967 uint8_t __io num_pf_rings;
1968 uint8_t __io pf_srn;
1969 #define SDP_MAX_VFS 128
1970 uint8_t __io vf_rings[SDP_MAX_VFS];
1973 struct sdp_chan_info_msg {
1974 struct mbox_msghdr hdr;
1975 struct sdp_node_info info;
1978 #endif /* __ROC_MBOX_H__ */