1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
8 struct roc_model *roc_model;
10 /* RoC and CPU IDs and revisions */
11 #define VENDOR_ARM 0x41 /* 'A' */
12 #define VENDOR_CAVIUM 0x43 /* 'C' */
14 #define SOC_PART_CN10K 0xD49
16 #define PART_106XX 0xB9
17 #define PART_105XX 0xBA
18 #define PART_105XXN 0xBC
19 #define PART_98XX 0xB1
20 #define PART_96XX 0xB2
21 #define PART_95XX 0xB3
22 #define PART_95XXN 0xB4
23 #define PART_95XXMM 0xB5
26 #define MODEL_IMPL_BITS 8
27 #define MODEL_IMPL_SHIFT 24
28 #define MODEL_IMPL_MASK ((1 << MODEL_IMPL_BITS) - 1)
29 #define MODEL_PART_BITS 12
30 #define MODEL_PART_SHIFT 4
31 #define MODEL_PART_MASK ((1 << MODEL_PART_BITS) - 1)
32 #define MODEL_MAJOR_BITS 4
33 #define MODEL_MAJOR_SHIFT 20
34 #define MODEL_MAJOR_MASK ((1 << MODEL_MAJOR_BITS) - 1)
35 #define MODEL_MINOR_BITS 4
36 #define MODEL_MINOR_SHIFT 0
37 #define MODEL_MINOR_MASK ((1 << MODEL_MINOR_BITS) - 1)
39 static const struct model_db {
45 char name[ROC_MODEL_STR_LEN_MAX];
47 {VENDOR_ARM, PART_106XX, 0, 0, ROC_MODEL_CN106XX, "cn10ka"},
48 {VENDOR_ARM, PART_105XX, 0, 0, ROC_MODEL_CNF105XX, "cnf10ka"},
49 {VENDOR_ARM, PART_105XXN, 0, 0, ROC_MODEL_CNF105XXN, "cnf10kb"},
50 {VENDOR_CAVIUM, PART_98XX, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"},
51 {VENDOR_CAVIUM, PART_96XX, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"},
52 {VENDOR_CAVIUM, PART_96XX, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"},
53 {VENDOR_CAVIUM, PART_96XX, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"},
54 {VENDOR_CAVIUM, PART_95XX, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"},
55 {VENDOR_CAVIUM, PART_95XX, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
56 {VENDOR_CAVIUM, PART_95XXN, 0, 0, ROC_MODEL_CNF95XXN_A0, "cnf95xxn_a0"},
57 {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95XXO_A0, "cnf95O_a0"},
58 {VENDOR_CAVIUM, PART_95XXMM, 0, 0, ROC_MODEL_CNF95XXMM_A0,
70 /* Read the CPU compatible variant */
71 fd = fopen("/proc/device-tree/compatible", "r");
73 plt_err("Failed to open /proc/device-tree/compatible");
77 if (fgets(buf, sizeof(buf), fd) == NULL) {
78 plt_err("Failed to read from /proc/device-tree/compatible");
81 ptr = strchr(buf, ',');
83 plt_err("Malformed 'CPU compatible': <%s>", buf);
87 if (strcmp("cn10ka", ptr) == 0) {
89 } else if (strcmp("cnf10ka", ptr) == 0) {
91 } else if (strcmp("cnf10kb", ptr) == 0) {
94 plt_err("Unidentified 'CPU compatible': <%s>", ptr);
106 populate_model(struct roc_model *model, uint32_t midr)
108 uint32_t impl, major, part, minor;
112 impl = (midr >> MODEL_IMPL_SHIFT) & MODEL_IMPL_MASK;
113 part = (midr >> MODEL_PART_SHIFT) & MODEL_PART_MASK;
114 major = (midr >> MODEL_MAJOR_SHIFT) & MODEL_MAJOR_MASK;
115 minor = (midr >> MODEL_MINOR_SHIFT) & MODEL_MINOR_MASK;
117 /* Update part number for cn10k from device-tree */
118 if (part == SOC_PART_CN10K)
119 part = cn10k_part_get();
121 for (i = 0; i < PLT_DIM(model_db); i++)
122 if (model_db[i].impl == impl && model_db[i].part == part &&
123 model_db[i].major == major && model_db[i].minor == minor) {
124 model->flag = model_db[i].flag;
125 strncpy(model->name, model_db[i].name,
126 ROC_MODEL_STR_LEN_MAX - 1);
133 strncpy(model->name, "unknown", ROC_MODEL_STR_LEN_MAX - 1);
134 plt_err("Invalid RoC model (impl=0x%x, part=0x%x)", impl, part);
141 midr_get(unsigned long *val)
144 "/sys/devices/system/cpu/cpu0/regs/identification/midr_el1";
145 int rc = UTIL_ERR_FS;
152 f = fopen(file, "r");
156 if (fgets(buf, sizeof(buf), f) == NULL)
159 *val = strtoul(buf, &end, 0);
160 if ((buf[0] == '\0') || (end == NULL) || (*end != '\n'))
171 detect_invalid_config(void)
173 #ifdef ROC_PLATFORM_CN9K
174 #ifdef ROC_PLATFORM_CN10K
175 PLT_STATIC_ASSERT(0);
181 roc_model_init(struct roc_model *model)
183 int rc = UTIL_ERR_PARAM;
186 detect_invalid_config();
191 rc = midr_get(&midr);
195 rc = UTIL_ERR_INVALID_MODEL;
196 if (!populate_model(model, midr))
200 plt_info("RoC Model: %s", model->name);