1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
8 struct roc_model *roc_model;
10 /* RoC and CPU IDs and revisions */
11 #define VENDOR_ARM 0x41 /* 'A' */
12 #define VENDOR_CAVIUM 0x43 /* 'C' */
14 #define SOC_PART_CN10K 0xD49
16 #define PART_106xx 0xB9
17 #define PART_105xx 0xBA
18 #define PART_105xxN 0xBC
19 #define PART_98xx 0xB1
20 #define PART_96xx 0xB2
21 #define PART_95xx 0xB3
22 #define PART_95xxN 0xB4
23 #define PART_95xxMM 0xB5
26 #define MODEL_IMPL_BITS 8
27 #define MODEL_IMPL_SHIFT 24
28 #define MODEL_IMPL_MASK ((1 << MODEL_IMPL_BITS) - 1)
29 #define MODEL_PART_BITS 12
30 #define MODEL_PART_SHIFT 4
31 #define MODEL_PART_MASK ((1 << MODEL_PART_BITS) - 1)
32 #define MODEL_MAJOR_BITS 4
33 #define MODEL_MAJOR_SHIFT 20
34 #define MODEL_MAJOR_MASK ((1 << MODEL_MAJOR_BITS) - 1)
35 #define MODEL_MINOR_BITS 4
36 #define MODEL_MINOR_SHIFT 0
37 #define MODEL_MINOR_MASK ((1 << MODEL_MINOR_BITS) - 1)
39 static const struct model_db {
45 char name[ROC_MODEL_STR_LEN_MAX];
47 {VENDOR_ARM, PART_106xx, 0, 0, ROC_MODEL_CN106xx_A0, "cn10ka_a0"},
48 {VENDOR_ARM, PART_105xx, 0, 0, ROC_MODEL_CNF105xx_A0, "cnf10ka_a0"},
49 {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"},
50 {VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"},
51 {VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"},
52 {VENDOR_CAVIUM, PART_96xx, 0, 1, ROC_MODEL_CN96xx_B0, "cn96xx_b0"},
53 {VENDOR_CAVIUM, PART_96xx, 2, 0, ROC_MODEL_CN96xx_C0, "cn96xx_c0"},
54 {VENDOR_CAVIUM, PART_96xx, 2, 1, ROC_MODEL_CN96xx_C0, "cn96xx_c1"},
55 {VENDOR_CAVIUM, PART_95xx, 0, 0, ROC_MODEL_CNF95xx_A0, "cnf95xx_a0"},
56 {VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
57 {VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"},
58 {VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"},
59 {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"},
60 {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,
71 /* Read the CPU compatible variant */
72 fd = fopen("/proc/device-tree/compatible", "r");
74 plt_err("Failed to open /proc/device-tree/compatible");
78 if (fgets(buf, sizeof(buf), fd) == NULL) {
79 plt_err("Failed to read from /proc/device-tree/compatible");
82 ptr = strchr(buf, ',');
84 plt_err("Malformed 'CPU compatible': <%s>", buf);
88 if (strcmp("cn10ka", ptr) == 0) {
90 } else if (strcmp("cnf10ka", ptr) == 0) {
92 } else if (strcmp("cnf10kb", ptr) == 0) {
95 plt_err("Unidentified 'CPU compatible': <%s>", ptr);
107 populate_model(struct roc_model *model, uint32_t midr)
109 uint32_t impl, major, part, minor;
113 impl = (midr >> MODEL_IMPL_SHIFT) & MODEL_IMPL_MASK;
114 part = (midr >> MODEL_PART_SHIFT) & MODEL_PART_MASK;
115 major = (midr >> MODEL_MAJOR_SHIFT) & MODEL_MAJOR_MASK;
116 minor = (midr >> MODEL_MINOR_SHIFT) & MODEL_MINOR_MASK;
118 /* Update part number for cn10k from device-tree */
119 if (part == SOC_PART_CN10K)
120 part = cn10k_part_get();
122 for (i = 0; i < PLT_DIM(model_db); i++)
123 if (model_db[i].impl == impl && model_db[i].part == part &&
124 model_db[i].major == major && model_db[i].minor == minor) {
125 model->flag = model_db[i].flag;
126 strncpy(model->name, model_db[i].name,
127 ROC_MODEL_STR_LEN_MAX - 1);
134 strncpy(model->name, "unknown", ROC_MODEL_STR_LEN_MAX - 1);
135 plt_err("Invalid RoC model (impl=0x%x, part=0x%x)", impl, part);
142 midr_get(unsigned long *val)
145 "/sys/devices/system/cpu/cpu0/regs/identification/midr_el1";
146 int rc = UTIL_ERR_FS;
153 f = fopen(file, "r");
157 if (fgets(buf, sizeof(buf), f) == NULL)
160 *val = strtoul(buf, &end, 0);
161 if ((buf[0] == '\0') || (end == NULL) || (*end != '\n'))
172 detect_invalid_config(void)
174 #ifdef ROC_PLATFORM_CN9K
175 #ifdef ROC_PLATFORM_CN10K
176 PLT_STATIC_ASSERT(0);
182 roc_model_init(struct roc_model *model)
184 int rc = UTIL_ERR_PARAM;
187 detect_invalid_config();
192 rc = midr_get(&midr);
196 rc = UTIL_ERR_INVALID_MODEL;
197 if (!populate_model(model, midr))
201 plt_info("RoC Model: %s", model->name);