1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
9 roc_nix_is_lbk(struct roc_nix *roc_nix)
11 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
17 roc_nix_get_base_chan(struct roc_nix *roc_nix)
19 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
21 return nix->rx_chan_base;
25 roc_nix_get_vwqe_interval(struct roc_nix *roc_nix)
27 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
29 return nix->vwqe_interval;
33 roc_nix_is_sdp(struct roc_nix *roc_nix)
35 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
41 roc_nix_is_pf(struct roc_nix *roc_nix)
43 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
45 return !dev_is_vf(&nix->dev);
49 roc_nix_get_pf(struct roc_nix *roc_nix)
51 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
52 struct dev *dev = &nix->dev;
54 return dev_get_pf(dev->pf_func);
58 roc_nix_get_vf(struct roc_nix *roc_nix)
60 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
61 struct dev *dev = &nix->dev;
63 return dev_get_vf(dev->pf_func);
67 roc_nix_is_vf_or_sdp(struct roc_nix *roc_nix)
69 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
71 return (dev_is_vf(&nix->dev) != 0) || roc_nix_is_sdp(roc_nix);
75 roc_nix_get_pf_func(struct roc_nix *roc_nix)
77 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
78 struct dev *dev = &nix->dev;
84 roc_nix_lf_inl_ipsec_cfg(struct roc_nix *roc_nix, struct roc_nix_ipsec_cfg *cfg,
87 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
88 struct nix_inline_ipsec_lf_cfg *lf_cfg;
89 struct mbox *mbox = (&nix->dev)->mbox;
91 lf_cfg = mbox_alloc_msg_nix_inline_ipsec_lf_cfg(mbox);
97 lf_cfg->sa_base_addr = cfg->iova;
98 lf_cfg->ipsec_cfg1.sa_idx_w = plt_log2_u32(cfg->max_sa);
99 lf_cfg->ipsec_cfg0.lenm1_max = roc_nix_max_pkt_len(roc_nix) - 1;
100 lf_cfg->ipsec_cfg1.sa_idx_max = cfg->max_sa - 1;
101 lf_cfg->ipsec_cfg0.sa_pow2_size = plt_log2_u32(cfg->sa_size);
102 lf_cfg->ipsec_cfg0.tag_const = cfg->tag_const;
103 lf_cfg->ipsec_cfg0.tt = cfg->tt;
108 return mbox_process(mbox);
112 roc_nix_cpt_ctx_cache_sync(struct roc_nix *roc_nix)
114 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
115 struct mbox *mbox = (&nix->dev)->mbox;
118 req = mbox_alloc_msg_cpt_ctx_cache_sync(mbox);
122 return mbox_process(mbox);
126 roc_nix_max_pkt_len(struct roc_nix *roc_nix)
128 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
130 if (roc_nix_is_sdp(roc_nix))
131 return NIX_SDP_MAX_HW_FRS;
133 if (roc_model_is_cn9k())
134 return NIX_CN9K_MAX_HW_FRS;
137 return NIX_LBK_MAX_HW_FRS;
139 return NIX_RPM_MAX_HW_FRS;
143 roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq,
146 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
147 struct mbox *mbox = (&nix->dev)->mbox;
148 struct nix_lf_alloc_req *req;
149 struct nix_lf_alloc_rsp *rsp;
152 req = mbox_alloc_msg_nix_lf_alloc(mbox);
155 req->rq_cnt = nb_rxq;
156 req->sq_cnt = nb_txq;
157 req->cq_cnt = nb_rxq;
158 /* XQESZ can be W64 or W16 */
159 req->xqe_sz = NIX_XQESZ_W16;
160 req->rss_sz = nix->reta_sz;
161 req->rss_grps = ROC_NIX_RSS_GRPS;
162 req->npa_func = idev_npa_pffunc_get();
163 req->sso_func = idev_sso_pffunc_get();
164 req->rx_cfg = rx_cfg;
165 if (roc_nix_is_lbk(roc_nix) && roc_nix->enable_loop &&
166 roc_model_is_cn98xx())
167 req->flags = NIX_LF_LBK_BLK_SEL;
169 if (!roc_nix->rss_tag_as_xor)
170 req->flags |= NIX_LF_RSS_TAG_LSB_AS_ADDER;
172 rc = mbox_process_msg(mbox, (void *)&rsp);
176 nix->rx_cfg = rx_cfg;
177 nix->sqb_size = rsp->sqb_size;
178 nix->tx_chan_base = rsp->tx_chan_base;
179 nix->rx_chan_base = rsp->rx_chan_base;
180 if (roc_nix_is_lbk(roc_nix) && roc_nix->enable_loop)
181 nix->tx_chan_base = rsp->rx_chan_base;
182 nix->rx_chan_cnt = rsp->rx_chan_cnt;
183 nix->tx_chan_cnt = rsp->tx_chan_cnt;
184 nix->lso_tsov4_idx = rsp->lso_tsov4_idx;
185 nix->lso_tsov6_idx = rsp->lso_tsov6_idx;
186 nix->lf_tx_stats = rsp->lf_tx_stats;
187 nix->lf_rx_stats = rsp->lf_rx_stats;
188 nix->cints = rsp->cints;
189 roc_nix->cints = rsp->cints;
190 nix->qints = rsp->qints;
191 nix->ptp_en = rsp->hw_rx_tstamp_en;
192 roc_nix->rx_ptp_ena = rsp->hw_rx_tstamp_en;
193 nix->cgx_links = rsp->cgx_links;
194 nix->lbk_links = rsp->lbk_links;
195 nix->sdp_links = rsp->sdp_links;
196 nix->tx_link = rsp->tx_link;
197 nix->nb_rx_queues = nb_rxq;
198 nix->nb_tx_queues = nb_txq;
199 nix->sqs = plt_zmalloc(sizeof(struct roc_nix_sq *) * nb_txq, 0);
203 nix_tel_node_add(roc_nix);
209 roc_nix_lf_free(struct roc_nix *roc_nix)
211 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
212 struct mbox *mbox = (&nix->dev)->mbox;
213 struct nix_lf_free_req *req;
214 struct ndc_sync_op *ndc_req;
220 /* Sync NDC-NIX for LF */
221 ndc_req = mbox_alloc_msg_ndc_sync_op(mbox);
224 ndc_req->nix_lf_tx_sync = 1;
225 ndc_req->nix_lf_rx_sync = 1;
226 rc = mbox_process(mbox);
228 plt_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
230 req = mbox_alloc_msg_nix_lf_free(mbox);
233 /* Let AF driver free all this nix lf's
234 * NPC entries allocated using NPC MBOX.
238 return mbox_process(mbox);
242 nix_lf_attach(struct dev *dev)
244 struct mbox *mbox = dev->mbox;
245 struct rsrc_attach_req *req;
249 req = mbox_alloc_msg_attach_resources(mbox);
255 return mbox_process(mbox);
259 nix_lf_get_msix_offset(struct dev *dev, struct nix *nix)
261 struct msix_offset_rsp *msix_rsp;
262 struct mbox *mbox = dev->mbox;
265 /* Get MSIX vector offsets */
266 mbox_alloc_msg_msix_offset(mbox);
267 rc = mbox_process_msg(mbox, (void *)&msix_rsp);
269 nix->msixoff = msix_rsp->nix_msixoff;
275 nix_lf_detach(struct nix *nix)
277 struct mbox *mbox = (&nix->dev)->mbox;
278 struct rsrc_detach_req *req;
281 req = mbox_alloc_msg_detach_resources(mbox);
287 return mbox_process(mbox);
291 roc_nix_get_hw_info(struct roc_nix *roc_nix)
293 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
294 struct mbox *mbox = (&nix->dev)->mbox;
295 struct nix_hw_info *hw_info;
298 mbox_alloc_msg_nix_get_hw_info(mbox);
299 rc = mbox_process_msg(mbox, (void *)&hw_info);
301 nix->vwqe_interval = hw_info->vwqe_delay;
307 sdp_lbk_id_update(struct plt_pci_device *pci_dev, struct nix *nix)
309 nix->sdp_link = false;
310 nix->lbk_link = false;
312 /* Update SDP/LBK link based on PCI device id */
313 switch (pci_dev->id.device_id) {
314 case PCI_DEVID_CNXK_RVU_SDP_PF:
315 case PCI_DEVID_CNXK_RVU_SDP_VF:
316 nix->sdp_link = true;
318 case PCI_DEVID_CNXK_RVU_AF_VF:
319 nix->lbk_link = true;
327 nix_get_blkaddr(struct dev *dev)
331 /* Reading the discovery register to know which NIX is the LF
334 reg = plt_read64(dev->bar2 +
335 RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_NIX0));
337 return reg & 0x1FFULL ? RVU_BLOCK_ADDR_NIX0 : RVU_BLOCK_ADDR_NIX1;
341 roc_nix_dev_init(struct roc_nix *roc_nix)
343 enum roc_nix_rss_reta_sz reta_sz;
344 struct plt_pci_device *pci_dev;
345 uint16_t max_sqb_count;
351 if (roc_nix == NULL || roc_nix->pci_dev == NULL)
352 return NIX_ERR_PARAM;
354 reta_sz = roc_nix->reta_sz;
355 if (reta_sz != 0 && reta_sz != 64 && reta_sz != 128 && reta_sz != 256)
356 return NIX_ERR_PARAM;
359 reta_sz = ROC_NIX_RSS_RETA_SZ_64;
361 max_sqb_count = roc_nix->max_sqb_count;
362 max_sqb_count = PLT_MIN(max_sqb_count, NIX_MAX_SQB);
363 max_sqb_count = PLT_MAX(max_sqb_count, NIX_MIN_SQB);
364 roc_nix->max_sqb_count = max_sqb_count;
366 PLT_STATIC_ASSERT(sizeof(struct nix) <= ROC_NIX_MEM_SZ);
367 nix = roc_nix_to_nix_priv(roc_nix);
368 pci_dev = roc_nix->pci_dev;
371 if (nix->dev.drv_inited)
374 if (dev->mbox_active)
377 memset(nix, 0, sizeof(*nix));
378 /* Initialize device */
379 rc = dev_init(dev, pci_dev);
381 plt_err("Failed to init roc device");
386 dev->roc_nix = roc_nix;
388 nix->lmt_base = dev->lmt_base;
389 /* Expose base LMT line address for
390 * "Per Core LMT line" mode.
392 roc_nix->lmt_base = dev->lmt_base;
395 rc = nix_lf_attach(dev);
399 blkaddr = nix_get_blkaddr(dev);
400 nix->is_nix1 = (blkaddr == RVU_BLOCK_ADDR_NIX1);
402 /* Calculating base address based on which NIX block LF
405 nix->base = dev->bar2 + (blkaddr << 20);
407 /* Get NIX MSIX offset */
408 rc = nix_lf_get_msix_offset(dev, nix);
412 /* Update nix context */
413 sdp_lbk_id_update(pci_dev, nix);
414 nix->pci_dev = pci_dev;
415 nix->reta_sz = reta_sz;
416 nix->mtu = ROC_NIX_DEFAULT_HW_FRS;
418 /* Always start with full FC for LBK */
422 } else if (!roc_nix_is_vf_or_sdp(roc_nix)) {
423 /* Get the current state of flow control */
424 roc_nix_fc_mode_get(roc_nix);
427 /* Register error and ras interrupts */
428 rc = nix_register_irqs(nix);
432 rc = nix_tm_conf_init(roc_nix);
434 goto unregister_irqs;
436 /* Get NIX HW info */
437 roc_nix_get_hw_info(roc_nix);
438 nix->dev.drv_inited = true;
442 nix_unregister_irqs(nix);
446 rc |= dev_fini(dev, pci_dev);
448 nix_tel_node_del(roc_nix);
453 roc_nix_dev_fini(struct roc_nix *roc_nix)
455 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
459 return NIX_ERR_PARAM;
461 if (!nix->dev.drv_inited)
464 nix_tm_conf_fini(roc_nix);
465 nix_unregister_irqs(nix);
467 rc = nix_lf_detach(nix);
468 nix->dev.drv_inited = false;
470 rc |= dev_fini(&nix->dev, nix->pci_dev);