1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
8 #define nix_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__)
9 #define NIX_REG_INFO(reg) \
13 #define NIX_REG_NAME_SZ 48
15 #define nix_dump_no_nl(fmt, ...) fprintf(stderr, fmt, ##__VA_ARGS__)
17 struct nix_lf_reg_info {
22 static const struct nix_lf_reg_info nix_lf_reg[] = {
23 NIX_REG_INFO(NIX_LF_RX_SECRETX(0)),
24 NIX_REG_INFO(NIX_LF_RX_SECRETX(1)),
25 NIX_REG_INFO(NIX_LF_RX_SECRETX(2)),
26 NIX_REG_INFO(NIX_LF_RX_SECRETX(3)),
27 NIX_REG_INFO(NIX_LF_RX_SECRETX(4)),
28 NIX_REG_INFO(NIX_LF_RX_SECRETX(5)),
29 NIX_REG_INFO(NIX_LF_CFG),
30 NIX_REG_INFO(NIX_LF_GINT),
31 NIX_REG_INFO(NIX_LF_GINT_W1S),
32 NIX_REG_INFO(NIX_LF_GINT_ENA_W1C),
33 NIX_REG_INFO(NIX_LF_GINT_ENA_W1S),
34 NIX_REG_INFO(NIX_LF_ERR_INT),
35 NIX_REG_INFO(NIX_LF_ERR_INT_W1S),
36 NIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1C),
37 NIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1S),
38 NIX_REG_INFO(NIX_LF_RAS),
39 NIX_REG_INFO(NIX_LF_RAS_W1S),
40 NIX_REG_INFO(NIX_LF_RAS_ENA_W1C),
41 NIX_REG_INFO(NIX_LF_RAS_ENA_W1S),
42 NIX_REG_INFO(NIX_LF_SQ_OP_ERR_DBG),
43 NIX_REG_INFO(NIX_LF_MNQ_ERR_DBG),
44 NIX_REG_INFO(NIX_LF_SEND_ERR_DBG),
48 roc_nix_lf_get_reg_count(struct roc_nix *roc_nix)
50 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
56 reg_count = PLT_DIM(nix_lf_reg);
58 reg_count += nix->lf_tx_stats;
60 reg_count += nix->lf_rx_stats;
62 reg_count += nix->qints;
63 /* NIX_LF_QINTX_INT */
64 reg_count += nix->qints;
65 /* NIX_LF_QINTX_ENA_W1S */
66 reg_count += nix->qints;
67 /* NIX_LF_QINTX_ENA_W1C */
68 reg_count += nix->qints;
69 /* NIX_LF_CINTX_CNT */
70 reg_count += nix->cints;
71 /* NIX_LF_CINTX_WAIT */
72 reg_count += nix->cints;
73 /* NIX_LF_CINTX_INT */
74 reg_count += nix->cints;
75 /* NIX_LF_CINTX_INT_W1S */
76 reg_count += nix->cints;
77 /* NIX_LF_CINTX_ENA_W1S */
78 reg_count += nix->cints;
79 /* NIX_LF_CINTX_ENA_W1C */
80 reg_count += nix->cints;
86 roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)
88 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
89 uintptr_t nix_lf_base = nix->base;
97 dump_stdout = data ? 0 : 1;
99 for (i = 0; i < PLT_DIM(nix_lf_reg); i++) {
100 reg = plt_read64(nix_lf_base + nix_lf_reg[i].offset);
101 if (dump_stdout && reg)
102 nix_dump("%32s = 0x%" PRIx64, nix_lf_reg[i].name, reg);
107 /* NIX_LF_TX_STATX */
108 for (i = 0; i < nix->lf_tx_stats; i++) {
109 reg = plt_read64(nix_lf_base + NIX_LF_TX_STATX(i));
110 if (dump_stdout && reg)
111 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_TX_STATX", i,
117 /* NIX_LF_RX_STATX */
118 for (i = 0; i < nix->lf_rx_stats; i++) {
119 reg = plt_read64(nix_lf_base + NIX_LF_RX_STATX(i));
120 if (dump_stdout && reg)
121 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_RX_STATX", i,
127 /* NIX_LF_QINTX_CNT*/
128 for (i = 0; i < nix->qints; i++) {
129 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_CNT(i));
130 if (dump_stdout && reg)
131 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_CNT", i,
137 /* NIX_LF_QINTX_INT */
138 for (i = 0; i < nix->qints; i++) {
139 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_INT(i));
140 if (dump_stdout && reg)
141 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_INT", i,
147 /* NIX_LF_QINTX_ENA_W1S */
148 for (i = 0; i < nix->qints; i++) {
149 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1S(i));
150 if (dump_stdout && reg)
151 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_ENA_W1S",
157 /* NIX_LF_QINTX_ENA_W1C */
158 for (i = 0; i < nix->qints; i++) {
159 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1C(i));
160 if (dump_stdout && reg)
161 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_ENA_W1C",
167 /* NIX_LF_CINTX_CNT */
168 for (i = 0; i < nix->cints; i++) {
169 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_CNT(i));
170 if (dump_stdout && reg)
171 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_CNT", i,
177 /* NIX_LF_CINTX_WAIT */
178 for (i = 0; i < nix->cints; i++) {
179 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_WAIT(i));
180 if (dump_stdout && reg)
181 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_WAIT", i,
187 /* NIX_LF_CINTX_INT */
188 for (i = 0; i < nix->cints; i++) {
189 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_INT(i));
190 if (dump_stdout && reg)
191 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_INT", i,
197 /* NIX_LF_CINTX_INT_W1S */
198 for (i = 0; i < nix->cints; i++) {
199 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_INT_W1S(i));
200 if (dump_stdout && reg)
201 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_INT_W1S",
207 /* NIX_LF_CINTX_ENA_W1S */
208 for (i = 0; i < nix->cints; i++) {
209 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1S(i));
210 if (dump_stdout && reg)
211 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_ENA_W1S",
217 /* NIX_LF_CINTX_ENA_W1C */
218 for (i = 0; i < nix->cints; i++) {
219 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1C(i));
220 if (dump_stdout && reg)
221 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_ENA_W1C",
230 nix_q_ctx_get(struct mbox *mbox, uint8_t ctype, uint16_t qid, __io void **ctx_p)
234 if (roc_model_is_cn9k()) {
235 struct nix_aq_enq_rsp *rsp;
236 struct nix_aq_enq_req *aq;
239 aq = mbox_alloc_msg_nix_aq_enq(mbox);
242 aq->op = NIX_AQ_INSTOP_READ;
244 rc = mbox_process_msg(mbox, (void *)&rsp);
247 if (ctype == NIX_AQ_CTYPE_RQ)
249 else if (ctype == NIX_AQ_CTYPE_SQ)
254 struct nix_cn10k_aq_enq_rsp *rsp;
255 struct nix_cn10k_aq_enq_req *aq;
257 aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);
260 aq->op = NIX_AQ_INSTOP_READ;
262 rc = mbox_process_msg(mbox, (void *)&rsp);
266 if (ctype == NIX_AQ_CTYPE_RQ)
268 else if (ctype == NIX_AQ_CTYPE_SQ)
277 nix_cn9k_lf_sq_dump(__io struct nix_sq_ctx_s *ctx, uint32_t *sqb_aura_p)
279 nix_dump("W0: sqe_way_mask \t\t%d\nW0: cq \t\t\t\t%d",
280 ctx->sqe_way_mask, ctx->cq);
281 nix_dump("W0: sdp_mcast \t\t\t%d\nW0: substream \t\t\t0x%03x",
282 ctx->sdp_mcast, ctx->substream);
283 nix_dump("W0: qint_idx \t\t\t%d\nW0: ena \t\t\t%d\n", ctx->qint_idx,
286 nix_dump("W1: sqb_count \t\t\t%d\nW1: default_chan \t\t%d",
287 ctx->sqb_count, ctx->default_chan);
288 nix_dump("W1: smq_rr_quantum \t\t%d\nW1: sso_ena \t\t\t%d",
289 ctx->smq_rr_quantum, ctx->sso_ena);
290 nix_dump("W1: xoff \t\t\t%d\nW1: cq_ena \t\t\t%d\nW1: smq\t\t\t\t%d\n",
291 ctx->xoff, ctx->cq_ena, ctx->smq);
293 nix_dump("W2: sqe_stype \t\t\t%d\nW2: sq_int_ena \t\t\t%d",
294 ctx->sqe_stype, ctx->sq_int_ena);
295 nix_dump("W2: sq_int \t\t\t%d\nW2: sqb_aura \t\t\t%d", ctx->sq_int,
297 nix_dump("W2: smq_rr_count \t\t%d\n", ctx->smq_rr_count);
299 nix_dump("W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d",
300 ctx->smq_next_sq_vld, ctx->smq_pend);
301 nix_dump("W3: smenq_next_sqb_vld \t%d\nW3: head_offset\t\t\t%d",
302 ctx->smenq_next_sqb_vld, ctx->head_offset);
303 nix_dump("W3: smenq_offset\t\t%d\nW3: tail_offset \t\t%d",
304 ctx->smenq_offset, ctx->tail_offset);
305 nix_dump("W3: smq_lso_segnum \t\t%d\nW3: smq_next_sq \t\t%d",
306 ctx->smq_lso_segnum, ctx->smq_next_sq);
307 nix_dump("W3: mnq_dis \t\t\t%d\nW3: lmt_dis \t\t\t%d", ctx->mnq_dis,
309 nix_dump("W3: cq_limit\t\t\t%d\nW3: max_sqe_size\t\t%d\n",
310 ctx->cq_limit, ctx->max_sqe_size);
312 nix_dump("W4: next_sqb \t\t\t0x%" PRIx64 "", ctx->next_sqb);
313 nix_dump("W5: tail_sqb \t\t\t0x%" PRIx64 "", ctx->tail_sqb);
314 nix_dump("W6: smenq_sqb \t\t\t0x%" PRIx64 "", ctx->smenq_sqb);
315 nix_dump("W7: smenq_next_sqb \t\t0x%" PRIx64 "", ctx->smenq_next_sqb);
316 nix_dump("W8: head_sqb \t\t\t0x%" PRIx64 "", ctx->head_sqb);
318 nix_dump("W9: vfi_lso_vld \t\t%d\nW9: vfi_lso_vlan1_ins_ena\t%d",
319 ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena);
320 nix_dump("W9: vfi_lso_vlan0_ins_ena\t%d\nW9: vfi_lso_mps\t\t\t%d",
321 ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps);
322 nix_dump("W9: vfi_lso_sb \t\t\t%d\nW9: vfi_lso_sizem1\t\t%d",
323 ctx->vfi_lso_sb, ctx->vfi_lso_sizem1);
324 nix_dump("W9: vfi_lso_total\t\t%d", ctx->vfi_lso_total);
326 nix_dump("W10: scm_lso_rem \t\t0x%" PRIx64 "",
327 (uint64_t)ctx->scm_lso_rem);
328 nix_dump("W11: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
329 nix_dump("W12: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
330 nix_dump("W14: dropped_octs \t\t0x%" PRIx64 "",
331 (uint64_t)ctx->drop_octs);
332 nix_dump("W15: dropped_pkts \t\t0x%" PRIx64 "",
333 (uint64_t)ctx->drop_pkts);
335 *sqb_aura_p = ctx->sqb_aura;
339 nix_lf_sq_dump(__io struct nix_cn10k_sq_ctx_s *ctx, uint32_t *sqb_aura_p)
341 nix_dump("W0: sqe_way_mask \t\t%d\nW0: cq \t\t\t\t%d",
342 ctx->sqe_way_mask, ctx->cq);
343 nix_dump("W0: sdp_mcast \t\t\t%d\nW0: substream \t\t\t0x%03x",
344 ctx->sdp_mcast, ctx->substream);
345 nix_dump("W0: qint_idx \t\t\t%d\nW0: ena \t\t\t%d\n", ctx->qint_idx,
348 nix_dump("W1: sqb_count \t\t\t%d\nW1: default_chan \t\t%d",
349 ctx->sqb_count, ctx->default_chan);
350 nix_dump("W1: smq_rr_weight \t\t%d\nW1: sso_ena \t\t\t%d",
351 ctx->smq_rr_weight, ctx->sso_ena);
352 nix_dump("W1: xoff \t\t\t%d\nW1: cq_ena \t\t\t%d\nW1: smq\t\t\t\t%d\n",
353 ctx->xoff, ctx->cq_ena, ctx->smq);
355 nix_dump("W2: sqe_stype \t\t\t%d\nW2: sq_int_ena \t\t\t%d",
356 ctx->sqe_stype, ctx->sq_int_ena);
357 nix_dump("W2: sq_int \t\t\t%d\nW2: sqb_aura \t\t\t%d", ctx->sq_int,
359 nix_dump("W2: smq_rr_count[ub:lb] \t\t%x:%x\n", ctx->smq_rr_count_ub,
360 ctx->smq_rr_count_lb);
362 nix_dump("W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d",
363 ctx->smq_next_sq_vld, ctx->smq_pend);
364 nix_dump("W3: smenq_next_sqb_vld \t%d\nW3: head_offset\t\t\t%d",
365 ctx->smenq_next_sqb_vld, ctx->head_offset);
366 nix_dump("W3: smenq_offset\t\t%d\nW3: tail_offset \t\t%d",
367 ctx->smenq_offset, ctx->tail_offset);
368 nix_dump("W3: smq_lso_segnum \t\t%d\nW3: smq_next_sq \t\t%d",
369 ctx->smq_lso_segnum, ctx->smq_next_sq);
370 nix_dump("W3: mnq_dis \t\t\t%d\nW3: lmt_dis \t\t\t%d", ctx->mnq_dis,
372 nix_dump("W3: cq_limit\t\t\t%d\nW3: max_sqe_size\t\t%d\n",
373 ctx->cq_limit, ctx->max_sqe_size);
375 nix_dump("W4: next_sqb \t\t\t0x%" PRIx64 "", ctx->next_sqb);
376 nix_dump("W5: tail_sqb \t\t\t0x%" PRIx64 "", ctx->tail_sqb);
377 nix_dump("W6: smenq_sqb \t\t\t0x%" PRIx64 "", ctx->smenq_sqb);
378 nix_dump("W7: smenq_next_sqb \t\t0x%" PRIx64 "", ctx->smenq_next_sqb);
379 nix_dump("W8: head_sqb \t\t\t0x%" PRIx64 "", ctx->head_sqb);
381 nix_dump("W9: vfi_lso_vld \t\t%d\nW9: vfi_lso_vlan1_ins_ena\t%d",
382 ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena);
383 nix_dump("W9: vfi_lso_vlan0_ins_ena\t%d\nW9: vfi_lso_mps\t\t\t%d",
384 ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps);
385 nix_dump("W9: vfi_lso_sb \t\t\t%d\nW9: vfi_lso_sizem1\t\t%d",
386 ctx->vfi_lso_sb, ctx->vfi_lso_sizem1);
387 nix_dump("W9: vfi_lso_total\t\t%d", ctx->vfi_lso_total);
389 nix_dump("W10: scm_lso_rem \t\t0x%" PRIx64 "",
390 (uint64_t)ctx->scm_lso_rem);
391 nix_dump("W11: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
392 nix_dump("W12: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
393 nix_dump("W14: dropped_octs \t\t0x%" PRIx64 "",
394 (uint64_t)ctx->drop_octs);
395 nix_dump("W15: dropped_pkts \t\t0x%" PRIx64 "",
396 (uint64_t)ctx->drop_pkts);
398 *sqb_aura_p = ctx->sqb_aura;
402 nix_cn9k_lf_rq_dump(__io struct nix_rq_ctx_s *ctx)
404 nix_dump("W0: wqe_aura \t\t\t%d\nW0: substream \t\t\t0x%03x",
405 ctx->wqe_aura, ctx->substream);
406 nix_dump("W0: cq \t\t\t\t%d\nW0: ena_wqwd \t\t\t%d", ctx->cq,
408 nix_dump("W0: ipsech_ena \t\t\t%d\nW0: sso_ena \t\t\t%d",
409 ctx->ipsech_ena, ctx->sso_ena);
410 nix_dump("W0: ena \t\t\t%d\n", ctx->ena);
412 nix_dump("W1: lpb_drop_ena \t\t%d\nW1: spb_drop_ena \t\t%d",
413 ctx->lpb_drop_ena, ctx->spb_drop_ena);
414 nix_dump("W1: xqe_drop_ena \t\t%d\nW1: wqe_caching \t\t%d",
415 ctx->xqe_drop_ena, ctx->wqe_caching);
416 nix_dump("W1: pb_caching \t\t\t%d\nW1: sso_tt \t\t\t%d",
417 ctx->pb_caching, ctx->sso_tt);
418 nix_dump("W1: sso_grp \t\t\t%d\nW1: lpb_aura \t\t\t%d", ctx->sso_grp,
420 nix_dump("W1: spb_aura \t\t\t%d\n", ctx->spb_aura);
422 nix_dump("W2: xqe_hdr_split \t\t%d\nW2: xqe_imm_copy \t\t%d",
423 ctx->xqe_hdr_split, ctx->xqe_imm_copy);
424 nix_dump("W2: xqe_imm_size \t\t%d\nW2: later_skip \t\t\t%d",
425 ctx->xqe_imm_size, ctx->later_skip);
426 nix_dump("W2: first_skip \t\t\t%d\nW2: lpb_sizem1 \t\t\t%d",
427 ctx->first_skip, ctx->lpb_sizem1);
428 nix_dump("W2: spb_ena \t\t\t%d\nW2: wqe_skip \t\t\t%d", ctx->spb_ena,
430 nix_dump("W2: spb_sizem1 \t\t\t%d\n", ctx->spb_sizem1);
432 nix_dump("W3: spb_pool_pass \t\t%d\nW3: spb_pool_drop \t\t%d",
433 ctx->spb_pool_pass, ctx->spb_pool_drop);
434 nix_dump("W3: spb_aura_pass \t\t%d\nW3: spb_aura_drop \t\t%d",
435 ctx->spb_aura_pass, ctx->spb_aura_drop);
436 nix_dump("W3: wqe_pool_pass \t\t%d\nW3: wqe_pool_drop \t\t%d",
437 ctx->wqe_pool_pass, ctx->wqe_pool_drop);
438 nix_dump("W3: xqe_pass \t\t\t%d\nW3: xqe_drop \t\t\t%d\n",
439 ctx->xqe_pass, ctx->xqe_drop);
441 nix_dump("W4: qint_idx \t\t\t%d\nW4: rq_int_ena \t\t\t%d",
442 ctx->qint_idx, ctx->rq_int_ena);
443 nix_dump("W4: rq_int \t\t\t%d\nW4: lpb_pool_pass \t\t%d", ctx->rq_int,
445 nix_dump("W4: lpb_pool_drop \t\t%d\nW4: lpb_aura_pass \t\t%d",
446 ctx->lpb_pool_drop, ctx->lpb_aura_pass);
447 nix_dump("W4: lpb_aura_drop \t\t%d\n", ctx->lpb_aura_drop);
449 nix_dump("W5: flow_tagw \t\t\t%d\nW5: bad_utag \t\t\t%d",
450 ctx->flow_tagw, ctx->bad_utag);
451 nix_dump("W5: good_utag \t\t\t%d\nW5: ltag \t\t\t%d\n", ctx->good_utag,
454 nix_dump("W6: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
455 nix_dump("W7: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
456 nix_dump("W8: drop_octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_octs);
457 nix_dump("W9: drop_pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_pkts);
458 nix_dump("W10: re_pkts \t\t\t0x%" PRIx64 "\n", (uint64_t)ctx->re_pkts);
462 nix_lf_rq_dump(__io struct nix_cn10k_rq_ctx_s *ctx)
464 nix_dump("W0: wqe_aura \t\t\t%d\nW0: len_ol3_dis \t\t\t%d",
465 ctx->wqe_aura, ctx->len_ol3_dis);
466 nix_dump("W0: len_ol4_dis \t\t\t%d\nW0: len_il3_dis \t\t\t%d",
467 ctx->len_ol4_dis, ctx->len_il3_dis);
468 nix_dump("W0: len_il4_dis \t\t\t%d\nW0: csum_ol4_dis \t\t\t%d",
469 ctx->len_il4_dis, ctx->csum_ol4_dis);
470 nix_dump("W0: csum_ol3_dis \t\t\t%d\nW0: lenerr_dis \t\t\t%d",
471 ctx->csum_ol4_dis, ctx->lenerr_dis);
472 nix_dump("W0: cq \t\t\t\t%d\nW0: ena_wqwd \t\t\t%d", ctx->cq,
474 nix_dump("W0: ipsech_ena \t\t\t%d\nW0: sso_ena \t\t\t%d",
475 ctx->ipsech_ena, ctx->sso_ena);
476 nix_dump("W0: ena \t\t\t%d\n", ctx->ena);
478 nix_dump("W1: chi_ena \t\t%d\nW1: ipsecd_drop_en \t\t%d", ctx->chi_ena,
479 ctx->ipsecd_drop_en);
480 nix_dump("W1: pb_stashing \t\t\t%d", ctx->pb_stashing);
481 nix_dump("W1: lpb_drop_ena \t\t%d\nW1: spb_drop_ena \t\t%d",
482 ctx->lpb_drop_ena, ctx->spb_drop_ena);
483 nix_dump("W1: xqe_drop_ena \t\t%d\nW1: wqe_caching \t\t%d",
484 ctx->xqe_drop_ena, ctx->wqe_caching);
485 nix_dump("W1: pb_caching \t\t\t%d\nW1: sso_tt \t\t\t%d",
486 ctx->pb_caching, ctx->sso_tt);
487 nix_dump("W1: sso_grp \t\t\t%d\nW1: lpb_aura \t\t\t%d", ctx->sso_grp,
489 nix_dump("W1: spb_aura \t\t\t%d\n", ctx->spb_aura);
491 nix_dump("W2: xqe_hdr_split \t\t%d\nW2: xqe_imm_copy \t\t%d",
492 ctx->xqe_hdr_split, ctx->xqe_imm_copy);
493 nix_dump("W2: xqe_imm_size \t\t%d\nW2: later_skip \t\t\t%d",
494 ctx->xqe_imm_size, ctx->later_skip);
495 nix_dump("W2: first_skip \t\t\t%d\nW2: lpb_sizem1 \t\t\t%d",
496 ctx->first_skip, ctx->lpb_sizem1);
497 nix_dump("W2: spb_ena \t\t\t%d\nW2: wqe_skip \t\t\t%d", ctx->spb_ena,
499 nix_dump("W2: spb_sizem1 \t\t\t%d\nW2: policer_ena \t\t\t%d",
500 ctx->spb_sizem1, ctx->policer_ena);
501 nix_dump("W2: band_prof_id \t\t\t%d", ctx->band_prof_id);
503 nix_dump("W3: spb_pool_pass \t\t%d\nW3: spb_pool_drop \t\t%d",
504 ctx->spb_pool_pass, ctx->spb_pool_drop);
505 nix_dump("W3: spb_aura_pass \t\t%d\nW3: spb_aura_drop \t\t%d",
506 ctx->spb_aura_pass, ctx->spb_aura_drop);
507 nix_dump("W3: wqe_pool_pass \t\t%d\nW3: wqe_pool_drop \t\t%d",
508 ctx->wqe_pool_pass, ctx->wqe_pool_drop);
509 nix_dump("W3: xqe_pass \t\t\t%d\nW3: xqe_drop \t\t\t%d\n",
510 ctx->xqe_pass, ctx->xqe_drop);
512 nix_dump("W4: qint_idx \t\t\t%d\nW4: rq_int_ena \t\t\t%d",
513 ctx->qint_idx, ctx->rq_int_ena);
514 nix_dump("W4: rq_int \t\t\t%d\nW4: lpb_pool_pass \t\t%d", ctx->rq_int,
516 nix_dump("W4: lpb_pool_drop \t\t%d\nW4: lpb_aura_pass \t\t%d",
517 ctx->lpb_pool_drop, ctx->lpb_aura_pass);
518 nix_dump("W4: lpb_aura_drop \t\t%d\n", ctx->lpb_aura_drop);
520 nix_dump("W5: vwqe_skip \t\t\t%d\nW5: max_vsize_exp \t\t\t%d",
521 ctx->vwqe_skip, ctx->max_vsize_exp);
522 nix_dump("W5: vtime_wait \t\t\t%d\nW5: vwqe_ena \t\t\t%d",
523 ctx->vtime_wait, ctx->max_vsize_exp);
524 nix_dump("W5: ipsec_vwqe \t\t\t%d", ctx->ipsec_vwqe);
525 nix_dump("W5: flow_tagw \t\t\t%d\nW5: bad_utag \t\t\t%d",
526 ctx->flow_tagw, ctx->bad_utag);
527 nix_dump("W5: good_utag \t\t\t%d\nW5: ltag \t\t\t%d\n", ctx->good_utag,
530 nix_dump("W6: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
531 nix_dump("W7: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
532 nix_dump("W8: drop_octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_octs);
533 nix_dump("W9: drop_pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_pkts);
534 nix_dump("W10: re_pkts \t\t\t0x%" PRIx64 "\n", (uint64_t)ctx->re_pkts);
538 nix_lf_cq_dump(__io struct nix_cq_ctx_s *ctx)
540 nix_dump("W0: base \t\t\t0x%" PRIx64 "\n", ctx->base);
542 nix_dump("W1: wrptr \t\t\t%" PRIx64 "", (uint64_t)ctx->wrptr);
543 nix_dump("W1: avg_con \t\t\t%d\nW1: cint_idx \t\t\t%d", ctx->avg_con,
545 nix_dump("W1: cq_err \t\t\t%d\nW1: qint_idx \t\t\t%d", ctx->cq_err,
547 nix_dump("W1: bpid \t\t\t%d\nW1: bp_ena \t\t\t%d\n", ctx->bpid,
550 nix_dump("W2: update_time \t\t%d\nW2: avg_level \t\t\t%d",
551 ctx->update_time, ctx->avg_level);
552 nix_dump("W2: head \t\t\t%d\nW2: tail \t\t\t%d\n", ctx->head,
555 nix_dump("W3: cq_err_int_ena \t\t%d\nW3: cq_err_int \t\t\t%d",
556 ctx->cq_err_int_ena, ctx->cq_err_int);
557 nix_dump("W3: qsize \t\t\t%d\nW3: caching \t\t\t%d", ctx->qsize,
559 nix_dump("W3: substream \t\t\t0x%03x\nW3: ena \t\t\t%d", ctx->substream,
561 nix_dump("W3: drop_ena \t\t\t%d\nW3: drop \t\t\t%d", ctx->drop_ena,
563 nix_dump("W3: bp \t\t\t\t%d\n", ctx->bp);
567 roc_nix_queues_ctx_dump(struct roc_nix *roc_nix)
569 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
570 int rc = -1, q, rq = nix->nb_rx_queues;
571 struct mbox *mbox = (&nix->dev)->mbox;
572 struct npa_aq_enq_rsp *npa_rsp;
573 struct npa_aq_enq_req *npa_aq;
575 int sq = nix->nb_tx_queues;
576 struct npa_lf *npa_lf;
579 npa_lf = idev_npa_obj_get();
581 return NPA_ERR_DEVICE_NOT_BOUNDED;
583 for (q = 0; q < rq; q++) {
584 rc = nix_q_ctx_get(mbox, NIX_AQ_CTYPE_CQ, q, &ctx);
586 plt_err("Failed to get cq context");
589 nix_dump("============== port=%d cq=%d ===============",
590 roc_nix->port_id, q);
594 for (q = 0; q < rq; q++) {
595 rc = nix_q_ctx_get(mbox, NIX_AQ_CTYPE_RQ, q, &ctx);
597 plt_err("Failed to get rq context");
600 nix_dump("============== port=%d rq=%d ===============",
601 roc_nix->port_id, q);
602 if (roc_model_is_cn9k())
603 nix_cn9k_lf_rq_dump(ctx);
608 for (q = 0; q < sq; q++) {
609 rc = nix_q_ctx_get(mbox, NIX_AQ_CTYPE_SQ, q, &ctx);
611 plt_err("Failed to get sq context");
614 nix_dump("============== port=%d sq=%d ===============",
615 roc_nix->port_id, q);
616 if (roc_model_is_cn9k())
617 nix_cn9k_lf_sq_dump(ctx, &sqb_aura);
619 nix_lf_sq_dump(ctx, &sqb_aura);
622 plt_err("NPA LF does not exist");
626 /* Dump SQB Aura minimal info */
627 npa_aq = mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
630 npa_aq->aura_id = sqb_aura;
631 npa_aq->ctype = NPA_AQ_CTYPE_AURA;
632 npa_aq->op = NPA_AQ_INSTOP_READ;
634 rc = mbox_process_msg(npa_lf->mbox, (void *)&npa_rsp);
636 plt_err("Failed to get sq's sqb_aura context");
640 nix_dump("\nSQB Aura W0: Pool addr\t\t0x%" PRIx64 "",
641 npa_rsp->aura.pool_addr);
642 nix_dump("SQB Aura W1: ena\t\t\t%d", npa_rsp->aura.ena);
643 nix_dump("SQB Aura W2: count\t\t%" PRIx64 "",
644 (uint64_t)npa_rsp->aura.count);
645 nix_dump("SQB Aura W3: limit\t\t%" PRIx64 "",
646 (uint64_t)npa_rsp->aura.limit);
647 nix_dump("SQB Aura W3: fc_ena\t\t%d", npa_rsp->aura.fc_ena);
648 nix_dump("SQB Aura W4: fc_addr\t\t0x%" PRIx64 "\n",
649 npa_rsp->aura.fc_addr);
656 /* Dumps struct nix_cqe_hdr_s and union nix_rx_parse_u */
658 roc_nix_cqe_dump(const struct nix_cqe_hdr_s *cq)
660 const union nix_rx_parse_u *rx =
661 (const union nix_rx_parse_u *)((const uint64_t *)cq + 1);
663 nix_dump("tag \t\t0x%x\tq \t\t%d\t\tnode \t\t%d\tcqe_type \t%d",
664 cq->tag, cq->q, cq->node, cq->cqe_type);
666 nix_dump("W0: chan \t%d\t\tdesc_sizem1 \t%d", rx->chan,
668 nix_dump("W0: imm_copy \t%d\t\texpress \t%d", rx->imm_copy,
670 nix_dump("W0: wqwd \t%d\t\terrlev \t\t%d\t\terrcode \t%d", rx->wqwd,
671 rx->errlev, rx->errcode);
672 nix_dump("W0: latype \t%d\t\tlbtype \t\t%d\t\tlctype \t\t%d",
673 rx->latype, rx->lbtype, rx->lctype);
674 nix_dump("W0: ldtype \t%d\t\tletype \t\t%d\t\tlftype \t\t%d",
675 rx->ldtype, rx->letype, rx->lftype);
676 nix_dump("W0: lgtype \t%d \t\tlhtype \t\t%d", rx->lgtype, rx->lhtype);
678 nix_dump("W1: pkt_lenm1 \t%d", rx->pkt_lenm1);
679 nix_dump("W1: l2m \t%d\t\tl2b \t\t%d\t\tl3m \t\t%d\tl3b \t\t%d",
680 rx->l2m, rx->l2b, rx->l3m, rx->l3b);
681 nix_dump("W1: vtag0_valid %d\t\tvtag0_gone \t%d", rx->vtag0_valid,
683 nix_dump("W1: vtag1_valid %d\t\tvtag1_gone \t%d", rx->vtag1_valid,
685 nix_dump("W1: pkind \t%d", rx->pkind);
686 nix_dump("W1: vtag0_tci \t%d\t\tvtag1_tci \t%d", rx->vtag0_tci,
689 nix_dump("W2: laflags \t%d\t\tlbflags\t\t%d\t\tlcflags \t%d",
690 rx->laflags, rx->lbflags, rx->lcflags);
691 nix_dump("W2: ldflags \t%d\t\tleflags\t\t%d\t\tlfflags \t%d",
692 rx->ldflags, rx->leflags, rx->lfflags);
693 nix_dump("W2: lgflags \t%d\t\tlhflags \t%d", rx->lgflags, rx->lhflags);
695 nix_dump("W3: eoh_ptr \t%d\t\twqe_aura \t%d\t\tpb_aura \t%d",
696 rx->eoh_ptr, rx->wqe_aura, rx->pb_aura);
697 nix_dump("W3: match_id \t%d", rx->match_id);
699 nix_dump("W4: laptr \t%d\t\tlbptr \t\t%d\t\tlcptr \t\t%d", rx->laptr,
700 rx->lbptr, rx->lcptr);
701 nix_dump("W4: ldptr \t%d\t\tleptr \t\t%d\t\tlfptr \t\t%d", rx->ldptr,
702 rx->leptr, rx->lfptr);
703 nix_dump("W4: lgptr \t%d\t\tlhptr \t\t%d", rx->lgptr, rx->lhptr);
705 nix_dump("W5: vtag0_ptr \t%d\t\tvtag1_ptr \t%d\t\tflow_key_alg \t%d",
706 rx->vtag0_ptr, rx->vtag1_ptr, rx->flow_key_alg);
710 roc_nix_rq_dump(struct roc_nix_rq *rq)
712 nix_dump("nix_rq@%p", rq);
713 nix_dump(" qid = %d", rq->qid);
714 nix_dump(" aura_handle = 0x%" PRIx64 "", rq->aura_handle);
715 nix_dump(" ipsec_ena = %d", rq->ipsech_ena);
716 nix_dump(" first_skip = %d", rq->first_skip);
717 nix_dump(" later_skip = %d", rq->later_skip);
718 nix_dump(" lpb_size = %d", rq->lpb_size);
719 nix_dump(" sso_ena = %d", rq->sso_ena);
720 nix_dump(" tag_mask = %d", rq->tag_mask);
721 nix_dump(" flow_tag_width = %d", rq->flow_tag_width);
722 nix_dump(" tt = %d", rq->tt);
723 nix_dump(" hwgrp = %d", rq->hwgrp);
724 nix_dump(" vwqe_ena = %d", rq->vwqe_ena);
725 nix_dump(" vwqe_first_skip = %d", rq->vwqe_first_skip);
726 nix_dump(" vwqe_max_sz_exp = %d", rq->vwqe_max_sz_exp);
727 nix_dump(" vwqe_wait_tmo = %ld", rq->vwqe_wait_tmo);
728 nix_dump(" vwqe_aura_handle = %ld", rq->vwqe_aura_handle);
729 nix_dump(" roc_nix = %p", rq->roc_nix);
733 roc_nix_cq_dump(struct roc_nix_cq *cq)
735 nix_dump("nix_cq@%p", cq);
736 nix_dump(" qid = %d", cq->qid);
737 nix_dump(" qnb_desc = %d", cq->nb_desc);
738 nix_dump(" roc_nix = %p", cq->roc_nix);
739 nix_dump(" door = 0x%" PRIx64 "", cq->door);
740 nix_dump(" status = %p", cq->status);
741 nix_dump(" wdata = 0x%" PRIx64 "", cq->wdata);
742 nix_dump(" desc_base = %p", cq->desc_base);
743 nix_dump(" qmask = 0x%" PRIx32 "", cq->qmask);
747 roc_nix_sq_dump(struct roc_nix_sq *sq)
749 nix_dump("nix_sq@%p", sq);
750 nix_dump(" qid = %d", sq->qid);
751 nix_dump(" max_sqe_sz = %d", sq->max_sqe_sz);
752 nix_dump(" nb_desc = %d", sq->nb_desc);
753 nix_dump(" sqes_per_sqb_log2 = %d", sq->sqes_per_sqb_log2);
754 nix_dump(" roc_nix= %p", sq->roc_nix);
755 nix_dump(" aura_handle = 0x%" PRIx64 "", sq->aura_handle);
756 nix_dump(" nb_sqb_bufs_adj = %d", sq->nb_sqb_bufs_adj);
757 nix_dump(" nb_sqb_bufs = %d", sq->nb_sqb_bufs);
758 nix_dump(" io_addr = 0x%" PRIx64 "", sq->io_addr);
759 nix_dump(" lmt_addr = %p", sq->lmt_addr);
760 nix_dump(" sqe_mem = %p", sq->sqe_mem);
761 nix_dump(" fc = %p", sq->fc);
765 roc_nix_dump(struct roc_nix *roc_nix)
767 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
768 struct dev *dev = &nix->dev;
770 nix_dump("nix@%p", nix);
771 nix_dump(" pf = %d", dev_get_pf(dev->pf_func));
772 nix_dump(" vf = %d", dev_get_vf(dev->pf_func));
773 nix_dump(" bar2 = 0x%" PRIx64, dev->bar2);
774 nix_dump(" bar4 = 0x%" PRIx64, dev->bar4);
775 nix_dump(" port_id = %d", roc_nix->port_id);
776 nix_dump(" rss_tag_as_xor = %d", roc_nix->rss_tag_as_xor);
777 nix_dump(" rss_tag_as_xor = %d", roc_nix->max_sqb_count);
779 nix_dump(" \tpci_dev = %p", nix->pci_dev);
780 nix_dump(" \tbase = 0x%" PRIxPTR "", nix->base);
781 nix_dump(" \tlmt_base = 0x%" PRIxPTR "", nix->lmt_base);
782 nix_dump(" \treta_size = %d", nix->reta_sz);
783 nix_dump(" \ttx_chan_base = %d", nix->tx_chan_base);
784 nix_dump(" \trx_chan_base = %d", nix->rx_chan_base);
785 nix_dump(" \tnb_rx_queues = %d", nix->nb_rx_queues);
786 nix_dump(" \tnb_tx_queues = %d", nix->nb_tx_queues);
787 nix_dump(" \tlso_tsov6_idx = %d", nix->lso_tsov6_idx);
788 nix_dump(" \tlso_tsov4_idx = %d", nix->lso_tsov4_idx);
789 nix_dump(" \tlf_rx_stats = %d", nix->lf_rx_stats);
790 nix_dump(" \tlf_tx_stats = %d", nix->lf_tx_stats);
791 nix_dump(" \trx_chan_cnt = %d", nix->rx_chan_cnt);
792 nix_dump(" \ttx_chan_cnt = %d", nix->tx_chan_cnt);
793 nix_dump(" \tcgx_links = %d", nix->cgx_links);
794 nix_dump(" \tlbk_links = %d", nix->lbk_links);
795 nix_dump(" \tsdp_links = %d", nix->sdp_links);
796 nix_dump(" \ttx_link = %d", nix->tx_link);
797 nix_dump(" \tsqb_size = %d", nix->sqb_size);
798 nix_dump(" \tmsixoff = %d", nix->msixoff);
799 nix_dump(" \tcints = %d", nix->cints);
800 nix_dump(" \tqints = %d", nix->qints);
801 nix_dump(" \tsdp_link = %d", nix->sdp_link);
802 nix_dump(" \tptp_en = %d", nix->ptp_en);
803 nix_dump(" \trss_alg_idx = %d", nix->rss_alg_idx);
804 nix_dump(" \ttx_pause = %d", nix->tx_pause);